| Run orig_default | Run icx_default | Run gcc_default | Run aocc_6 | Run icx_7 | Run gcc_6 |
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-31
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5494/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
|
| ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s |
| 5 | 0.01 | 0.00 | 0.02 | 100 | 29.1 | 1360.3 | 4 | 3.43 | 2.88 | 55.45 | 100 | 91.25 | 7878.55 | 3 | 2.92 | 2.68 | 46.97 | 100 | 91.46 | 8374.35 | 5 | 0.01 | 0.00 | 0.02 | 100 | 29.1 | 1467.38 | 4 | 3.37 | 2.84 | 55.89 | 100 | 91.25 | 7995.07 | 3 | 0.02 | 0.00 | 0.04 | 6.45 | 8.47 | 1331.99 |
| | | | | 4 | 3.46 | 2.85 | 47.57 | 100 | 91.46 | 7700.72 |
| | | | | |
| Sum on 1 analyzed binary loop (exec - 5) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 3) | Sum on 1 analyzed binary loop (exec - 5) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 2 analyzed binary loops (exec - 3, exec - 4) |
| Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count |
| Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | |
| Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 |
| Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | |
| Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | |
| More than 10% of the vector loads instructions are unaligned | | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 1 |
| Presence of special instructions executing on a single port | | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 |
| Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | |
| Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | |
| Presence of special instructions executing on a single port | 0 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 0 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 |
| Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 |