| Run orig_default | Run aocc_default | Run gcc_default | Run icx_3 | Run aocc_6 | Run gcc_2 |
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5529/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5529/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5529/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-31
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5529/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5529/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-654-5529/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19-31
|
| ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s |
| 4 | 7.02 | 6.83 | 80.40 | 100 | 45.63 | 3401.41 | 4 | 22.37 | 21.59 | 91.97 | 41.24 | 14.37 | 1215.17 | 3 | 7.03 | 6.68 | 76.93 | 100 | 45.73 | 3366.41 | 11 | 7.03 | 6.81 | 79.01 | 100 | 45.63 | 3411.3 | 4 | 7.14 | 6.73 | 80.69 | 100 | 29.17 | 3454.37 | 4 | 6.96 | 6.64 | 77.07 | 100 | 91.46 | 3380.27 |
| | | | | |
| Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 3) | Sum on 1 analyzed binary loop (exec - 11) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 4) |
| Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count |
| Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | |
| Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 |
| Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 1 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 |
| Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | |
| Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | |
| More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 0 | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | | More than 10% of the vector loads instructions are unaligned | 0 |
| Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | | Presence of special instructions executing on a single port | 1 |
| Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | |
| Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | |
| Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 0 | Presence of special instructions executing on a single port | 1 |
| Use of masked instructions | 1 | Use of masked instructions | 0 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 |