OV - exec - Loop 935

	Loop Id: 935	Module: exec	Source: MultiBsplineRef.hpp:68-71	Coverage: 25.78%

0x47d850 VMULPD	(%R10,%RCX,1),%YMM5,%YMM8    [1]

0x47d856 VMULPD	(%R12,%RCX,1),%YMM13,%YMM28    [3]

0x47d85d VFMADD231PD	(%RAX,%RCX,1),%YMM6,%YMM8    [8]

0x47d863 VFMADD231PD	(%RSI,%RCX,1),%YMM4,%YMM28    [6]

0x47d86a VADDPD	%YMM28,%YMM8,%YMM0

0x47d870 VMULPD	(%R14,%RCX,1),%YMM5,%YMM26    [4]

0x47d877 VMULPD	(%R15,%RCX,1),%YMM13,%YMM1    [5]

0x47d87d VFMADD231PD	(%RDX,%RCX,1),%YMM6,%YMM26    [10]

0x47d884 VMULPD	0x20(%RCX,%R10,1),%YMM5,%YMM8    [2]

0x47d88b VFMADD231PD	(%R13,%RCX,1),%YMM4,%YMM1    [7]

0x47d892 VADDPD	%YMM1,%YMM26,%YMM27

0x47d898 VFMADD213PD	(%RBX,%RCX,1),%YMM9,%YMM27    [9]

0x47d89f VMULPD	0x20(%R12,%RCX,1),%YMM13,%YMM30    [3]

0x47d8a7 VFMADD132PD	%YMM7,%YMM27,%YMM0

0x47d8ad VFMADD231PD	0x20(%RCX,%RAX,1),%YMM6,%YMM8    [2]

0x47d8b4 VFMADD231PD	0x20(%RSI,%RCX,1),%YMM4,%YMM30    [6]

0x47d8bc VMULPD	0x20(%R14,%RCX,1),%YMM5,%YMM3    [4]

0x47d8c3 VMULPD	0x20(%R15,%RCX,1),%YMM13,%YMM29    [5]

0x47d8cb VFMADD231PD	0x20(%RCX,%RDX,1),%YMM6,%YMM3    [2]

0x47d8d2 VFMADD231PD	0x20(%RCX,%R13,1),%YMM4,%YMM29    [2]

0x47d8da VADDPD	%YMM29,%YMM3,%YMM1

0x47d8e0 VFMADD213PD	0x20(%RBX,%RCX,1),%YMM9,%YMM1    [9]

0x47d8e7 VMOVUPD	%YMM0,(%RBX,%RCX,1)    [9]

0x47d8ec VADDPD	%YMM30,%YMM8,%YMM0

0x47d8f2 VFMADD132PD	%YMM7,%YMM1,%YMM0

0x47d8f7 VMOVUPD	%YMM0,0x20(%RBX,%RCX,1)    [9]

0x47d8fd ADD	$0x40,%RCX

0x47d901 CMP	%R8,%RCX

0x47d904 JNE	47d850

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 68 - 71

--------------------------------------------------------------------------------

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

Coverage (%)	Name	Source Location	Module
►49.32+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:178	exec
○	qmcplusplus::WaveFunction::eva[...]	allocator.h:161	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►47.25+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:178	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:68-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	3.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	10.00
P11 cycles	10.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	28.00
Nb loads	18.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	14.40
Nb FLOP add-sub	16.00
Nb FLOP mul	32.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	5.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source	MultiBsplineRef.hpp:68-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	3.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	10.00
P11 cycles	10.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	28.00
Nb loads	18.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	14.40
Nb FLOP add-sub	16.00
Nb FLOP mul	32.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	5.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:68-71
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:68-71.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 5.00 cycles (2.00x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

24 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

64: addition or subtraction (48 inside FMA instructions)
80: multiply (48 inside FMA instructions)

The binary loop is loading 576 bytes (72 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	29
nb uops	28
loop length	186
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	15
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	10.00	10.00	2.00	2.00	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	10.00	10.00	2.00	2.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

22% of peak load performance is reached (57.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 47d850

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD (%R10,%RCX,1),%YMM5,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD (%R12,%RCX,1),%YMM13,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%RAX,%RCX,1),%YMM6,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD (%RSI,%RCX,1),%YMM4,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM28,%YMM8,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R14,%RCX,1),%YMM5,%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD (%R15,%RCX,1),%YMM13,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%RDX,%RCX,1),%YMM6,%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%RCX,%R10,1),%YMM5,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%R13,%RCX,1),%YMM4,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM1,%YMM26,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD213PD (%RBX,%RCX,1),%YMM9,%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%R12,%RCX,1),%YMM13,%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM7,%YMM27,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x20(%RCX,%RAX,1),%YMM6,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x20(%RSI,%RCX,1),%YMM4,%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%R14,%RCX,1),%YMM5,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%R15,%RCX,1),%YMM13,%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x20(%RCX,%RDX,1),%YMM6,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x20(%RCX,%R13,1),%YMM4,%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM29,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD213PD 0x20(%RBX,%RCX,1),%YMM9,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%RBX,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VADDPD %YMM30,%YMM8,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD132PD %YMM7,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RBX,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x40,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 47d850 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)
Source file and lines	MultiBsplineRef.hpp:68-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

24 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

64: addition or subtraction (48 inside FMA instructions)
80: multiply (48 inside FMA instructions)

The binary loop is loading 576 bytes (72 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	29
nb uops	28
loop length	186
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	15
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	10.00	10.00	2.00	2.00	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	5.00	5.00	5.00	5.00	10.00	10.00	2.00	2.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

22% of peak load performance is reached (57.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 47d850

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD (%R10,%RCX,1),%YMM5,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD (%R12,%RCX,1),%YMM13,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%RAX,%RCX,1),%YMM6,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD (%RSI,%RCX,1),%YMM4,%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM28,%YMM8,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD (%R14,%RCX,1),%YMM5,%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD (%R15,%RCX,1),%YMM13,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%RDX,%RCX,1),%YMM6,%YMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%RCX,%R10,1),%YMM5,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD (%R13,%RCX,1),%YMM4,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM1,%YMM26,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD213PD (%RBX,%RCX,1),%YMM9,%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%R12,%RCX,1),%YMM13,%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM7,%YMM27,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x20(%RCX,%RAX,1),%YMM6,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x20(%RSI,%RCX,1),%YMM4,%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x20(%R14,%RCX,1),%YMM5,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%R15,%RCX,1),%YMM13,%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x20(%RCX,%RDX,1),%YMM6,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x20(%RCX,%R13,1),%YMM4,%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM29,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD213PD 0x20(%RBX,%RCX,1),%YMM9,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%RBX,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VADDPD %YMM30,%YMM8,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD132PD %YMM7,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,0x20(%RBX,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x40,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 47d850 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code