OV - exec - Loop 605

	Loop Id: 605	Module: exec	Source: TwoBodyJastrowRef.h:342-347	Coverage: 0.61%

0x457f62 VMOVUPD	(%R12,%RAX,1),%YMM14    [4]

0x457f68 VMOVUPD	(%RCX,%RAX,1),%YMM4    [7]

0x457f6d VMOVUPD	(%R15,%RAX,1),%YMM3    [1]

0x457f73 VMOVUPD	(%RSI,%RAX,1),%YMM9    [2]

0x457f78 VFMADD132PD	(%R14,%RAX,1),%YMM9,%YMM3    [5]

0x457f7e VMOVUPD	0x20(%RSI,%RAX,1),%YMM1    [2]

0x457f84 VFNMADD231PD	%YMM14,%YMM4,%YMM3

0x457f89 VFMADD231PD	%YMM14,%YMM4,%YMM0

0x457f8e VMOVUPD	%YMM3,(%RSI,%RAX,1)    [2]

0x457f93 VMOVUPD	0x20(%R12,%RAX,1),%YMM15    [4]

0x457f9a VMOVUPD	0x20(%RAX,%RCX,1),%YMM3    [6]

0x457fa0 VMOVUPD	0x20(%RAX,%R15,1),%YMM14    [6]

0x457fa7 VFMADD132PD	0x20(%R14,%RAX,1),%YMM1,%YMM14    [5]

0x457fae VMOVUPD	0x60(%RSI,%RAX,1),%YMM1    [2]

0x457fb4 VFNMADD231PD	%YMM15,%YMM3,%YMM14

0x457fb9 VFMADD132PD	%YMM15,%YMM0,%YMM3

0x457fbe VMOVUPD	0x40(%RSI,%RAX,1),%YMM15    [2]

0x457fc4 VMOVUPD	%YMM14,0x20(%RSI,%RAX,1)    [2]

0x457fca VMOVUPD	0x40(%R12,%RAX,1),%YMM9    [4]

0x457fd1 VMOVUPD	0x40(%RAX,%RCX,1),%YMM0    [6]

0x457fd7 VMOVUPD	0x40(%RAX,%R15,1),%YMM4    [6]

0x457fde VFMADD132PD	0x40(%R14,%RAX,1),%YMM15,%YMM4    [5]

0x457fe5 VFNMADD231PD	%YMM9,%YMM0,%YMM4

0x457fea VFMADD231PD	%YMM9,%YMM0,%YMM3

0x457fef VMOVUPD	%YMM4,0x40(%RSI,%RAX,1)    [2]

0x457ff5 VMOVUPD	0x60(%R12,%RAX,1),%YMM14    [4]

0x457ffc VMOVUPD	0x60(%RAX,%RCX,1),%YMM0    [6]

0x458002 VMOVUPD	0x60(%RAX,%R15,1),%YMM9    [6]

0x458009 VFMADD132PD	0x60(%R14,%RAX,1),%YMM1,%YMM9    [5]

0x458010 VFNMADD231PD	%YMM14,%YMM0,%YMM9

0x458015 VFMADD132PD	%YMM14,%YMM3,%YMM0

0x45801a VMOVUPD	%YMM9,0x60(%RSI,%RAX,1)    [2]

0x458020 SUB	$-0x80,%RAX

0x458024 CMP	%RAX,-0x58(%RBP)    [3]

0x458028 JNE	457f62

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 342 - 347

--------------------------------------------------------------------------------

342:     for (int jat = 0; jat < N; jat++)

343:     {

344:       const valT newg = cur_du_pt[jat] * new_dX[jat];

345:       const valT dg   = newg - old_du_pt[jat] * old_dX[jat];

346:       save_g[jat] -= dg;

347:       cur_g += newg;

Coverage (%)	Name	Source Location	Module
►96.67+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.56
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	13.03
CQA cycles if fully vectorized	8.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	6.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.50
Bytes prefetched	0.00
Bytes loaded	648.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	3.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.56
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	13.03
CQA cycles if fully vectorized	8.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	6.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.50
Bytes prefetched	0.00
Bytes loaded	648.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	3.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:342-347.

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

48: addition or subtraction (all inside FMA instructions)
48: multiply (all inside FMA instructions)

The binary loop is loading 648 bytes (81 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	34
loop length	204
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	7
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.25	6.25	6.25	6.25	6.00	6.00	0.00	0.00	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.25	6.25	6.25	6.25	6.00	6.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	4.25
Dispatch	6.25
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

15% of peak load performance is reached (40.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 457f62

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R12,%RAX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RCX,%RAX,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R15,%RAX,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RAX,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD (%R14,%RAX,1),%YMM9,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD 0x20(%RSI,%RAX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFNMADD231PD %YMM14,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM3,(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD 0x20(%R12,%RAX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RAX,%RCX,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RAX,%R15,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD 0x20(%R14,%RAX,1),%YMM1,%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD 0x60(%RSI,%RAX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFNMADD231PD %YMM15,%YMM3,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM15,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD 0x40(%RSI,%RAX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD 0x40(%R12,%RAX,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RAX,%RCX,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RAX,%R15,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD 0x40(%R14,%RAX,1),%YMM15,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFNMADD231PD %YMM9,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM4,0x40(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD 0x60(%R12,%RAX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%RAX,%RCX,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%RAX,%R15,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD 0x60(%R14,%RAX,1),%YMM1,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFNMADD231PD %YMM14,%YMM0,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM14,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM9,0x60(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
SUB $-0x80,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 457f62 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x572>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

48: addition or subtraction (all inside FMA instructions)
48: multiply (all inside FMA instructions)

The binary loop is loading 648 bytes (81 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	34
loop length	204
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	7
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.25	6.25	6.25	6.25	6.00	6.00	0.00	0.00	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.25	6.25	6.25	6.25	6.00	6.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	4.25
Dispatch	6.25
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

15% of peak load performance is reached (40.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 457f62

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R12,%RAX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RCX,%RAX,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R15,%RAX,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RSI,%RAX,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD (%R14,%RAX,1),%YMM9,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD 0x20(%RSI,%RAX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFNMADD231PD %YMM14,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM3,(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD 0x20(%R12,%RAX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RAX,%RCX,1),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RAX,%R15,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD 0x20(%R14,%RAX,1),%YMM1,%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD 0x60(%RSI,%RAX,1),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFNMADD231PD %YMM15,%YMM3,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM15,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD 0x40(%RSI,%RAX,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM14,0x20(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD 0x40(%R12,%RAX,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RAX,%RCX,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RAX,%R15,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD 0x40(%R14,%RAX,1),%YMM15,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFNMADD231PD %YMM9,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM4,0x40(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD 0x60(%R12,%RAX,1),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%RAX,%RCX,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%RAX,%R15,1),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD 0x60(%R14,%RAX,1),%YMM1,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFNMADD231PD %YMM14,%YMM0,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM14,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM9,0x60(%RSI,%RAX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
SUB $-0x80,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 457f62 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x572>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code