OV - exec - Loop 3088

	Loop Id: 3088	Module: exec	Source: SoaDistanceTableABOMPTarget.h:228-228 [...]	Coverage: 4.58%

0x5ba950 VMOVSD	(%R9,%RAX,8),%XMM3    [2]

0x5ba956 VMOVSD	(%R9,%RDI,1),%XMM4    [2]

0x5ba95c VSUBSD	%XMM7,%XMM3,%XMM0

0x5ba960 VMOVSD	(%R9,%R10,1),%XMM2    [2]

0x5ba966 VSUBSD	%XMM8,%XMM4,%XMM3

0x5ba96b VSUBSD	%XMM9,%XMM2,%XMM4

0x5ba970 VMULSD	%XMM26,%XMM3,%XMM2

0x5ba976 VFMADD231SD	%XMM27,%XMM0,%XMM2

0x5ba97c VMULSD	%XMM23,%XMM3,%XMM1

0x5ba982 VMULSD	%XMM20,%XMM3,%XMM3

0x5ba988 VFMADD231SD	%XMM24,%XMM0,%XMM1

0x5ba98e VFMADD132SD	%XMM21,%XMM3,%XMM0

0x5ba994 VFMADD231SD	%XMM25,%XMM4,%XMM2

0x5ba99a VFMADD231SD	%XMM22,%XMM4,%XMM1

0x5ba9a0 VFMADD132SD	%XMM19,%XMM0,%XMM4

0x5ba9a6 VMOVAPD	%XMM5,%XMM0

0x5ba9aa VPTERNLOGQ	$-0x8,%XMM6,%XMM2,%XMM0

0x5ba9b1 VMOVAPD	%XMM4,%XMM3

0x5ba9b5 VADDSD	%XMM0,%XMM2,%XMM4

0x5ba9b9 VRNDSCALESD	$0x3,%XMM4,%XMM4,%XMM0

0x5ba9c0 VSUBSD	%XMM0,%XMM2,%XMM2

0x5ba9c4 VMOVAPD	%XMM5,%XMM0

0x5ba9c8 VPTERNLOGQ	$-0x8,%XMM6,%XMM1,%XMM0

0x5ba9cf VADDSD	%XMM0,%XMM1,%XMM4

0x5ba9d3 VRNDSCALESD	$0x3,%XMM4,%XMM4,%XMM0

0x5ba9da VSUBSD	%XMM0,%XMM1,%XMM0

0x5ba9de VMOVAPD	%XMM5,%XMM1

0x5ba9e2 VPTERNLOGQ	$-0x8,%XMM6,%XMM3,%XMM1

0x5ba9e9 VADDSD	%XMM1,%XMM3,%XMM4

0x5ba9ed VRNDSCALESD	$0x3,%XMM4,%XMM4,%XMM1

0x5ba9f4 VSUBSD	%XMM1,%XMM3,%XMM4

0x5ba9f8 VMULSD	%XMM17,%XMM0,%XMM3

0x5ba9fe VMULSD	%XMM14,%XMM0,%XMM1

0x5baa03 VFMADD231SD	%XMM18,%XMM2,%XMM3

0x5baa09 VFMADD231SD	%XMM15,%XMM2,%XMM1

0x5baa0e VMULSD	%XMM11,%XMM0,%XMM0

0x5baa13 VFMADD231SD	%XMM12,%XMM2,%XMM0

0x5baa18 VFMADD231SD	%XMM16,%XMM4,%XMM3

0x5baa1e VFMADD231SD	%XMM13,%XMM4,%XMM1

0x5baa23 VFMADD231SD	%XMM10,%XMM4,%XMM0

0x5baa28 VMOVSD	%XMM3,(%RCX,%RAX,8)    [1]

0x5baa2d VMOVSD	%XMM1,(%RCX,%RDI,1)    [1]

0x5baa32 VMOVSD	%XMM0,(%RCX,%R10,1)    [1]

0x5baa38 VMOVSD	(%RCX,%RAX,8),%XMM4    [1]

0x5baa3d VMOVSD	(%RCX,%RDI,1),%XMM2    [1]

0x5baa42 VMULSD	%XMM2,%XMM2,%XMM3

0x5baa46 VFMADD132SD	%XMM4,%XMM3,%XMM4

0x5baa4b ADD	$0x8,%RDI

0x5baa4f ADD	$0x8,%R10

0x5baa53 VFMADD132SD	%XMM0,%XMM4,%XMM0

0x5baa58 VSQRTSD	%XMM0,%XMM0,%XMM0

0x5baa5c VMOVSD	%XMM0,(%RBX,%RAX,8)    [3]

0x5baa61 INC	%RAX

0x5baa64 CMP	%EAX,%R11D

0x5baa67 JG	5ba950

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

--------------------------------------------------------------------------------

280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 228 - 228

--------------------------------------------------------------------------------

228:           for (int iel = first; iel < last; iel++)

Coverage (%)	Name	Source Location	Module
►96.14+	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	4.29
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298,SoaDistanceTableABOMPTarget.h:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	2.56
CQA cycles if fully vectorized	1.38
Front-end cycles	6.75
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	5.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	4.09
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.55
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	14.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	70.00
Vector-efficiency ratio all	14.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	21.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	4.29
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:280-298,SoaDistanceTableABOMPTarget.h:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	2.56
CQA cycles if fully vectorized	1.38
Front-end cycles	6.75
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	5.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	4.09
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.55
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	14.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	70.00
Vector-efficiency ratio all	14.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	21.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	SoaDistanceTableABOMPTarget.h:228-228
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 1.37 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 45 FP arithmetical operations:

23: addition or subtraction (14 inside FMA instructions)
21: multiply (14 inside FMA instructions)
1: square root

The binary loop is loading 40 bytes (5 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.62 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	285
used x86 registers	7
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	2.25	2.25	2.25	2.25	11.00	11.00	7.50	7.50	2.00	2.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	2.25	2.25	2.25	2.25	11.00	11.00	7.50	7.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	57%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	70%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	19%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

1% of peak load performance is reached (3.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5ba950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R9,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%RDI,1),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R9,%R10,1),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM8,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM26,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM27,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM20,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM21,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM22,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM19,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM6,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVAPD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM0,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM6,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM0,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM6,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM17,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM18,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM15,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM16,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM10,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,(%RCX,%RDI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX,%RDI,1),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM4,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMOVSD %XMM0,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 5ba950 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x670>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	SoaDistanceTableABOMPTarget.h:228-228
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 45 FP arithmetical operations:

23: addition or subtraction (14 inside FMA instructions)
21: multiply (14 inside FMA instructions)
1: square root

The binary loop is loading 40 bytes (5 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.62 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	285
used x86 registers	7
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	2.25	2.25	2.25	2.25	11.00	11.00	7.50	7.50	2.00	2.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	2.25	2.25	2.25	2.25	11.00	11.00	7.50	7.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	57%

INT+FP

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	70%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	19%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

1% of peak load performance is reached (3.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5ba950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R9,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%RDI,1),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD (%R9,%R10,1),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD %XMM8,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM9,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM26,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM27,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM23,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM20,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM24,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM21,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM25,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM22,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM19,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM6,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVAPD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM0,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM6,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM0,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM6,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM17,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM18,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM15,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM16,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM10,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,(%RCX,%RDI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX,%RDI,1),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD %XMM4,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
VMOVSD %XMM0,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EAX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 5ba950 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x670>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code