OV - exec - Loop 2596

	Loop Id: 2596	Module: exec	Source: ParticleBConds3DSoa.h:237-255	Coverage: 0.16%

0x5704e0 VMOVAPD	(%R11,%R10,1),%YMM4    [2]

0x5704e6 VMOVAPD	(%R12,%R10,1),%YMM7    [4]

0x5704ec VMOVAPD	(%RDI,%R10,1),%YMM0    [1]

0x5704f2 VSUBPD	%YMM9,%YMM4,%YMM12

0x5704f7 VSUBPD	%YMM10,%YMM7,%YMM14

0x5704fc VSUBPD	%YMM8,%YMM0,%YMM0

0x570501 VMULPD	0x168(%RBX){1to4},%YMM12,%YMM15    [6]

0x570508 VMULPD	0x180(%RBX){1to4},%YMM12,%YMM7    [6]

0x57050f VMULPD	0x198(%RBX){1to4},%YMM12,%YMM13    [6]

0x570516 VFMADD231PD	0x160(%RBX){1to4},%YMM14,%YMM15    [6]

0x57051d VFMADD231PD	0x178(%RBX){1to4},%YMM14,%YMM7    [6]

0x570524 VFMADD231PD	0x190(%RBX){1to4},%YMM14,%YMM13    [6]

0x57052b VMOVAPD	%YMM6,%YMM14

0x57052f VFMADD231PD	0x170(%RBX){1to4},%YMM0,%YMM15    [6]

0x570536 VFMADD231PD	0x188(%RBX){1to4},%YMM0,%YMM7    [6]

0x57053d VFMADD132PD	0x1a0(%RBX){1to4},%YMM13,%YMM0    [6]

0x570544 VMOVAPD	%YMM6,%YMM13

0x570548 VPTERNLOGQ	$-0x8,%YMM5,%YMM15,%YMM14

0x57054f VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM13

0x570556 VADDPD	%YMM14,%YMM15,%YMM4

0x57055b VADDPD	%YMM13,%YMM7,%YMM14

0x570560 VRNDSCALEPD	$0x3,%YMM4,%YMM12

0x570567 VRNDSCALEPD	$0x3,%YMM14,%YMM4

0x57056e VSUBPD	%YMM12,%YMM15,%YMM15

0x570573 VMOVAPD	%YMM6,%YMM12

0x570577 VPTERNLOGQ	$-0x8,%YMM5,%YMM0,%YMM12

0x57057e VADDPD	%YMM12,%YMM0,%YMM13

0x570583 VSUBPD	%YMM4,%YMM7,%YMM7

0x570587 VRNDSCALEPD	$0x3,%YMM13,%YMM14

0x57058e VMULPD	0x120(%RBX){1to4},%YMM7,%YMM4    [6]

0x570595 VFMADD231PD	0x118(%RBX){1to4},%YMM15,%YMM4    [6]

0x57059c VSUBPD	%YMM14,%YMM0,%YMM0

0x5705a1 VFMADD231PD	0x128(%RBX){1to4},%YMM0,%YMM4    [6]

0x5705a8 VMOVAPD	%YMM4,(%RCX,%R10,1)    [7]

0x5705ae VMULPD	0x138(%RBX){1to4},%YMM7,%YMM12    [6]

0x5705b5 VFMADD231PD	0x130(%RBX){1to4},%YMM15,%YMM12    [6]

0x5705bc VFMADD231PD	0x140(%RBX){1to4},%YMM0,%YMM12    [6]

0x5705c3 VMOVAPD	%YMM12,(%RDX,%R10,1)    [8]

0x5705c9 VMULPD	0x150(%RBX){1to4},%YMM7,%YMM7    [6]

0x5705d0 VFMADD231PD	0x148(%RBX){1to4},%YMM15,%YMM7    [6]

0x5705d7 VFMADD132PD	0x158(%RBX){1to4},%YMM7,%YMM0    [6]

0x5705de VMOVAPD	%YMM0,(%RSI,%R10,1)    [3]

0x5705e4 VMOVAPD	(%RDX,%R10,1),%YMM13    [8]

0x5705ea VMOVAPD	(%RCX,%R10,1),%YMM15    [7]

0x5705f0 VMULPD	%YMM13,%YMM13,%YMM14

0x5705f5 VFMADD132PD	%YMM15,%YMM14,%YMM15

0x5705fa VFMADD132PD	%YMM0,%YMM15,%YMM0

0x5705ff VSQRTPD	%YMM0,%YMM0

0x570603 VMOVAPD	%YMM0,(%R14,%R10,1)    [5]

0x570609 ADD	$0x20,%R10

0x57060d CMP	%R10,%R8

0x570610 JNE	5704e0

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 237 - 255

--------------------------------------------------------------------------------

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module
►97.30+	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.70+	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:242	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	main	refwrap.h:350	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	miniqmc.cpp:321	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	5.50
Front-end cycles	6.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	16.36
Nb FLOP add-sub	36.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	39.27
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	5.50
Front-end cycles	6.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	16.36
Nb FLOP add-sub	36.00
Nb FLOP mul	28.00
Nb FLOP fma	56.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	39.27
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

34 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 180 FP arithmetical operations:

92: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes (38 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	52
nb uops	51
loop length	310
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	12
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

INT+FP

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

10% of peak load performance is reached (27.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5704e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%R11,%R10,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%R12,%R10,1),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%RDI,%R10,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM9,%YMM4,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM10,%YMM7,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM8,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x168(%RBX){1to4},%YMM12,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x180(%RBX){1to4},%YMM12,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x198(%RBX){1to4},%YMM12,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x160(%RBX){1to4},%YMM14,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x178(%RBX){1to4},%YMM14,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x190(%RBX){1to4},%YMM14,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM6,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD231PD 0x170(%RBX){1to4},%YMM0,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x188(%RBX){1to4},%YMM0,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD 0x1a0(%RBX){1to4},%YMM13,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM6,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM15,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM7,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM14,%YMM15,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM13,%YMM7,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM4,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM14,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM12,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVAPD %YMM6,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM0,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM12,%YMM0,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMULPD 0x120(%RBX){1to4},%YMM7,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x118(%RBX){1to4},%YMM15,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSUBPD %YMM14,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD231PD 0x128(%RBX){1to4},%YMM0,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM4,(%RCX,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD 0x138(%RBX){1to4},%YMM7,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x130(%RBX){1to4},%YMM15,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x140(%RBX){1to4},%YMM0,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM12,(%RDX,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD 0x150(%RBX){1to4},%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x148(%RBX){1to4},%YMM15,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD 0x158(%RBX){1to4},%YMM7,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM0,(%RSI,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD (%RDX,%R10,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%RCX,%R10,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM13,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM15,%YMM14,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VMOVAPD %YMM0,(%R14,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5704e0 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x110>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 56 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

34 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 180 FP arithmetical operations:

92: addition or subtraction (56 inside FMA instructions)
84: multiply (56 inside FMA instructions)
4: square root

The binary loop is loading 304 bytes (38 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	52
nb uops	51
loop length	310
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	12
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

INT+FP

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

10% of peak load performance is reached (27.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5704e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%R11,%R10,1),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%R12,%R10,1),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%RDI,%R10,1),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM9,%YMM4,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM10,%YMM7,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM8,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x168(%RBX){1to4},%YMM12,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x180(%RBX){1to4},%YMM12,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x198(%RBX){1to4},%YMM12,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x160(%RBX){1to4},%YMM14,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x178(%RBX){1to4},%YMM14,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x190(%RBX){1to4},%YMM14,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM6,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD231PD 0x170(%RBX){1to4},%YMM0,%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x188(%RBX){1to4},%YMM0,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD 0x1a0(%RBX){1to4},%YMM13,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM6,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM15,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM7,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM14,%YMM15,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM13,%YMM7,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM4,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM14,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM12,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVAPD %YMM6,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM5,%YMM0,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM12,%YMM0,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VRNDSCALEPD $0x3,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VMULPD 0x120(%RBX){1to4},%YMM7,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x118(%RBX){1to4},%YMM15,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSUBPD %YMM14,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD231PD 0x128(%RBX){1to4},%YMM0,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM4,(%RCX,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD 0x138(%RBX){1to4},%YMM7,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x130(%RBX){1to4},%YMM15,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD 0x140(%RBX){1to4},%YMM0,%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM12,(%RDX,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD 0x150(%RBX){1to4},%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD 0x148(%RBX){1to4},%YMM15,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD 0x158(%RBX){1to4},%YMM7,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM0,(%RSI,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD (%RDX,%R10,1),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD (%RCX,%R10,1),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM13,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM15,%YMM14,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM0,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VSQRTPD %YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (50.0%)
VMOVAPD %YMM0,(%R14,%R10,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5704e0 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x110>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code