OV - exec - Loop 121

	Loop Id: 121	Module: exec	Source: OperatorTags.h:43-63 [...]	Coverage: 0.05%

0x40ea40 INC	%R15

0x40ea43 CMP	%RDX,%R15

0x40ea46 JAE	40ed1a

0x40ea4c MOV	-0xb0(%RBP),%RDI

0x40ea53 LEA	(,%R15,8),%R8

0x40ea5b MOV	0x18(%RDI),%RSI

0x40ea5f ADD	%R8,%RSI

0x40ea62 VMOVSD	(%RSI),%XMM0

0x40ea66 VCOMISD	0x1440(%R14),%XMM0

0x40ea6f JAE	40ea40

0x40ea71 MOV	0x2830(%R14),%RDX

0x40ea78 MOV	$-0x5555555555555555,%RAX

0x40ea82 SUB	0x2828(%R14),%RDX

0x40ea89 SAR	$0x3,%RDX

0x40ea8d IMUL	%RDX,%RAX

0x40ea91 TEST	%EAX,%EAX

0x40ea93 JLE	40eca8

0x40ea99 MOV	-0x150(%RBP),%R11

0x40eaa0 LEA	-0x1(%RAX),%EAX

0x40eaa3 MOV	-0x170(%RBP),%RDI

0x40eaaa ADD	0x40(%R13),%RDI

0x40eaae MOVSXD	0x8(%R11),%R10

0x40eab2 MOV	0x18(%R11),%RCX

0x40eab6 LEA	(%RAX,%RAX,2),%R11

0x40eaba LEA	(%R12,%R11,8),%RAX

0x40eabe LEA	(%R11,%R11,2),%R11

0x40eac2 VMOVQ	%RAX,%XMM4

0x40eac7 LEA	(%R10,%R15,1),%RDX

0x40eacb ADD	%RCX,%R8

0x40eace LEA	(%RCX,%RDX,8),%R9

0x40ead2 ADD	%R10,%RDX

0x40ead5 AND	$0x3,%R11D

0x40ead9 LEA	(%RCX,%RDX,8),%R10

0x40eadd MOV	-0x70(%RBP),%RDX

0x40eae1 MOV	%R12,%RCX

0x40eae4 JE	40ee59

0x40eaea VMOVSD	(%R8),%XMM6

0x40eaef VMOVHPD	(%R9),%XMM6,%XMM7

0x40eaf4 VADDPD	(%RDI),%XMM7,%XMM5

0x40eaf8 VMOVSD	(%R10),%XMM3

0x40eafd VMOVDDUP	%XMM0,%XMM1

0x40eb01 VADDSD	0x10(%RDI),%XMM3,%XMM8

0x40eb06 VFMADD231PD	(%R12),%XMM1,%XMM5

0x40eb0c VFMADD231SD	0x10(%R12),%XMM0,%XMM8

0x40eb13 ADD	$0x18,%RDX

0x40eb17 VMOVUPD	%XMM5,-0x18(%RDX)

0x40eb1c VMOVSD	%XMM8,-0x8(%RDX)

0x40eb21 LEA	0x18(%R12),%RCX

0x40eb26 VMOVSD	(%RSI),%XMM0

0x40eb2a CMP	$0x1,%R11

0x40eb2e JE	40ee59

0x40eb34 CMP	$0x2,%R11

0x40eb38 JE	40eb7a

0x40eb3a VMOVSD	(%R8),%XMM13

0x40eb3f VMOVHPD	(%R9),%XMM13,%XMM12

0x40eb44 VADDPD	(%RDI),%XMM12,%XMM11

0x40eb48 VMOVSD	(%R10),%XMM14

0x40eb4d VMOVDDUP	%XMM0,%XMM15

0x40eb51 VADDSD	0x10(%RDI),%XMM14,%XMM10

0x40eb56 VFMADD231PD	0x18(%R12),%XMM15,%XMM11

0x40eb5d VFMADD231SD	0x10(%RCX),%XMM0,%XMM10

0x40eb63 ADD	$0x18,%RDX

0x40eb67 LEA	0x30(%R12),%RCX

0x40eb6c VMOVUPD	%XMM11,-0x18(%RDX)

0x40eb71 VMOVSD	%XMM10,-0x8(%RDX)

0x40eb76 VMOVSD	(%RSI),%XMM0

0x40eb7a VMOVSD	(%R8),%XMM1

0x40eb7f VMOVHPD	(%R9),%XMM1,%XMM6

0x40eb84 VADDPD	(%RDI),%XMM6,%XMM7

0x40eb88 VMOVSD	(%R10),%XMM9

0x40eb8d VMOVDDUP	%XMM0,%XMM3

0x40eb91 VADDSD	0x10(%RDI),%XMM9,%XMM5

0x40eb96 VFMADD231PD	(%RCX),%XMM3,%XMM7

0x40eb9b VFMADD231SD	0x10(%RCX),%XMM0,%XMM5

0x40eba1 ADD	$0x18,%RDX

0x40eba5 VMOVUPD	%XMM7,-0x18(%RDX)

0x40ebaa VMOVSD	%XMM5,-0x8(%RDX)

0x40ebaf ADD	$0x18,%RCX

0x40ebb3 VMOVQ	%XMM4,%RAX

0x40ebb8 VMOVSD	(%RSI),%XMM0

0x40ebbc JMP	40ec6f

  (122) 0x40ebc1 VMOVSD	(%R8),%XMM10

  (122) 0x40ebc6 VMOVHPD	(%R9),%XMM10,%XMM9

  (122) 0x40ebcb VADDPD	(%RDI),%XMM9,%XMM3

  (122) 0x40ebcf VMOVSD	(%R10),%XMM11

  (122) 0x40ebd4 VMOVDDUP	(%RSI),%XMM1

  (122) 0x40ebd8 VADDSD	0x10(%RDI),%XMM11,%XMM7

  (122) 0x40ebdd VFMADD231PD	0x18(%RCX),%XMM1,%XMM3

  (122) 0x40ebe3 VMOVSD	0x28(%RCX),%XMM6

  (122) 0x40ebe8 VFMADD231SD	(%RSI),%XMM6,%XMM7

  (122) 0x40ebed VMOVUPD	%XMM3,0x18(%RDX)

  (122) 0x40ebf2 VMOVSD	%XMM7,0x28(%RDX)

  (122) 0x40ebf7 VMOVSD	(%R8),%XMM0

  (122) 0x40ebfc VMOVHPD	(%R9),%XMM0,%XMM4

  (122) 0x40ec01 VADDPD	(%RDI),%XMM4,%XMM8

  (122) 0x40ec05 VMOVSD	0x40(%RCX),%XMM13

  (122) 0x40ec0a VMOVSD	(%R10),%XMM5

  (122) 0x40ec0f VMOVDDUP	(%RSI),%XMM14

  (122) 0x40ec13 VADDSD	0x10(%RDI),%XMM5,%XMM15

  (122) 0x40ec18 VFMADD231PD	0x30(%RCX),%XMM14,%XMM8

  (122) 0x40ec1e VFMADD231SD	(%RSI),%XMM13,%XMM15

  (122) 0x40ec23 VMOVUPD	%XMM8,0x30(%RDX)

  (122) 0x40ec28 VMOVSD	%XMM15,0x40(%RDX)

  (122) 0x40ec2d VMOVSD	(%R8),%XMM11

  (122) 0x40ec32 VMOVSD	0x58(%RCX),%XMM7

  (122) 0x40ec37 VMOVHPD	(%R9),%XMM11,%XMM10

  (122) 0x40ec3c VADDPD	(%RDI),%XMM10,%XMM9

  (122) 0x40ec40 VMOVSD	(%R10),%XMM12

  (122) 0x40ec45 VMOVDDUP	(%RSI),%XMM3

  (122) 0x40ec49 VADDSD	0x10(%RDI),%XMM12,%XMM1

  (122) 0x40ec4e VFMADD231PD	0x48(%RCX),%XMM3,%XMM9

  (122) 0x40ec54 VFMADD231SD	(%RSI),%XMM7,%XMM1

  (122) 0x40ec59 ADD	$0x60,%RDX

  (122) 0x40ec5d ADD	$0x60,%RCX

  (122) 0x40ec61 VMOVUPD	%XMM9,-0x18(%RDX)

  (122) 0x40ec66 VMOVSD	%XMM1,-0x8(%RDX)

  (122) 0x40ec6b VMOVSD	(%RSI),%XMM0

  (122) 0x40ec6f VMOVSD	(%R8),%XMM14

  (122) 0x40ec74 VMOVHPD	(%R9),%XMM14,%XMM15

  (122) 0x40ec79 VADDPD	(%RDI),%XMM15,%XMM13

  (122) 0x40ec7d VMOVSD	(%R10),%XMM4

  (122) 0x40ec82 VMOVDDUP	%XMM0,%XMM8

  (122) 0x40ec86 VADDSD	0x10(%RDI),%XMM4,%XMM12

  (122) 0x40ec8b VFMADD231PD	(%RCX),%XMM8,%XMM13

  (122) 0x40ec90 VFMADD132SD	0x10(%RCX),%XMM12,%XMM0

  (122) 0x40ec96 VMOVUPD	%XMM13,(%RDX)

  (122) 0x40ec9a VMOVSD	%XMM0,0x10(%RDX)

  (122) 0x40ec9f CMP	%RAX,%RCX

  (122) 0x40eca2 JNE	40ebc1

0x40eca8 VMOVQ	%XMM2,%R8

0x40ecad MOV	0x2840(%R14),%R9

0x40ecb4 MOV	-0x110(%RBP),%EDX

0x40ecba LEA	-0x70(%RBP),%RCX

0x40ecbe MOV	0x18(%R8),%RSI

0x40ecc2 MOV	$0x1,%R8D

0x40ecc8 MOVSXD	(%RSI,%R15,4),%RDI

0x40eccc MOV	%R13,%RSI

0x40eccf MOV	(%R9,%RDI,8),%RDI

0x40ecd3 MOV	%R15D,%R9D

0x40ecd6 MOV	%RDI,-0xd0(%RBP)

0x40ecdd CALL	4dcf90 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>

0x40ece2 MOV	-0xd0(%RBP),%RSI

0x40ece9 MOV	-0x88(%RBP),%RDI

0x40ecf0 LEA	-0x50(%RBP),%RDX

0x40ecf4 CALL	418480 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>

0x40ecf9 VMOVQ	0x2858(%R14),%XMM2

0x40ed02 INC	%R15

0x40ed05 VMOVQ	%XMM2,%R10

0x40ed0a MOV	0x260(%R10),%RDX

0x40ed11 CMP	%RDX,%R15

0x40ed14 JB	40ea4c

0x40ee59 VMOVQ	%XMM4,%RAX

0x40ee5e JMP	40ec6f

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 277 - 277

--------------------------------------------------------------------------------

277:   inline size_t getTotalNum() const { return TotalNum; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 429 - 429

--------------------------------------------------------------------------------

429:         for (int iel = 0; iel < nels; ++iel)

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 992 - 993

--------------------------------------------------------------------------------

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

Coverage (%)	Name	Source Location	Module
►97.01+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.48
CQA speedup if fully vectorized	8.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.72
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main._omp_fn.1
Source	ParticleSet.h:277-277,miniqmc.cpp:429-429,TinyVector.h:145-145,stl_vector.h:992-993,OhmmsVector.h:229-229,unique_ptr.h:193-193,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,OperatorTags.h:43-43,OperatorTags.h:63-63,VectorSoAContainer.h:231-231
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	9.75
CQA cycles if FP arith vectorized	9.13
CQA cycles if fully vectorized	1.66
Front-end cycles	13.50
P0 cycles	7.83
P1 cycles	7.83
P2 cycles	7.83
P3 cycles	7.83
P4 cycles	7.83
P5 cycles	7.83
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	4.75
P11 cycles	4.75
P12 cycles	4.75
P13 cycles	4.75
P14 cycles	5.50
P15 cycles	5.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	108.00
Nb loads	46.00
Nb stores	7.00
Nb stack references	8.00
FLOP/cycle	2.00
Nb FLOP add-sub	9.00
Nb FLOP mul	0.00
Nb FLOP fma	9.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.26
Bytes prefetched	0.00
Bytes loaded	396.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	19.57
Vectorization ratio load	22.22
Vectorization ratio store	42.86
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.81
Vector-efficiency ratio load	15.28
Vector-efficiency ratio store	17.86
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.02

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.48
CQA speedup if fully vectorized	8.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.72
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main._omp_fn.1
Source	ParticleSet.h:277-277,miniqmc.cpp:429-429,TinyVector.h:145-145,stl_vector.h:992-993,OhmmsVector.h:229-229,unique_ptr.h:193-193,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135,OperatorTags.h:43-43,OperatorTags.h:63-63,VectorSoAContainer.h:231-231
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	9.75
CQA cycles if FP arith vectorized	9.13
CQA cycles if fully vectorized	1.66
Front-end cycles	13.50
P0 cycles	7.83
P1 cycles	7.83
P2 cycles	7.83
P3 cycles	7.83
P4 cycles	7.83
P5 cycles	7.83
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	4.75
P11 cycles	4.75
P12 cycles	4.75
P13 cycles	4.75
P14 cycles	5.50
P15 cycles	5.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	108.00
Nb loads	46.00
Nb stores	7.00
Nb stack references	8.00
FLOP/cycle	2.00
Nb FLOP add-sub	9.00
Nb FLOP mul	0.00
Nb FLOP fma	9.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.26
Bytes prefetched	0.00
Bytes loaded	396.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	19.57
Vectorization ratio load	22.22
Vectorization ratio store	42.86
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	14.81
Vector-efficiency ratio load	15.28
Vector-efficiency ratio store	17.86
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.02

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.1
Source file and lines	OperatorTags.h:43-63
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:992-993
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/unique_ptr.h:193
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 9.75 cycles (1.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.50 to 1.66 cycles (8.15x speedup).

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

22% of SSE/AVX loads are used in vector version.
42% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 7.83 cycles (1.72x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 9 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

18: addition or subtraction (9 inside FMA instructions)
9: multiply (all inside FMA instructions)

The binary loop is loading 396 bytes (49 double precision FP elements). The binary loop is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	108
loop length	509
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	13.50	13.50	13.50	13.50	4.75	4.75	4.75	4.75	5.50	5.50
cycles	7.83	7.83	7.83	7.83	7.83	7.83	13.50	13.50	13.50	13.50	4.75	4.75	4.75	4.75	5.50	5.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	13.50
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	23%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	19%
load	22%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	14%
load	15%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

11% of peak load performance is reached (29.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.93 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 7.83 cycles (1.72x speedup).

ASM code

In the binary file, the address of the loop is: 40ea4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 40ed1a <main._omp_fn.1+0x30aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R15,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCOMISD 0x1440(%R14),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 40ea40 <main._omp_fn.1+0x2dd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x2830(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $-0x5555555555555555,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB 0x2828(%R14),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SAR $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RDX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40eca8 <main._omp_fn.1+0x3038>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x150(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x1(%RAX),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x170(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD 0x40(%R13),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD 0x8(%R11),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%R11),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RAX,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%R11,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %RAX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%R10,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDX,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 40ee59 <main._omp_fn.1+0x31e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD (%RDI),%XMM7,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSD (%R10),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDSD 0x10(%RDI),%XMM3,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231PD (%R12),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231SD 0x10(%R12),%XMM0,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM5,-0x18(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM8,-0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x18(%R12),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x1,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ee59 <main._omp_fn.1+0x31e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eb7a <main._omp_fn.1+0x2f0a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9),%XMM13,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD (%RDI),%XMM12,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSD (%R10),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDSD 0x10(%RDI),%XMM14,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231PD 0x18(%R12),%XMM15,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231SD 0x10(%RCX),%XMM0,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x30(%R12),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM11,-0x18(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM10,-0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD (%RDI),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSD (%R10),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDSD 0x10(%RDI),%XMM9,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231PD (%RCX),%XMM3,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231SD 0x10(%RCX),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM7,-0x18(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM5,-0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 40ec6f <main._omp_fn.1+0x2fff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVQ %XMM2,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x2840(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x110(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x70(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD (%RSI,%R15,4),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R9,%RDI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4dcf90 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0xd0(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x50(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 418480 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x2858(%R14),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x260(%R10),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 40ea4c <main._omp_fn.1+0x2ddc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 40ec6f <main._omp_fn.1+0x2fff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	main._omp_fn.1
Source file and lines	OperatorTags.h:43-63
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:277
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:992-993
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/unique_ptr.h:193
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 9.75 cycles (1.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

22% of SSE/AVX loads are used in vector version.
42% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 7.83 cycles (1.72x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 9 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

qmcplusplus::VirtualParticleSet::makeMoves(qmcplusplus::ParticleSet const&, int, std::vector
, std::allocator
> > const&, bool, int): 1 occurrences►
qmcplusplus::WaveFunction::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector
>&): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:129

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

18: addition or subtraction (9 inside FMA instructions)
9: multiply (all inside FMA instructions)

The binary loop is loading 396 bytes (49 double precision FP elements). The binary loop is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	108
loop length	509
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	13.50	13.50	13.50	13.50	4.75	4.75	4.75	4.75	5.50	5.50
cycles	7.83	7.83	7.83	7.83	7.83	7.83	13.50	13.50	13.50	13.50	4.75	4.75	4.75	4.75	5.50	5.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	13.50
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	23%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	19%
load	22%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	15%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	14%
load	15%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

11% of peak load performance is reached (29.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.93 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40ea4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 40ed1a <main._omp_fn.1+0x30aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R15,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCOMISD 0x1440(%R14),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 40ea40 <main._omp_fn.1+0x2dd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x2830(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $-0x5555555555555555,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB 0x2828(%R14),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SAR $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
IMUL %RDX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40eca8 <main._omp_fn.1+0x3038>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x150(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x1(%RAX),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x170(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD 0x40(%R13),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD 0x8(%R11),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%R11),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RAX,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%R11,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %RAX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%R10,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDX,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 40ee59 <main._omp_fn.1+0x31e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD (%RDI),%XMM7,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSD (%R10),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDSD 0x10(%RDI),%XMM3,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231PD (%R12),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231SD 0x10(%R12),%XMM0,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM5,-0x18(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM8,-0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x18(%R12),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x1,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40ee59 <main._omp_fn.1+0x31e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eb7a <main._omp_fn.1+0x2f0a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9),%XMM13,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD (%RDI),%XMM12,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSD (%R10),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDSD 0x10(%RDI),%XMM14,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231PD 0x18(%R12),%XMM15,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231SD 0x10(%RCX),%XMM0,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x30(%R12),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM11,-0x18(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM10,-0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD (%RDI),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSD (%R10),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDSD 0x10(%RDI),%XMM9,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231PD (%RCX),%XMM3,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231SD 0x10(%RCX),%XMM0,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM7,-0x18(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM5,-0x8(%RDX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x18,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 40ec6f <main._omp_fn.1+0x2fff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVQ %XMM2,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x2840(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x110(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x70(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD (%RSI,%R15,4),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R9,%RDI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4dcf90 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0xd0(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA -0x50(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 418480 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x2858(%R14),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM2,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x260(%R10),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 40ea4c <main._omp_fn.1+0x2ddc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 40ec6f <main._omp_fn.1+0x2fff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

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Execution units bottlenecks

Workaround

FMA

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code