OV - exec - Loop 1110

	Loop Id: 1110	Module: exec	Source: inner_product.hpp:155-155 [...]	Coverage: 0.38%

0x49d592 VMOVUPD	(%RAX),%YMM3    [2]

0x49d596 VMOVUPD	0x20(%RAX),%YMM21    [2]

0x49d59d VMOVUPD	0x40(%RAX),%YMM20    [2]

0x49d5a4 VMOVUPD	(%RDX),%YMM19    [4]

0x49d5aa VMOVUPD	0x80(%RAX),%YMM22    [2]

0x49d5b1 VMOVUPD	0xa0(%RAX),%YMM25    [2]

0x49d5b8 VMOVUPD	0x20(%RDX),%YMM24    [4]

0x49d5bf VMOVUPD	0xe0(%RAX),%YMM28    [2]

0x49d5c6 VMOVUPD	0x100(%RAX),%YMM29    [2]

0x49d5cd VMOVUPD	0x140(%RAX),%YMM16    [2]

0x49d5d4 VMOVUPD	0x60(%RDX),%YMM17    [4]

0x49d5db SUB	$-0x80,%RDX

0x49d5df ADD	$0x180,%RAX

0x49d5e5 VMOVAPD	%YMM3,%YMM18

0x49d5eb VMOVAPD	%YMM3,%YMM23

0x49d5f1 VPERMT2PD	%YMM21,%YMM5,%YMM3

0x49d5f7 VPERMT2PD	%YMM20,%YMM4,%YMM3

0x49d5fd VPERMT2PD	%YMM21,%YMM9,%YMM18

0x49d603 VPERMT2PD	%YMM21,%YMM7,%YMM23

0x49d609 VFMADD231PD	%YMM19,%YMM3,%YMM0

0x49d60f VMOVUPD	-0x120(%RAX),%YMM3    [1]

0x49d617 VPERMT2PD	%YMM20,%YMM8,%YMM18

0x49d61d VPERMT2PD	%YMM20,%YMM6,%YMM23

0x49d623 VFMADD132PD	%YMM19,%YMM1,%YMM18

0x49d629 VFMADD231PD	%YMM19,%YMM23,%YMM2

0x49d62f VMOVUPD	-0x20(%RAX),%YMM19    [1]

0x49d636 VMOVAPD	%YMM3,%YMM26

0x49d63c VMOVAPD	%YMM3,%YMM1

0x49d640 VPERMT2PD	%YMM22,%YMM5,%YMM3

0x49d646 VPERMT2PD	%YMM25,%YMM4,%YMM3

0x49d64c VPERMT2PD	%YMM22,%YMM7,%YMM1

0x49d652 VPERMT2PD	%YMM22,%YMM9,%YMM26

0x49d658 VFMADD132PD	%YMM24,%YMM0,%YMM3

0x49d65e VMOVUPD	-0xc0(%RAX),%YMM0    [1]

0x49d666 VPERMT2PD	%YMM25,%YMM6,%YMM1

0x49d66c VPERMT2PD	%YMM25,%YMM8,%YMM26

0x49d672 VFMADD132PD	%YMM24,%YMM2,%YMM1

0x49d678 VMOVUPD	-0x40(%RDX),%YMM2    [3]

0x49d67d VFMADD132PD	%YMM24,%YMM18,%YMM26

0x49d683 VMOVAPD	%YMM3,%YMM27

0x49d689 VMOVAPD	%YMM0,%YMM30

0x49d68f VMOVAPD	%YMM0,%YMM31

0x49d695 VPERMT2PD	%YMM28,%YMM5,%YMM0

0x49d69b VPERMT2PD	%YMM29,%YMM4,%YMM0

0x49d6a1 VPERMT2PD	%YMM28,%YMM9,%YMM30

0x49d6a7 VPERMT2PD	%YMM28,%YMM7,%YMM31

0x49d6ad VFMADD231PD	%YMM2,%YMM0,%YMM27

0x49d6b3 VMOVUPD	-0x60(%RAX),%YMM0    [1]

0x49d6b8 VPERMT2PD	%YMM29,%YMM8,%YMM30

0x49d6be VPERMT2PD	%YMM29,%YMM6,%YMM31

0x49d6c4 VFMADD132PD	%YMM2,%YMM1,%YMM31

0x49d6ca VFMADD132PD	%YMM2,%YMM26,%YMM30

0x49d6d0 VMOVAPD	%YMM0,%YMM1

0x49d6d4 VMOVAPD	%YMM0,%YMM2

0x49d6d8 VPERMT2PD	%YMM16,%YMM5,%YMM0

0x49d6de VPERMT2PD	%YMM16,%YMM9,%YMM1

0x49d6e4 VPERMT2PD	%YMM16,%YMM7,%YMM2

0x49d6ea VPERMT2PD	%YMM19,%YMM4,%YMM0

0x49d6f0 VPERMT2PD	%YMM19,%YMM8,%YMM1

0x49d6f6 VFMADD132PD	%YMM17,%YMM27,%YMM0

0x49d6fc VPERMT2PD	%YMM19,%YMM6,%YMM2

0x49d702 VFMADD132PD	%YMM17,%YMM30,%YMM1

0x49d708 VFMADD132PD	%YMM17,%YMM31,%YMM2

0x49d70e CMP	%RDX,%R13

0x49d711 JNE	49d592

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Coverage (%)	Name	Source Location	Module
►48.53+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:250	exec
○	main._omp_fn.1	miniqmc.cpp:469	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►48.15+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main._omp_fn.1	miniqmc.cpp:469	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.24
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	12.92
CQA cycles if fully vectorized	8.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	64.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.24
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	12.92
CQA cycles if fully vectorized	8.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	64.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

48: addition or subtraction (all inside FMA instructions)
48: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	64
loop length	389
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	26
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	8.00
Dispatch	12.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49d592

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
VMOVUPD (%RAX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RAX),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RAX),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RDX),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x80(%RAX),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0xa0(%RAX),%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0xe0(%RAX),%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x100(%RAX),%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x140(%RAX),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%RDX),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
SUB $-0x80,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x180,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM3,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM21,%YMM5,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM20,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM21,%YMM9,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM21,%YMM7,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x120(%RAX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM20,%YMM8,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM20,%YMM6,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM19,%YMM1,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM23,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x20(%RAX),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM22,%YMM5,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM25,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM22,%YMM7,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM22,%YMM9,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM24,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0xc0(%RAX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM25,%YMM6,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM25,%YMM8,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM24,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x40(%RDX),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM24,%YMM18,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM28,%YMM5,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM29,%YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM28,%YMM9,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM28,%YMM7,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD231PD %YMM2,%YMM0,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x60(%RAX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM29,%YMM8,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM29,%YMM6,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM1,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM26,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM16,%YMM5,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM16,%YMM9,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM16,%YMM7,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM19,%YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM19,%YMM8,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM17,%YMM27,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VPERMT2PD %YMM19,%YMM6,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM17,%YMM30,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM17,%YMM31,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
JNE 49d592 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x492>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&, bool)
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

48: addition or subtraction (all inside FMA instructions)
48: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	64
loop length	389
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	26
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	8.00
Dispatch	12.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49d592

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
VMOVUPD (%RAX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RAX),%YMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RAX),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%RDX),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x80(%RAX),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0xa0(%RAX),%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0xe0(%RAX),%YMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x100(%RAX),%YMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x140(%RAX),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%RDX),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
SUB $-0x80,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x180,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM3,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM21,%YMM5,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM20,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM21,%YMM9,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM21,%YMM7,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x120(%RAX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM20,%YMM8,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM20,%YMM6,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM19,%YMM1,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM23,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x20(%RAX),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM22,%YMM5,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM25,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM22,%YMM7,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM22,%YMM9,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM24,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0xc0(%RAX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM25,%YMM6,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM25,%YMM8,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM24,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x40(%RDX),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM24,%YMM18,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM28,%YMM5,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM29,%YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM28,%YMM9,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM28,%YMM7,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD231PD %YMM2,%YMM0,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x60(%RAX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM29,%YMM8,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM29,%YMM6,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM1,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM26,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM16,%YMM5,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM16,%YMM9,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM16,%YMM7,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM19,%YMM4,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM19,%YMM8,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM17,%YMM27,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VPERMT2PD %YMM19,%YMM6,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM17,%YMM30,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM17,%YMM31,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
JNE 49d592 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x492>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code