OV - exec - Loop 1102

	Loop Id: 1102	Module: exec	Source: inner_product.hpp:155-155 [...]	Coverage: 0.02%

0x49aec2 VMOVUPD	(%RDX),%YMM3    [4]

0x49aec6 VMOVUPD	0x20(%RDX),%YMM15    [4]

0x49aecb VMOVUPD	0x40(%RDX),%YMM14    [4]

0x49aed0 VMOVUPD	(%R8),%YMM4    [2]

0x49aed5 SUB	$-0x80,%R8

0x49aed9 ADD	$0x180,%RDX

0x49aee0 VMOVAPD	%YMM3,%YMM5

0x49aee4 VMOVAPD	%YMM3,%YMM12

0x49aee8 VPERMT2PD	%YMM15,%YMM7,%YMM3

0x49aeee VPERMT2PD	%YMM15,%YMM11,%YMM5

0x49aef4 VPERMT2PD	%YMM15,%YMM9,%YMM12

0x49aefa VPERMT2PD	%YMM14,%YMM6,%YMM3

0x49af00 VMOVUPD	-0xe0(%RDX),%YMM15    [3]

0x49af08 VFMADD231PD	%YMM4,%YMM3,%YMM0

0x49af0d VPERMT2PD	%YMM14,%YMM10,%YMM5

0x49af13 VPERMT2PD	%YMM14,%YMM8,%YMM12

0x49af19 VMOVUPD	-0x100(%RDX),%YMM3    [3]

0x49af21 VFMADD231PD	%YMM4,%YMM5,%YMM1

0x49af26 VMOVUPD	-0x60(%R8),%YMM5    [1]

0x49af2c VMOVUPD	-0x80(%RDX),%YMM14    [3]

0x49af31 VFMADD231PD	%YMM12,%YMM4,%YMM2

0x49af36 VMOVUPD	-0x120(%RDX),%YMM4    [3]

0x49af3e VMOVAPD	%YMM4,%YMM12

0x49af42 VMOVAPD	%YMM4,%YMM13

0x49af46 VPERMT2PD	%YMM3,%YMM7,%YMM4

0x49af4c VPERMT2PD	%YMM3,%YMM11,%YMM12

0x49af52 VPERMT2PD	%YMM3,%YMM9,%YMM13

0x49af58 VPERMT2PD	%YMM15,%YMM6,%YMM4

0x49af5e VMOVUPD	-0xc0(%RDX),%YMM3    [3]

0x49af66 VFMADD132PD	%YMM5,%YMM0,%YMM4

0x49af6b VMOVUPD	-0xa0(%RDX),%YMM0    [3]

0x49af73 VPERMT2PD	%YMM15,%YMM10,%YMM12

0x49af79 VPERMT2PD	%YMM15,%YMM8,%YMM13

0x49af7f VFMADD132PD	%YMM5,%YMM1,%YMM12

0x49af84 VMOVUPD	-0x40(%R8),%YMM1    [1]

0x49af8a VFMADD231PD	%YMM13,%YMM5,%YMM2

0x49af8f VMOVUPD	-0x20(%RDX),%YMM13    [3]

0x49af94 VMOVAPD	%YMM3,%YMM5

0x49af98 VMOVAPD	%YMM3,%YMM15

0x49af9c VPERMT2PD	%YMM0,%YMM11,%YMM5

0x49afa2 VPERMT2PD	%YMM0,%YMM9,%YMM15

0x49afa8 VPERMT2PD	%YMM0,%YMM7,%YMM3

0x49afae VMOVUPD	-0x60(%RDX),%YMM0    [3]

0x49afb3 VPERMT2PD	%YMM14,%YMM10,%YMM5

0x49afb9 VPERMT2PD	%YMM14,%YMM8,%YMM15

0x49afbf VPERMT2PD	%YMM14,%YMM6,%YMM3

0x49afc5 VMOVUPD	-0x40(%RDX),%YMM14    [3]

0x49afca VFMADD132PD	%YMM1,%YMM4,%YMM3

0x49afcf VFMADD132PD	%YMM1,%YMM12,%YMM5

0x49afd4 VFMADD132PD	%YMM15,%YMM2,%YMM1

0x49afd9 VMOVUPD	-0x20(%R8),%YMM2    [1]

0x49afdf VMOVAPD	%YMM0,%YMM12

0x49afe3 VMOVAPD	%YMM1,%YMM4

0x49afe7 VMOVAPD	%YMM0,%YMM1

0x49afeb VPERMT2PD	%YMM14,%YMM9,%YMM12

0x49aff1 VPERMT2PD	%YMM14,%YMM7,%YMM0

0x49aff7 VPERMT2PD	%YMM14,%YMM11,%YMM1

0x49affd VPERMT2PD	%YMM13,%YMM8,%YMM12

0x49b003 VPERMT2PD	%YMM13,%YMM6,%YMM0

0x49b009 VPERMT2PD	%YMM13,%YMM10,%YMM1

0x49b00f VFMADD132PD	%YMM2,%YMM3,%YMM0

0x49b014 VFMADD132PD	%YMM2,%YMM5,%YMM1

0x49b019 VFMADD132PD	%YMM12,%YMM4,%YMM2

0x49b01e CMP	%RSI,%R8

0x49b021 JNE	49aec2

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Coverage (%)	Name	Source Location	Module
►51.12+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►45.89+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.24
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	12.92
CQA cycles if fully vectorized	8.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	64.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.24
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	12.92
CQA cycles if fully vectorized	8.00
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	64.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	48.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

48: addition or subtraction (all inside FMA instructions)
48: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	64
loop length	357
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	8.00
Dispatch	12.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49aec2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
VMOVUPD (%RDX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R8),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
SUB $-0x80,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x180,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM3,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM15,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM11,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM9,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM6,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0xe0(%RDX),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM4,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0x100(%RDX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM4,%YMM5,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x60(%R8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x80(%RDX),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM12,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x120(%RDX),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM4,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM4,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM3,%YMM7,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM3,%YMM11,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM3,%YMM9,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0xc0(%RDX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM5,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0xa0(%RDX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM10,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM8,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM5,%YMM1,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x40(%R8),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM5,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x20(%RDX),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM0,%YMM11,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM0,%YMM9,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM0,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0x60(%RDX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM8,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM6,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0x40(%RDX),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM12,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM15,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x20(%R8),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM0,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM1,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM14,%YMM9,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM7,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM11,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM13,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM13,%YMM6,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM13,%YMM10,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM5,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM12,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
JNE 49aec2 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x412>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 48 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

48: addition or subtraction (all inside FMA instructions)
48: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	64
loop length	357
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	8.00
Dispatch	12.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

12% of peak load performance is reached (32.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 49aec2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
VMOVUPD (%RDX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R8),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
SUB $-0x80,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x180,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %YMM3,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM15,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM11,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM9,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM6,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0xe0(%RDX),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM4,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0x100(%RDX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM4,%YMM5,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x60(%R8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x80(%RDX),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM12,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x120(%RDX),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM4,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM4,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM3,%YMM7,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM3,%YMM11,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM3,%YMM9,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0xc0(%RDX),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM5,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0xa0(%RDX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM10,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM15,%YMM8,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM5,%YMM1,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x40(%R8),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM5,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x20(%RDX),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM0,%YMM11,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM0,%YMM9,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM0,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0x60(%RDX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM10,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM8,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM6,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVUPD -0x40(%RDX),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM12,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM15,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVUPD -0x20(%R8),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM0,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM1,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPERMT2PD %YMM14,%YMM9,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM7,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM14,%YMM11,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM13,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM13,%YMM6,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPERMT2PD %YMM13,%YMM10,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM2,%YMM5,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM12,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
JNE 49aec2 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x412>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code