OV - exec - Loop 1000

	Loop Id: 1000	Module: exec	Source: MultiBsplineRef.hpp:242-262	Coverage: 10.53%

0x4875f0 VMOVSD	(%R9,%RAX,8),%XMM2    [2]

0x4875f6 VMOVSD	(%R13,%RAX,8),%XMM26    [7]

0x4875fe VMOVSD	(%RDI,%RAX,8),%XMM3    [9]

0x487603 VMOVSD	(%R10,%RAX,8),%XMM25    [3]

0x48760a VMULSD	%XMM11,%XMM26,%XMM0

0x487610 VMULSD	%XMM13,%XMM25,%XMM1

0x487616 VFMADD231SD	%XMM16,%XMM2,%XMM0

0x48761c VFMADD231SD	%XMM12,%XMM3,%XMM1

0x487621 MOV	0xf8(%RSP),%RCX    [11]

0x487629 VMULSD	%XMM19,%XMM25,%XMM27

0x48762f VMULSD	%XMM10,%XMM25,%XMM25

0x487635 VFMADD231SD	%XMM14,%XMM3,%XMM27

0x48763b VFMADD132SD	%XMM17,%XMM25,%XMM3

0x487641 VADDSD	%XMM1,%XMM0,%XMM0

0x487645 VMULSD	%XMM21,%XMM26,%XMM1

0x48764b VMULSD	%XMM20,%XMM26,%XMM26

0x487651 VFMADD231SD	%XMM18,%XMM2,%XMM1

0x487657 VFMADD132SD	%XMM15,%XMM26,%XMM2

0x48765d VADDSD	%XMM27,%XMM1,%XMM1

0x487663 VADDSD	%XMM3,%XMM2,%XMM2

0x487667 VMOVAPD	%XMM9,%XMM3

0x48766b VFMADD213SD	(%R11,%RAX,8),%XMM0,%XMM3    [4]

0x487671 VMOVSD	%XMM3,(%R11,%RAX,8)    [4]

0x487677 VMOVAPD	%XMM30,%XMM3

0x48767d VFMADD213SD	(%R14,%RAX,8),%XMM0,%XMM3    [8]

0x487683 VMOVSD	%XMM3,(%R14,%RAX,8)    [8]

0x487689 VMOVAPD	%XMM29,%XMM3

0x48768f VFMADD213SD	(%R15,%RAX,8),%XMM1,%XMM3    [10]

0x487695 VMOVSD	%XMM3,(%R15,%RAX,8)    [10]

0x48769b VMOVAPD	%XMM31,%XMM3

0x4876a1 VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM3    [15]

0x4876a7 VMOVSD	%XMM3,(%RDX,%RAX,8)    [15]

0x4876ac VMOVAPD	%XMM5,%XMM3

0x4876b0 VFMADD213SD	(%RSI,%RAX,8),%XMM1,%XMM3    [5]

0x4876b6 VMOVSD	%XMM3,(%RSI,%RAX,8)    [5]

0x4876bb VMOVAPD	%XMM5,%XMM3

0x4876bf VFMADD213SD	(%RBX,%RAX,8),%XMM4,%XMM2    [12]

0x4876c5 VMOVSD	%XMM2,(%RBX,%RAX,8)    [12]

0x4876ca VMOVAPD	%XMM29,%XMM2

0x4876d0 VFMADD213SD	(%R12,%RAX,8),%XMM0,%XMM2    [6]

0x4876d6 VMOVSD	%XMM2,(%R12,%RAX,8)    [6]

0x4876dc VFMADD213SD	(%R8,%RAX,8),%XMM0,%XMM3    [1]

0x4876e2 VMOVSD	%XMM3,(%R8,%RAX,8)    [1]

0x4876e8 VFMADD213SD	(%RCX,%RAX,8),%XMM4,%XMM1    [14]

0x4876ee VMOVSD	%XMM1,(%RCX,%RAX,8)    [14]

0x4876f3 MOV	0xf0(%RSP),%RCX    [11]

0x4876fb VFMADD213SD	(%RCX,%RAX,8),%XMM4,%XMM0    [13]

0x487701 VMOVSD	%XMM0,(%RCX,%RAX,8)    [13]

0x487706 MOV	%RAX,%RCX

0x487709 INC	%RAX

0x48770c CMP	%RCX,0xe8(%RSP)    [11]

0x487714 JNE	4875f0

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 242 - 262

--------------------------------------------------------------------------------

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►43.02+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►39.59+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.11+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:210	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.89+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:210	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:172	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.81
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	P10, P11,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	6.09
CQA cycles if fully vectorized	1.38
Front-end cycles	6.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	5.00
P15 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	3.00
FLOP/cycle	3.73
Nb FLOP add-sub	3.00
Nb FLOP mul	6.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.64
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	80.00
Stride 0	1.00
Stride 1	14.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	15.22
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	14.40
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.81
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	P10, P11,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	6.09
CQA cycles if fully vectorized	1.38
Front-end cycles	6.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	5.00
P15 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	3.00
FLOP/cycle	3.73
Nb FLOP add-sub	3.00
Nb FLOP mul	6.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.64
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	80.00
Stride 0	1.00
Stride 1	14.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	15.22
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	14.40
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242-262.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 1.37 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 6.75 cycles (1.63x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 41 FP arithmetical operations:

19: addition or subtraction (16 inside FMA instructions)
22: multiply (16 inside FMA instructions)

The binary loop is loading 136 bytes (17 double precision FP elements). The binary loop is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	52
nb uops	51
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	1.50	1.50	5.00	5.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	1.50	1.50	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Dispatch	11.00
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

4% of peak load performance is reached (12.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4875f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R9,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R13,%RAX,8),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM11,%XMM26,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM13,%XMM25,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM16,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD %XMM19,%XMM25,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM14,%XMM3,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM17,%XMM25,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM21,%XMM26,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM20,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM18,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM15,%XMM26,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVAPD %XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R11,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM30,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R14,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R14,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM29,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R15,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM31,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%RSI,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RSI,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%RBX,%RAX,8),%XMM4,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM29,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R12,%RAX,8),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%R12,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD213SD (%R8,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,0xe8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 4875f0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 41 FP arithmetical operations:

19: addition or subtraction (16 inside FMA instructions)
22: multiply (16 inside FMA instructions)

The binary loop is loading 136 bytes (17 double precision FP elements). The binary loop is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	52
nb uops	51
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	1.50	1.50	5.00	5.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	1.50	1.50	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Dispatch	11.00
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

4% of peak load performance is reached (12.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4875f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%R9,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R13,%RAX,8),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM11,%XMM26,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM13,%XMM25,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM16,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD %XMM19,%XMM25,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM14,%XMM3,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM17,%XMM25,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMULSD %XMM21,%XMM26,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM20,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VFMADD231SD %XMM18,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD132SD %XMM15,%XMM26,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM27,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVAPD %XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R11,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM30,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R14,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R14,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM29,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R15,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM31,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%RSI,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RSI,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%RBX,%RAX,8),%XMM4,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM29,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD (%R12,%RAX,8),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%R12,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD213SD (%R8,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%R8,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0xf0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,0xe8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 4875f0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code