OV - exec - Function miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: OneBodyJastrowRef.h:132-155 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h: 132 - 155

--------------------------------------------------------------------------------

132:   inline void evaluateRatios(VirtualParticleSet& VP, std::vector<ValueType>& ratios)

133:   {

134:     for (int k = 0; k < ratios.size(); ++k)

135:       ratios[k] = std::exp(Vat[VP.refPtcl] - computeU(VP.getDistTableAB(myTableID).getDistRow(k).data()));

136:   }

137:

138:   inline valT computeU(const valT* dist)

139:   {

140:     valT curVat(0);

141:     if (NumGroups > 0)

142:     {

143:       for (int jg = 0; jg < NumGroups; ++jg)

144:       {

145:         if (F[jg] != nullptr)

146:           curVat += F[jg]->evaluateV(-1, Ions.first(jg), Ions.last(jg), dist, DistCompressed.data());

147:       }

148:     }

149:     else

150:     {

151:       for (int c = 0; c < Nions; ++c)

152:       {

153:         int gid = Ions.GroupID[c];

154:         if (F[gid] != nullptr)

155:           curVat += F[gid]->evaluate(dist[c]);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 993 - 1150

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

1148:       {

1149: 	__glibcxx_requires_subscript(__n);

1150: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 166 - 260

--------------------------------------------------------------------------------

166:     if (r >= cutoff_radius)

167:       return 0.0;

168:     r *= DeltaRInv;

169:     real_type ipart, t;

170:     t     = std::modf(r, &ipart);

171:     int i = (int)ipart;

172:     real_type tp[4];

173:     tp[0] = t * t * t;

[...]

179:       (SplineCoefs[i+0]*(A[ 0]*tp[0] + A[ 1]*tp[1] + A[ 2]*tp[2] + A[ 3]*tp[3])+

180:        SplineCoefs[i+1]*(A[ 4]*tp[0] + A[ 5]*tp[1] + A[ 6]*tp[2] + A[ 7]*tp[3])+

181:        SplineCoefs[i+2]*(A[ 8]*tp[0] + A[ 9]*tp[1] + A[10]*tp[2] + A[11]*tp[3])+

182:        SplineCoefs[i+3]*(A[12]*tp[0] + A[13]*tp[1] + A[14]*tp[2] + A[15]*tp[3]));

[...]

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

0x41fc20 LEA	0x8(%RSP),%R10

0x41fc25 AND	$-0x20,%RSP

0x41fc29 MOV	$0x1,%EAX

0x41fc2e PUSHQ	-0x8(%R10)

0x41fc32 PUSH	%RBP

0x41fc33 VPBROADCASTD	%EAX,%XMM5

0x41fc39 MOV	%RSP,%RBP

0x41fc3c PUSH	%R15

0x41fc3e PUSH	%R14

0x41fc40 PUSH	%R13

0x41fc42 PUSH	%R12

0x41fc44 PUSH	%R10

0x41fc46 PUSH	%RBX

0x41fc47 SUB	$0x1a0,%RSP

0x41fc4e MOV	0x8(%RDX),%RCX

0x41fc52 VMOVDQA	%XMM5,-0x1a0(%RBP)

0x41fc5a MOV	%RSI,-0x1b8(%RBP)

0x41fc61 CMP	%RCX,(%RDX)

0x41fc64 JE	420904

0x41fc6a MOV	%RDI,%RBX

0x41fc6d MOV	%RDX,%R15

0x41fc70 XOR	%R14D,%R14D

0x41fc73 NOPW	%CS:(%RAX,%RAX,1)

0x41fc7e XCHG	%AX,%AX

(252) 0x41fc80 MOV	-0x1b8(%RBP),%RDI

(252) 0x41fc87 MOV	0xf0(%RBX),%RSI

(252) 0x41fc8e MOVSXD	0x2a0(%RDI),%RDX

(252) 0x41fc95 VMOVSD	(%RSI,%RDX,8),%XMM1

(252) 0x41fc9a MOV	0xa8(%RBX),%ESI

(252) 0x41fca0 VMOVSD	%XMM1,-0x70(%RBP)

(252) 0x41fca5 CALL	4c7c00 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>

(252) 0x41fcaa MOVSXD	0x98(%RBX),%R10

(252) 0x41fcb1 LEA	(%R14,%R14,4),%R8

(252) 0x41fcb5 VMOVSD	-0x70(%RBP),%XMM7

(252) 0x41fcba MOV	0x48(%RAX),%R9

(252) 0x41fcbe TEST	%R10D,%R10D

(252) 0x41fcc1 LEA	(%R9,%R8,8),%R11

(252) 0x41fcc5 MOV	0x18(%R11),%R12

(252) 0x41fcc9 JLE	420920

(252) 0x41fccf MOV	0x1c8(%RBX),%R11

(252) 0x41fcd6 MOV	$0x1,%R13D

(252) 0x41fcdc MOV	$0x2,%EDX

(252) 0x41fce1 MOV	%R15,-0x1b0(%RBP)

(252) 0x41fce8 VPBROADCASTD	%R13D,%YMM6

(252) 0x41fcee VPBROADCASTD	%EDX,%YMM2

(252) 0x41fcf4 XOR	%ESI,%ESI

(252) 0x41fcf6 KXNORB	%K1,%K1,%K1

(252) 0x41fcfa SAL	$0x2,%R10

(252) 0x41fcfe MOVQ	$0,-0x48(%RBP)

(252) 0x41fd06 MOV	%R14,-0x1a8(%RBP)

(252) 0x41fd0d VMOVDQA	%YMM6,-0xf0(%RBP)

(252) 0x41fd15 VMOVDQA	%YMM2,-0x110(%RBP)

(252) 0x41fd1d MOV	%R12,%R13

(252) 0x41fd20 VMOVQ	%XMM7,%R15

(252) 0x41fd25 NOPW	%CS:(%RAX,%RAX,1)

  (254) 0x41fd30 MOV	(%R11,%RSI,2),%R12

  (254) 0x41fd34 TEST	%R12,%R12

  (254) 0x41fd37 JE	4208b3

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  (254) 0x41fd44 MOV	0x268(%RDI),%RCX

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  (254) 0x41fd5a MOV	0x4(%RAX,%RSI,1),%R14D

  (254) 0x41fd5f MOV	%R8,%R9

  (254) 0x41fd62 CMP	%R8D,%R14D

  (254) 0x41fd65 JLE	4208b3

  (254) 0x41fd6b LEA	(%R13,%R8,8),%RCX

  (254) 0x41fd70 MOV	%R8D,%EAX

  (254) 0x41fd73 MOV	%R14D,%R8D

  (254) 0x41fd76 XOR	%EDX,%EDX

  (254) 0x41fd78 SUB	%R9D,%R8D

  (254) 0x41fd7b VMOVSD	0x8(%R12),%XMM9

  (254) 0x41fd82 AND	$0x7,%R8D

  (254) 0x41fd86 JE	41feac

  (254) 0x41fd8c CMP	$0x1,%R8D

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  (254) 0x41fda4 JE	41fe41

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  (254) 0x41fdb0 CMP	$0x5,%R8D

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  (254) 0x41fdba JE	41fdde

  (254) 0x41fdbc VMOVSD	(%RCX),%XMM10

  (254) 0x41fdc0 VCOMISD	%XMM10,%XMM9

  (254) 0x41fdc5 JBE	41fdd6

  (254) 0x41fdc7 CMP	$-0x1,%R9D

  (254) 0x41fdcb JE	41fdd6

  (254) 0x41fdcd MOV	$0x1,%EDX

  (254) 0x41fdd2 VMOVSD	%XMM10,(%RDI)

  (254) 0x41fdd6 ADD	$0x8,%RCX

  (254) 0x41fdda LEA	0x1(%R9),%EAX

  (254) 0x41fdde VMOVSD	(%RCX),%XMM11

  (254) 0x41fde2 VCOMISD	%XMM11,%XMM9

  (254) 0x41fde7 JBE	41fdf9

  (254) 0x41fde9 CMP	$-0x1,%EAX

  (254) 0x41fdec JE	41fdf9

  (254) 0x41fdee MOVSXD	%EDX,%R9

  (254) 0x41fdf1 INC	%EDX

  (254) 0x41fdf3 VMOVSD	%XMM11,(%RDI,%R9,8)

  (254) 0x41fdf9 ADD	$0x8,%RCX

  (254) 0x41fdfd INC	%EAX

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  (254) 0x41fe03 VCOMISD	%XMM12,%XMM9

  (254) 0x41fe08 JBE	41fe1a

  (254) 0x41fe0a CMP	$-0x1,%EAX

  (254) 0x41fe0d JE	41fe1a

  (254) 0x41fe0f MOVSXD	%EDX,%R8

  (254) 0x41fe12 INC	%EDX

  (254) 0x41fe14 VMOVSD	%XMM12,(%RDI,%R8,8)

  (254) 0x41fe1a ADD	$0x8,%RCX

  (254) 0x41fe1e INC	%EAX

  (254) 0x41fe20 VMOVSD	(%RCX),%XMM13

  (254) 0x41fe24 VCOMISD	%XMM13,%XMM9

  (254) 0x41fe29 JBE	41fe3b

  (254) 0x41fe2b CMP	$-0x1,%EAX

  (254) 0x41fe2e JE	41fe3b

  (254) 0x41fe30 MOVSXD	%EDX,%R9

  (254) 0x41fe33 INC	%EDX

  (254) 0x41fe35 VMOVSD	%XMM13,(%RDI,%R9,8)

  (254) 0x41fe3b ADD	$0x8,%RCX

  (254) 0x41fe3f INC	%EAX

  (254) 0x41fe41 VMOVSD	(%RCX),%XMM14

  (254) 0x41fe45 VCOMISD	%XMM14,%XMM9

  (254) 0x41fe4a JBE	41fe5c

  (254) 0x41fe4c CMP	$-0x1,%EAX

  (254) 0x41fe4f JE	41fe5c

  (254) 0x41fe51 MOVSXD	%EDX,%R8

  (254) 0x41fe54 INC	%EDX

  (254) 0x41fe56 VMOVSD	%XMM14,(%RDI,%R8,8)

  (254) 0x41fe5c ADD	$0x8,%RCX

  (254) 0x41fe60 INC	%EAX

  (254) 0x41fe62 VMOVSD	(%RCX),%XMM15

  (254) 0x41fe66 VCOMISD	%XMM15,%XMM9

  (254) 0x41fe6b JBE	41fe7d

  (254) 0x41fe6d CMP	$-0x1,%EAX

  (254) 0x41fe70 JE	41fe7d

  (254) 0x41fe72 MOVSXD	%EDX,%R9

  (254) 0x41fe75 INC	%EDX

  (254) 0x41fe77 VMOVSD	%XMM15,(%RDI,%R9,8)

  (254) 0x41fe7d ADD	$0x8,%RCX

  (254) 0x41fe81 INC	%EAX

  (254) 0x41fe83 VMOVSD	(%RCX),%XMM5

  (254) 0x41fe87 VCOMISD	%XMM5,%XMM9

  (254) 0x41fe8b JBE	41fe9d

  (254) 0x41fe8d CMP	$-0x1,%EAX

  (254) 0x41fe90 JE	41fe9d

  (254) 0x41fe92 MOVSXD	%EDX,%R8

  (254) 0x41fe95 INC	%EDX

  (254) 0x41fe97 VMOVSD	%XMM5,(%RDI,%R8,8)

  (254) 0x41fe9d INC	%EAX

  (254) 0x41fe9f ADD	$0x8,%RCX

  (254) 0x41fea3 CMP	%EAX,%R14D

  (254) 0x41fea6 JE	41ffb7

    (255) 0x41feac VMOVSD	(%RCX),%XMM1

    (255) 0x41feb0 VCOMISD	%XMM1,%XMM9

    (255) 0x41feb4 JBE	41fec6

    (255) 0x41feb6 CMP	$-0x1,%EAX

    (255) 0x41feb9 JE	41fec6

    (255) 0x41febb MOVSXD	%EDX,%R9

    (255) 0x41febe INC	%EDX

    (255) 0x41fec0 VMOVSD	%XMM1,(%RDI,%R9,8)

    (255) 0x41fec6 INC	%EAX

    (255) 0x41fec8 VMOVSD	0x8(%RCX),%XMM4

    (255) 0x41fecd LEA	0x8(%RCX),%R8

    (255) 0x41fed1 VCOMISD	%XMM4,%XMM9

    (255) 0x41fed5 JBE	41fee6

    (255) 0x41fed7 CMP	$-0x1,%EAX

    (255) 0x41feda JE	41fee6

    (255) 0x41fedc MOVSXD	%EDX,%RCX

    (255) 0x41fedf INC	%EDX

    (255) 0x41fee1 VMOVSD	%XMM4,(%RDI,%RCX,8)

    (255) 0x41fee6 VMOVSD	0x8(%R8),%XMM3

    (255) 0x41feec LEA	0x1(%RAX),%R9D

    (255) 0x41fef0 VCOMISD	%XMM3,%XMM9

    (255) 0x41fef4 JBE	41ff06

    (255) 0x41fef6 CMP	$-0x1,%R9D

    (255) 0x41fefa JE	41ff06

    (255) 0x41fefc MOVSXD	%EDX,%RCX

    (255) 0x41feff INC	%EDX

    (255) 0x41ff01 VMOVSD	%XMM3,(%RDI,%RCX,8)

    (255) 0x41ff06 VMOVSD	0x10(%R8),%XMM0

    (255) 0x41ff0c LEA	0x2(%RAX),%R9D

    (255) 0x41ff10 VCOMISD	%XMM0,%XMM9

    (255) 0x41ff14 JBE	41ff26

    (255) 0x41ff16 CMP	$-0x1,%R9D

    (255) 0x41ff1a JE	41ff26

    (255) 0x41ff1c MOVSXD	%EDX,%RCX

    (255) 0x41ff1f INC	%EDX

    (255) 0x41ff21 VMOVSD	%XMM0,(%RDI,%RCX,8)

    (255) 0x41ff26 VMOVSD	0x18(%R8),%XMM8

    (255) 0x41ff2c LEA	0x3(%RAX),%R9D

    (255) 0x41ff30 VCOMISD	%XMM8,%XMM9

    (255) 0x41ff35 JBE	41ff47

    (255) 0x41ff37 CMP	$-0x1,%R9D

    (255) 0x41ff3b JE	41ff47

    (255) 0x41ff3d MOVSXD	%EDX,%RCX

    (255) 0x41ff40 INC	%EDX

    (255) 0x41ff42 VMOVSD	%XMM8,(%RDI,%RCX,8)

    (255) 0x41ff47 VMOVSD	0x20(%R8),%XMM7

    (255) 0x41ff4d LEA	0x4(%RAX),%R9D

    (255) 0x41ff51 VCOMISD	%XMM7,%XMM9

    (255) 0x41ff55 JBE	41ff67

    (255) 0x41ff57 CMP	$-0x1,%R9D

    (255) 0x41ff5b JE	41ff67

    (255) 0x41ff5d MOVSXD	%EDX,%RCX

    (255) 0x41ff60 INC	%EDX

    (255) 0x41ff62 VMOVSD	%XMM7,(%RDI,%RCX,8)

    (255) 0x41ff67 VMOVSD	0x28(%R8),%XMM6

    (255) 0x41ff6d LEA	0x5(%RAX),%R9D

    (255) 0x41ff71 VCOMISD	%XMM6,%XMM9

    (255) 0x41ff75 JBE	41ff87

    (255) 0x41ff77 CMP	$-0x1,%R9D

    (255) 0x41ff7b JE	41ff87

    (255) 0x41ff7d MOVSXD	%EDX,%RCX

    (255) 0x41ff80 INC	%EDX

    (255) 0x41ff82 VMOVSD	%XMM6,(%RDI,%RCX,8)

    (255) 0x41ff87 VMOVSD	0x30(%R8),%XMM2

    (255) 0x41ff8d LEA	0x6(%RAX),%R9D

    (255) 0x41ff91 VCOMISD	%XMM2,%XMM9

    (255) 0x41ff95 JBE	41ffa7

    (255) 0x41ff97 CMP	$-0x1,%R9D

    (255) 0x41ff9b JE	41ffa7

    (255) 0x41ff9d MOVSXD	%EDX,%RCX

    (255) 0x41ffa0 INC	%EDX

    (255) 0x41ffa2 VMOVSD	%XMM2,(%RDI,%RCX,8)

    (255) 0x41ffa7 ADD	$0x7,%EAX

    (255) 0x41ffaa LEA	0x38(%R8),%RCX

    (255) 0x41ffae CMP	%EAX,%R14D

    (255) 0x41ffb1 JNE	41feac

  (254) 0x41ffb7 TEST	%EDX,%EDX

  (254) 0x41ffb9 JE	4208b3

  (254) 0x41ffbf VMOVSD	0x30(%R12),%XMM6

  (254) 0x41ffc6 VMOVSD	0x38(%R12),%XMM2

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  (254) 0x41ffd4 VMOVSD	0x48(%R12),%XMM0

  (254) 0x41ffdb VMOVSD	0x50(%R12),%XMM1

  (254) 0x41ffe2 VMOVSD	0x58(%R12),%XMM14

  (254) 0x41ffe9 VMOVSD	0x60(%R12),%XMM13

  (254) 0x41fff0 VMOVSD	0x68(%R12),%XMM12

  (254) 0x41fff7 VMOVSD	0x70(%R12),%XMM15

  (254) 0x41fffe VMOVSD	0x78(%R12),%XMM9

  (254) 0x420005 VMOVSD	0x80(%R12),%XMM10

  (254) 0x42000f VMOVSD	0x88(%R12),%XMM11

  (254) 0x420019 MOV	0x218(%R12),%RAX

  (254) 0x420021 VMOVSD	0x238(%R12),%XMM3

  (254) 0x42002b VMOVSD	0x18(%R12),%XMM4

  (254) 0x420032 VMOVSD	0x20(%R12),%XMM5

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  (254) 0x420040 VMOVSD	0x90(%R12),%XMM31

  (254) 0x420048 LEA	-0x1(%RDX),%R12D

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  (254) 0x4200a9 CMP	$0x6,%R12D

  (254) 0x4200ad JBE	420d07

  (254) 0x4200b3 MOV	%EDX,%R8D

  (254) 0x4200b6 VBROADCASTSD	%XMM6,%YMM23

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  (254) 0x4200c2 VBROADCASTSD	%XMM0,%YMM6

  (254) 0x4200c7 SHR	$0x3,%R8D

  (254) 0x4200cb VMOVSD	%XMM3,-0x170(%RBP)

  (254) 0x4200d3 VMOVSD	%XMM4,-0x178(%RBP)

  (254) 0x4200db VMOVSD	%XMM5,-0x180(%RBP)

  (254) 0x4200e3 VBROADCASTSD	%XMM7,%YMM21

  (254) 0x4200e9 VBROADCASTSD	%XMM1,%YMM2

  (254) 0x4200ee VBROADCASTSD	%XMM11,%YMM7

  (254) 0x4200f3 VBROADCASTSD	%XMM31,%YMM0

  (254) 0x4200f9 SAL	$0x6,%R8

  (254) 0x4200fd VMOVSD	%XMM8,-0x188(%RBP)

  (254) 0x420105 VMOVSD	%XMM31,-0x190(%RBP)

  (254) 0x42010c VBROADCASTSD	%XMM14,%YMM28

  (254) 0x420112 VBROADCASTSD	%XMM13,%YMM29

  (254) 0x420118 VXORPD	%XMM14,%XMM14,%XMM14

  (254) 0x42011d VBROADCASTSD	%XMM3,%YMM27

  (254) 0x420123 VBROADCASTSD	%XMM4,%YMM26

  (254) 0x420129 VBROADCASTSD	%XMM5,%YMM25

  (254) 0x42012f VBROADCASTSD	%XMM8,%YMM24

  (254) 0x420135 VMOVAPD	%YMM6,-0x90(%RBP)

  (254) 0x42013d VMOVAPD	%YMM2,-0x70(%RBP)

  (254) 0x420142 VBROADCASTSD	%XMM12,%YMM20

  (254) 0x420148 VBROADCASTSD	%XMM15,%YMM19

  (254) 0x42014e VBROADCASTSD	%XMM9,%YMM18

  (254) 0x420154 VBROADCASTSD	%XMM10,%YMM17

  (254) 0x42015a VMOVAPD	%YMM7,-0xb0(%RBP)

  (254) 0x420162 VMOVAPD	%YMM0,-0xd0(%RBP)

  (254) 0x42016a MOV	%RDI,%R14

  (254) 0x42016d ADD	%RDI,%R8

  (254) 0x420170 VMOVAPD	%YMM14,%YMM13

  (254) 0x420175 NOPW	%CS:(%RAX,%RAX,1)

    (256) 0x420180 VMULPD	0x20(%R14),%YMM27,%YMM3

    (256) 0x420187 VMULPD	(%R14),%YMM27,%YMM8

    (256) 0x42018d KMOVB	%K1,%K2

    (256) 0x420191 KMOVB	%K1,%K4

    (256) 0x420195 VMOVAPD	%YMM24,%YMM6

    (256) 0x42019b ADD	$0x40,%R14

    (256) 0x42019f KMOVB	%K1,%K3

    (256) 0x4201a3 KMOVB	%K1,%K5

    (256) 0x4201a7 KMOVB	%K1,%K6

    (256) 0x4201ab KMOVB	%K1,%K7

    (256) 0x4201af VRNDSCALEPD	$0xb,%YMM3,%YMM15

    (256) 0x4201b6 VCVTTPD2DQ	%YMM3,%XMM5

    (256) 0x4201ba VCVTTPD2DQ	%YMM8,%XMM4

    (256) 0x4201bf VINSERTI32X4	$0x1,%XMM5,%YMM4,%YMM1

    (256) 0x4201c6 VGATHERDPD	(%RAX,%XMM4,8),%YMM16{%K2}

    (256) 0x4201cd VMOVAPD	%YMM24,%YMM4

    (256) 0x4201d3 VPERM2I128	$0x11,%YMM1,%YMM1,%YMM11

    (256) 0x4201d9 KMOVB	%K1,%K2

    (256) 0x4201dd VSUBPD	%YMM15,%YMM3,%YMM3

    (256) 0x4201e2 VGATHERDPD	(%RAX,%XMM11,8),%YMM15{%K3}

    (256) 0x4201e9 VMOVAPD	-0x90(%RBP),%YMM11

    (256) 0x4201f1 KMOVB	%K1,%K3

    (256) 0x4201f5 VRNDSCALEPD	$0xb,%YMM8,%YMM12

    (256) 0x4201fc VMULPD	%YMM3,%YMM3,%YMM2

    (256) 0x420200 VFMADD132PD	%YMM3,%YMM23,%YMM4

    (256) 0x420206 VMULPD	%YMM3,%YMM2,%YMM9

    (256) 0x42020a VMULPD	%YMM2,%YMM25,%YMM7

    (256) 0x420210 VSUBPD	%YMM12,%YMM8,%YMM0

    (256) 0x420215 VPADDD	-0xf0(%RBP),%YMM1,%YMM12

    (256) 0x42021d VMOVAPD	%YMM11,%YMM31

    (256) 0x420223 VFMADD213PD	-0x70(%RBP),%YMM3,%YMM11

    (256) 0x420229 VFMADD213PD	-0x70(%RBP),%YMM0,%YMM31

    (256) 0x420233 VFMADD231PD	%YMM9,%YMM26,%YMM7

    (256) 0x420239 VMULPD	%YMM0,%YMM0,%YMM5

    (256) 0x42023d VFMADD132PD	%YMM0,%YMM23,%YMM6

    (256) 0x420243 VMULPD	%YMM0,%YMM5,%YMM10

    (256) 0x420247 VMULPD	%YMM5,%YMM25,%YMM8

    (256) 0x42024d VGATHERDPD	(%RAX,%XMM12,8),%YMM30{%K4}

    (256) 0x420254 VADDPD	%YMM4,%YMM7,%YMM7

    (256) 0x420258 VPERM2I128	$0x11,%YMM12,%YMM12,%YMM4

    (256) 0x42025e VMULPD	%YMM21,%YMM2,%YMM12

    (256) 0x420264 VFMADD231PD	%YMM10,%YMM26,%YMM8

    (256) 0x42026a VFMADD231PD	%YMM22,%YMM9,%YMM12

    (256) 0x420270 VADDPD	%YMM6,%YMM8,%YMM8

    (256) 0x420274 VGATHERDPD	(%RAX,%XMM4,8),%YMM6{%K5}

    (256) 0x42027b VMULPD	%YMM21,%YMM5,%YMM4

    (256) 0x420281 VADDPD	%YMM12,%YMM11,%YMM12

    (256) 0x420286 VMOVAPD	%YMM3,%YMM11

    (256) 0x42028a VFMADD132PD	%YMM20,%YMM19,%YMM11

    (256) 0x420290 VFMADD231PD	%YMM22,%YMM10,%YMM4

    (256) 0x420296 VMULPD	%YMM12,%YMM6,%YMM6

    (256) 0x42029b VFMADD231PD	%YMM7,%YMM15,%YMM6

    (256) 0x4202a0 VPADDD	-0x110(%RBP),%YMM1,%YMM15

    (256) 0x4202a8 VADDPD	%YMM31,%YMM4,%YMM4

    (256) 0x4202ae VPADDD	0x19f9ea(%RIP),%YMM1,%YMM1

    (256) 0x4202b6 VMULPD	%YMM30,%YMM4,%YMM4

    (256) 0x4202bc VPERM2I128	$0x11,%YMM15,%YMM15,%YMM7

    (256) 0x4202c2 VFMADD231PD	%YMM8,%YMM16,%YMM4

    (256) 0x4202c8 VGATHERDPD	(%RAX,%XMM15,8),%YMM12{%K6}

    (256) 0x4202cf VMOVAPD	%YMM0,%YMM16

    (256) 0x4202d5 VMULPD	%YMM29,%YMM2,%YMM15

    (256) 0x4202db VMULPD	%YMM17,%YMM2,%YMM2

    (256) 0x4202e1 VGATHERDPD	(%RAX,%XMM7,8),%YMM8{%K7}

    (256) 0x4202e8 VMULPD	%YMM29,%YMM5,%YMM7

    (256) 0x4202ee VMULPD	%YMM17,%YMM5,%YMM5

    (256) 0x4202f4 VFMADD132PD	%YMM20,%YMM19,%YMM16

    (256) 0x4202fa VFMADD231PD	%YMM28,%YMM9,%YMM15

    (256) 0x420300 VFMADD231PD	%YMM18,%YMM9,%YMM2

    (256) 0x420306 VMOVAPD	-0xb0(%RBP),%YMM9

    (256) 0x42030e VFMADD231PD	%YMM28,%YMM10,%YMM7

    (256) 0x420314 VFMADD231PD	%YMM18,%YMM10,%YMM5

    (256) 0x42031a VMOVAPD	-0xd0(%RBP),%YMM10

    (256) 0x420322 VADDPD	%YMM15,%YMM11,%YMM11

    (256) 0x420327 VGATHERDPD	(%RAX,%XMM1,8),%YMM15{%K2}

    (256) 0x42032e VPERM2I128	$0x11,%YMM1,%YMM1,%YMM1

    (256) 0x420334 VADDPD	%YMM16,%YMM7,%YMM7

    (256) 0x42033a VGATHERDPD	(%RAX,%XMM1,8),%YMM31{%K3}

    (256) 0x420341 VFMADD132PD	%YMM9,%YMM10,%YMM0

    (256) 0x420346 VFMADD132PD	%YMM9,%YMM10,%YMM3

    (256) 0x42034b VADDPD	%YMM5,%YMM0,%YMM0

    (256) 0x42034f VADDPD	%YMM3,%YMM2,%YMM3

    (256) 0x420353 VMULPD	%YMM15,%YMM0,%YMM15

    (256) 0x420358 VFMADD231PD	%YMM7,%YMM12,%YMM15

    (256) 0x42035d VMULPD	%YMM3,%YMM31,%YMM12

    (256) 0x420363 VFMADD132PD	%YMM11,%YMM12,%YMM8

    (256) 0x420368 VADDPD	%YMM4,%YMM15,%YMM4

    (256) 0x42036c VADDPD	%YMM8,%YMM6,%YMM6

    (256) 0x420371 VADDPD	%YMM4,%YMM13,%YMM13

    (256) 0x420375 VADDPD	%YMM6,%YMM14,%YMM14

    (256) 0x420379 CMP	%R14,%R8

    (256) 0x42037c JNE	420180

  (254) 0x420382 VADDPD	%YMM14,%YMM13,%YMM7

  (254) 0x420387 MOV	%EDX,%ECX

  (254) 0x420389 VMOVSD	-0x170(%RBP),%XMM3

  (254) 0x420391 VMOVSD	-0x178(%RBP),%XMM4

  (254) 0x420399 AND	$-0x8,%ECX

  (254) 0x42039c VMOVSD	-0x180(%RBP),%XMM5

  (254) 0x4203a4 VMOVSD	-0x188(%RBP),%XMM8

  (254) 0x4203ac VMOVSD	-0x190(%RBP),%XMM31

  (254) 0x4203b3 MOV	%ECX,%R9D

  (254) 0x4203b6 VEXTRACTF64X2	$0x1,%YMM7,%XMM11

  (254) 0x4203bd VADDPD	%XMM7,%XMM11,%XMM1

  (254) 0x4203c1 VUNPCKHPD	%XMM1,%XMM1,%XMM2

  (254) 0x4203c5 VADDPD	%XMM1,%XMM2,%XMM0

  (254) 0x4203c9 CMP	%EDX,%ECX

  (254) 0x4203cb JE	4208a9

  (254) 0x4203d1 MOV	%EDX,%R12D

  (254) 0x4203d4 SUB	%R9D,%R12D

  (254) 0x4203d7 LEA	-0x1(%R12),%R14D

  (254) 0x4203dc CMP	$0x2,%R14D

  (254) 0x4203e0 JBE	420653

  (254) 0x4203e6 LEA	(%RDI,%R9,8),%R9

  (254) 0x4203ea VMOVDDUP	%XMM3,%XMM10

  (254) 0x4203ee KMOVB	%K1,%K5

  (254) 0x4203f2 VMOVDDUP	%XMM5,%XMM7

  (254) 0x4203f6 VMULPD	(%R9),%XMM10,%XMM2

  (254) 0x4203fb VMULPD	0x10(%R9),%XMM10,%XMM1

  (254) 0x420401 VMOVDDUP	%XMM4,%XMM30

  (254) 0x420407 VMOVDDUP	-0x50(%RBP),%XMM26

  (254) 0x42040e VMOVDDUP	%XMM8,%XMM17

  (254) 0x420414 VMOVDDUP	-0x120(%RBP),%XMM11

  (254) 0x42041c VMOVDDUP	-0x118(%RBP),%XMM25

  (254) 0x420423 VMOVDDUP	-0x130(%RBP),%XMM24

  (254) 0x42042a KMOVB	%K1,%K4

  (254) 0x42042e VMOVDDUP	-0x128(%RBP),%XMM16

  (254) 0x420435 KMOVB	%K1,%K7

  (254) 0x420439 VMOVDDUP	-0x140(%RBP),%XMM6

  (254) 0x420441 KMOVB	%K1,%K6

  (254) 0x420445 VMOVDDUP	-0x160(%RBP),%XMM9

  (254) 0x42044d VMOVDDUP	-0x138(%RBP),%XMM23

  (254) 0x420454 VMOVDDUP	-0x150(%RBP),%XMM22

  (254) 0x42045b VMOVDDUP	-0x148(%RBP),%XMM15

  (254) 0x420463 VMOVDDUP	-0x158(%RBP),%XMM20

  (254) 0x42046a VMOVDDUP	-0x168(%RBP),%XMM19

  (254) 0x420471 VMOVDDUP	%XMM31,%XMM13

  (254) 0x420477 KMOVB	%K1,%K3

  (254) 0x42047b KMOVB	%K1,%K2

  (254) 0x42047f VINSERTF64X2	$0x1,%XMM1,%YMM2,%YMM12

  (254) 0x420486 VCVTTPD2DQ	%YMM12,%XMM10

  (254) 0x42048b VRNDSCALEPD	$0xb,%XMM2,%XMM14

  (254) 0x420492 VPSHUFD	$-0x12,%XMM10,%XMM27

  (254) 0x420499 VGATHERDPD	(%RAX,%XMM27,8),%XMM29{%K5}

  (254) 0x4204a0 KMOVB	%K1,%K5

  (254) 0x4204a4 VGATHERDPD	(%RAX,%XMM10,8),%XMM28{%K4}

  (254) 0x4204ab KMOVB	%K1,%K4

  (254) 0x4204af VRNDSCALEPD	$0xb,%XMM1,%XMM12

  (254) 0x4204b6 VSUBPD	%XMM14,%XMM2,%XMM2

  (254) 0x4204bb VSUBPD	%XMM12,%XMM1,%XMM1

  (254) 0x4204c0 VMULPD	%XMM2,%XMM2,%XMM12

  (254) 0x4204c4 VMULPD	%XMM1,%XMM1,%XMM18

  (254) 0x4204ca VMULPD	%XMM12,%XMM2,%XMM14

  (254) 0x4204cf VMULPD	%XMM7,%XMM12,%XMM27

  (254) 0x4204d5 VMULPD	%XMM18,%XMM1,%XMM21

  (254) 0x4204db VMULPD	%XMM7,%XMM18,%XMM7

  (254) 0x4204e1 VFMADD231PD	%XMM30,%XMM14,%XMM27

  (254) 0x4204e7 VFMADD231PD	%XMM30,%XMM21,%XMM7

  (254) 0x4204ed VMOVAPD	%XMM2,%XMM30

  (254) 0x4204f3 VFMADD132PD	%XMM17,%XMM26,%XMM30

  (254) 0x4204f9 VFMADD132PD	%XMM1,%XMM26,%XMM17

  (254) 0x4204ff VADDPD	%XMM17,%XMM7,%XMM7

  (254) 0x420505 VADDPD	%XMM27,%XMM30,%XMM26

  (254) 0x42050b VMULPD	%XMM11,%XMM12,%XMM27

  (254) 0x420511 VMULPD	%XMM11,%XMM18,%XMM11

  (254) 0x420517 VMULPD	%XMM29,%XMM7,%XMM7

  (254) 0x42051d VFMADD231PD	%XMM25,%XMM14,%XMM27

  (254) 0x420523 VFMADD231PD	%XMM25,%XMM21,%XMM11

  (254) 0x420529 VMOVAPD	%XMM2,%XMM25

  (254) 0x42052f VFMADD132PD	%XMM16,%XMM24,%XMM25

  (254) 0x420535 VFMADD132PD	%XMM1,%XMM24,%XMM16

  (254) 0x42053b VFMADD231PD	%XMM26,%XMM28,%XMM7

  (254) 0x420541 VPADDD	-0x1a0(%RBP),%XMM10,%XMM28

  (254) 0x420548 VADDPD	%XMM16,%XMM11,%XMM11

  (254) 0x42054e VADDPD	%XMM25,%XMM27,%XMM24

  (254) 0x420554 VPADDD	0x19f722(%RIP),%XMM10,%XMM16

  (254) 0x42055e VPADDD	0x19f73a(%RIP),%XMM10,%XMM10

  (254) 0x420566 VPSHUFD	$-0x12,%XMM28,%XMM29

  (254) 0x42056d VGATHERDPD	(%RAX,%XMM29,8),%XMM30{%K7}

  (254) 0x420574 VGATHERDPD	(%RAX,%XMM28,8),%XMM17{%K6}

  (254) 0x42057b VMULPD	%XMM30,%XMM11,%XMM11

  (254) 0x420581 VPSHUFD	$-0x12,%XMM16,%XMM28

  (254) 0x420588 VFMADD132PD	%XMM24,%XMM11,%XMM17

  (254) 0x42058e VGATHERDPD	(%RAX,%XMM28,8),%XMM11{%K3}

  (254) 0x420595 VADDPD	%XMM7,%XMM17,%XMM26

  (254) 0x42059b VMULPD	%XMM6,%XMM12,%XMM17

  (254) 0x4205a1 VMULPD	%XMM6,%XMM18,%XMM6

  (254) 0x4205a7 VGATHERDPD	(%RAX,%XMM16,8),%XMM7{%K2}

  (254) 0x4205ae VMULPD	%XMM9,%XMM12,%XMM12

  (254) 0x4205b3 VMULPD	%XMM9,%XMM18,%XMM9

  (254) 0x4205b9 VFMADD231PD	%XMM23,%XMM14,%XMM17

  (254) 0x4205bf VFMADD231PD	%XMM23,%XMM21,%XMM6

  (254) 0x4205c5 VMOVAPD	%XMM2,%XMM23

  (254) 0x4205cb VFMADD132PD	%XMM15,%XMM22,%XMM23

  (254) 0x4205d1 VFMADD132PD	%XMM1,%XMM22,%XMM15

  (254) 0x4205d7 VFMADD132PD	%XMM19,%XMM13,%XMM2

  (254) 0x4205dd VFMADD231PD	%XMM20,%XMM21,%XMM9

  (254) 0x4205e3 VFMADD231PD	%XMM19,%XMM1,%XMM13

  (254) 0x4205e9 VFMADD132PD	%XMM20,%XMM12,%XMM14

  (254) 0x4205ef VADDPD	%XMM15,%XMM6,%XMM15

  (254) 0x4205f4 VADDPD	%XMM23,%XMM17,%XMM22

  (254) 0x4205fa VADDPD	%XMM13,%XMM9,%XMM13

  (254) 0x4205ff VADDPD	%XMM2,%XMM14,%XMM2

  (254) 0x420603 VMULPD	%XMM11,%XMM15,%XMM6

  (254) 0x420608 VPSHUFD	$-0x12,%XMM10,%XMM15

  (254) 0x42060e VGATHERDPD	(%RAX,%XMM15,8),%XMM11{%K5}

  (254) 0x420615 VMULPD	%XMM11,%XMM13,%XMM1

  (254) 0x42061a VFMADD231PD	%XMM22,%XMM7,%XMM6

  (254) 0x420620 VGATHERDPD	(%RAX,%XMM10,8),%XMM7{%K4}

  (254) 0x420627 VFMADD132PD	%XMM2,%XMM1,%XMM7

  (254) 0x42062c VADDPD	%XMM6,%XMM7,%XMM14

  (254) 0x420630 VADDPD	%XMM26,%XMM14,%XMM6

  (254) 0x420636 VUNPCKHPD	%XMM6,%XMM6,%XMM10

  (254) 0x42063a VADDPD	%XMM6,%XMM10,%XMM7

  (254) 0x42063e VADDSD	%XMM7,%XMM0,%XMM0

  (254) 0x420642 TEST	$0x3,%R12B

  (254) 0x420646 JE	4208a9

  (254) 0x42064c AND	$-0x4,%R12D

  (254) 0x420650 ADD	%R12D,%ECX

  (254) 0x420653 MOVSXD	%ECX,%R8

  (254) 0x420656 VMOVSD	-0x50(%RBP),%XMM12

  (254) 0x42065b VMOVAPD	%XMM12,%XMM9

  (254) 0x420660 VMOVSD	-0x128(%RBP),%XMM14

  (254) 0x420668 VMULSD	(%RDI,%R8,8),%XMM3,%XMM15

  (254) 0x42066e VRNDSCALESD	$0xb,%XMM15,%XMM15,%XMM11

  (254) 0x420675 VSUBSD	%XMM11,%XMM15,%XMM1

  (254) 0x42067a VMULSD	%XMM1,%XMM1,%XMM6

  (254) 0x42067e VFMADD231SD	%XMM8,%XMM1,%XMM9

  (254) 0x420683 VMULSD	%XMM6,%XMM1,%XMM7

  (254) 0x420687 VMULSD	%XMM5,%XMM6,%XMM2

  (254) 0x42068b VFMADD231SD	%XMM7,%XMM4,%XMM2

  (254) 0x420690 VCVTTSD2SI	%XMM15,%R14D

  (254) 0x420695 VMOVAPD	%XMM14,%XMM13

  (254) 0x42069a MOVSXD	%R14D,%R9

  (254) 0x42069d VMOVSD	-0x120(%RBP),%XMM11

  (254) 0x4206a5 VMOVSD	-0x118(%RBP),%XMM18

  (254) 0x4206ac VMOVSD	-0x130(%RBP),%XMM29

  (254) 0x4206b3 VFMADD132SD	%XMM1,%XMM29,%XMM13

  (254) 0x4206b9 VMOVSD	-0x140(%RBP),%XMM19

  (254) 0x4206c0 VMOVSD	-0x138(%RBP),%XMM15

  (254) 0x4206c8 VMULSD	%XMM19,%XMM6,%XMM10

  (254) 0x4206ce VMOVSD	-0x150(%RBP),%XMM20

  (254) 0x4206d5 VFMADD231SD	%XMM15,%XMM7,%XMM10

  (254) 0x4206da VADDSD	%XMM9,%XMM2,%XMM2

  (254) 0x4206df VFMADD132SD	(%RAX,%R9,8),%XMM0,%XMM2

  (254) 0x4206e5 VMULSD	%XMM11,%XMM6,%XMM0

  (254) 0x4206ea VFMADD231SD	%XMM18,%XMM7,%XMM0

  (254) 0x4206f0 VMOVSD	-0x160(%RBP),%XMM21

  (254) 0x4206f7 VMOVSD	-0x158(%RBP),%XMM30

  (254) 0x4206fe VMULSD	%XMM21,%XMM6,%XMM6

  (254) 0x420704 VMOVSD	-0x168(%RBP),%XMM27

  (254) 0x42070b VFMADD132SD	%XMM30,%XMM6,%XMM7

  (254) 0x420711 LEA	(,%R8,8),%R12

  (254) 0x420719 LEA	0x1(%RCX),%R8D

  (254) 0x42071d VADDSD	%XMM13,%XMM0,%XMM0

  (254) 0x420722 VMOVSD	-0x148(%RBP),%XMM13

  (254) 0x42072a VMOVAPD	%XMM13,%XMM9

  (254) 0x42072f VFMADD132SD	%XMM1,%XMM20,%XMM9

  (254) 0x420735 VFMADD132SD	%XMM27,%XMM31,%XMM1

  (254) 0x42073b VADDSD	%XMM10,%XMM9,%XMM10

  (254) 0x420740 VADDSD	%XMM7,%XMM1,%XMM1

  (254) 0x420744 VMULSD	0x10(%RAX,%R9,8),%XMM10,%XMM9

  (254) 0x42074b VFMADD132SD	0x18(%RAX,%R9,8),%XMM2,%XMM1

  (254) 0x420752 VFMADD132SD	0x8(%RAX,%R9,8),%XMM9,%XMM0

  (254) 0x420759 VADDSD	%XMM1,%XMM0,%XMM0

  (254) 0x42075d CMP	%EDX,%R8D

  (254) 0x420760 JGE	4208a9

  (254) 0x420766 VMOVAPD	%XMM12,%XMM9

  (254) 0x42076b VMULSD	0x8(%RDI,%R12,1),%XMM3,%XMM7

  (254) 0x420772 VRNDSCALESD	$0xb,%XMM7,%XMM7,%XMM2

  (254) 0x420779 VSUBSD	%XMM2,%XMM7,%XMM1

  (254) 0x42077d VMULSD	%XMM1,%XMM1,%XMM2

  (254) 0x420781 VFMADD231SD	%XMM1,%XMM8,%XMM9

  (254) 0x420786 VMULSD	%XMM1,%XMM2,%XMM6

  (254) 0x42078a VMULSD	%XMM2,%XMM5,%XMM10

  (254) 0x42078e VFMADD231SD	%XMM6,%XMM4,%XMM10

  (254) 0x420793 VCVTTSD2SI	%XMM7,%R14D

  (254) 0x420797 MOVSXD	%R14D,%R9

  (254) 0x42079a ADD	$0x2,%ECX

  (254) 0x42079d VADDSD	%XMM10,%XMM9,%XMM7

  (254) 0x4207a2 VFMADD132SD	(%RAX,%R9,8),%XMM0,%XMM7

  (254) 0x4207a8 VMOVAPD	%XMM14,%XMM0

  (254) 0x4207ac VMULSD	%XMM11,%XMM2,%XMM10

  (254) 0x4207b1 VFMADD132SD	%XMM1,%XMM29,%XMM0

  (254) 0x4207b7 VFMADD231SD	%XMM18,%XMM6,%XMM10

  (254) 0x4207bd VMOVAPD	%XMM13,%XMM9

  (254) 0x4207c2 VFMADD132SD	%XMM1,%XMM20,%XMM9

  (254) 0x4207c8 VFMADD132SD	%XMM27,%XMM31,%XMM1

  (254) 0x4207ce VADDSD	%XMM10,%XMM0,%XMM0

  (254) 0x4207d3 VMULSD	%XMM19,%XMM2,%XMM10

  (254) 0x4207d9 VMULSD	%XMM21,%XMM2,%XMM2

  (254) 0x4207df VFMADD231SD	%XMM15,%XMM6,%XMM10

  (254) 0x4207e4 VFMADD132SD	%XMM30,%XMM2,%XMM6

  (254) 0x4207ea VADDSD	%XMM10,%XMM9,%XMM10

  (254) 0x4207ef VMULSD	0x10(%RAX,%R9,8),%XMM10,%XMM9

  (254) 0x4207f6 VFMADD132SD	0x8(%RAX,%R9,8),%XMM9,%XMM0

  (254) 0x4207fd VADDSD	%XMM6,%XMM1,%XMM1

  (254) 0x420801 VFMADD132SD	0x18(%RAX,%R9,8),%XMM7,%XMM1

  (254) 0x420808 VADDSD	%XMM1,%XMM0,%XMM0

  (254) 0x42080c CMP	%EDX,%ECX

  (254) 0x42080e JGE	4208a9

  (254) 0x420814 VMULSD	0x10(%RDI,%R12,1),%XMM3,%XMM3

  (254) 0x42081b VRNDSCALESD	$0xb,%XMM3,%XMM3,%XMM6

  (254) 0x420822 VSUBSD	%XMM6,%XMM3,%XMM7

  (254) 0x420826 VMULSD	%XMM7,%XMM7,%XMM2

  (254) 0x42082a VFMADD132SD	%XMM7,%XMM12,%XMM8

  (254) 0x42082f VMULSD	%XMM2,%XMM7,%XMM1

  (254) 0x420833 VMULSD	%XMM2,%XMM5,%XMM5

  (254) 0x420837 VFMADD132SD	%XMM1,%XMM5,%XMM4

  (254) 0x42083c VFMADD132SD	%XMM7,%XMM29,%XMM14

  (254) 0x420842 VFMADD132SD	%XMM7,%XMM20,%XMM13

  (254) 0x420848 VMULSD	%XMM21,%XMM2,%XMM9

  (254) 0x42084e VCVTTSD2SI	%XMM3,%EDI

  (254) 0x420852 VFMADD231SD	%XMM30,%XMM1,%XMM9

  (254) 0x420858 VFMADD132SD	%XMM27,%XMM31,%XMM7

  (254) 0x42085e MOVSXD	%EDI,%RDX

  (254) 0x420861 VADDSD	%XMM4,%XMM8,%XMM8

  (254) 0x420865 VMULSD	%XMM11,%XMM2,%XMM4

  (254) 0x42086a VMULSD	%XMM19,%XMM2,%XMM11

  (254) 0x420870 VFMADD231SD	%XMM18,%XMM1,%XMM4

  (254) 0x420876 VFMADD132SD	%XMM1,%XMM11,%XMM15

  (254) 0x42087b VFMADD132SD	(%RAX,%RDX,8),%XMM0,%XMM8

  (254) 0x420881 VADDSD	%XMM9,%XMM7,%XMM10

  (254) 0x420886 VFMADD132SD	0x18(%RAX,%RDX,8),%XMM8,%XMM10

  (254) 0x42088d VADDSD	%XMM14,%XMM4,%XMM12

  (254) 0x420892 VADDSD	%XMM15,%XMM13,%XMM0

  (254) 0x420897 VMULSD	0x10(%RAX,%RDX,8),%XMM0,%XMM3

  (254) 0x42089d VFMADD132SD	0x8(%RAX,%RDX,8),%XMM3,%XMM12

  (254) 0x4208a4 VADDSD	%XMM12,%XMM10,%XMM0

  (254) 0x4208a9 VADDSD	-0x48(%RBP),%XMM0,%XMM6

  (254) 0x4208ae VMOVSD	%XMM6,-0x48(%RBP)

  (254) 0x4208b3 ADD	$0x4,%RSI

  (254) 0x4208b7 CMP	%RSI,%R10

  (254) 0x4208ba JNE	41fd30

(252) 0x4208c0 VMOVQ	%R15,%XMM7

(252) 0x4208c5 MOV	-0x1a8(%RBP),%R14

(252) 0x4208cc MOV	-0x1b0(%RBP),%R15

(252) 0x4208d3 VSUBSD	-0x48(%RBP),%XMM7,%XMM7

(252) 0x4208d8 VZEROUPPER

(252) 0x4208db VMOVAPD	%XMM7,%XMM0

(252) 0x4208df CALL	4040b0 <exp@plt>

(252) 0x4208e4 MOV	(%R15),%RSI

(252) 0x4208e7 MOV	0x8(%R15),%R10

(252) 0x4208eb SUB	%RSI,%R10

(252) 0x4208ee VMOVSD	%XMM0,(%RSI,%R14,8)

(252) 0x4208f4 INC	%R14

(252) 0x4208f7 SAR	$0x3,%R10

(252) 0x4208fb CMP	%R10,%R14

(252) 0x4208fe JB	41fc80

0x420904 ADD	$0x1a0,%RSP

0x42090b POP	%RBX

0x42090c POP	%R11

0x42090e POP	%R12

0x420910 POP	%R13

0x420912 POP	%R14

0x420914 POP	%R15

0x420916 POP	%RBP

0x420917 LEA	-0x8(%R11),%RSP

0x42091b RET

0x42091c NOPL	(%RAX)

(252) 0x420920 MOV	0x90(%RBX),%R10D

(252) 0x420927 TEST	%R10D,%R10D

(252) 0x42092a JLE	4208db

(252) 0x42092c MOV	0xa0(%RBX),%RAX

(252) 0x420933 MOVSXD	%R10D,%RSI

(252) 0x420936 MOV	0x1c8(%RBX),%R13

(252) 0x42093d MOV	%R12,%RDX

(252) 0x420940 VXORPD	%XMM8,%XMM8,%XMM8

(252) 0x420945 MOV	0x18(%RAX),%RAX

(252) 0x420949 LEA	(%RAX,%RSI,4),%R10

(252) 0x42094d AND	$0x1,%ESI

(252) 0x420950 JE	420a88

(252) 0x420956 MOVSXD	(%RAX),%RDX

(252) 0x420959 MOV	(%R13,%RDX,8),%RDI

(252) 0x42095e TEST	%RDI,%RDI

(252) 0x420961 JE	420a76

(252) 0x420967 VMOVSD	(%R12),%XMM0

(252) 0x42096d VCOMISD	0x8(%RDI),%XMM0

(252) 0x420972 JAE	420a76

(252) 0x420978 VMULSD	0x238(%RDI),%XMM0,%XMM0

(252) 0x420980 MOV	%RDI,-0x70(%RBP)

(252) 0x420984 LEA	-0x38(%RBP),%RDI

(252) 0x420988 MOV	%R10,-0xf0(%RBP)

(252) 0x42098f VMOVSD	%XMM7,-0xd0(%RBP)

(252) 0x420997 MOV	%RAX,-0xb0(%RBP)

(252) 0x42099e VMOVSD	%XMM8,-0x90(%RBP)

(252) 0x4209a6 CALL	404320 <modf@plt>

(252) 0x4209ab MOV	-0x70(%RBP),%RCX

(252) 0x4209af MOV	-0xf0(%RBP),%R10

(252) 0x4209b6 MOV	-0xb0(%RBP),%RAX

(252) 0x4209bd VCVTTSD2SI	-0x38(%RBP),%R9D

(252) 0x4209c2 MOVSXD	%R9D,%R11

(252) 0x4209c5 VMULSD	%XMM0,%XMM0,%XMM4

(252) 0x4209c9 VMOVSD	-0x90(%RBP),%XMM7

(252) 0x4209d1 VMULSD	%XMM0,%XMM4,%XMM6

(252) 0x4209d5 MOV	0x218(%RCX),%R8

(252) 0x4209dc VMULSD	0x20(%RCX),%XMM4,%XMM3

(252) 0x4209e1 VMOVSD	0x28(%RCX),%XMM2

(252) 0x4209e6 VFMADD231SD	0x18(%RCX),%XMM6,%XMM3

(252) 0x4209ec VFMADD213SD	0x30(%RCX),%XMM0,%XMM2

(252) 0x4209f2 VMULSD	0x40(%RCX),%XMM4,%XMM9

(252) 0x4209f7 VADDSD	%XMM2,%XMM3,%XMM8

(252) 0x4209fb VFMADD231SD	0x38(%RCX),%XMM6,%XMM9

(252) 0x420a01 VMOVSD	0x48(%RCX),%XMM10

(252) 0x420a06 VMULSD	0x60(%RCX),%XMM4,%XMM12

(252) 0x420a0b VFMADD213SD	0x50(%RCX),%XMM0,%XMM10

(252) 0x420a11 VFMADD231SD	0x58(%RCX),%XMM6,%XMM12

(252) 0x420a17 VADDSD	%XMM10,%XMM9,%XMM11

(252) 0x420a1c VMOVSD	0x68(%RCX),%XMM13

(252) 0x420a21 VMULSD	0x80(%RCX),%XMM4,%XMM5

(252) 0x420a29 VFMADD213SD	0x70(%RCX),%XMM0,%XMM13

(252) 0x420a2f VFMADD132SD	0x78(%RCX),%XMM5,%XMM6

(252) 0x420a35 VADDSD	%XMM13,%XMM12,%XMM14

(252) 0x420a3a VMOVSD	0x90(%RCX),%XMM1

(252) 0x420a42 VFMADD132SD	0x88(%RCX),%XMM1,%XMM0

(252) 0x420a4b VFMADD132SD	(%R8,%R11,8),%XMM7,%XMM8

(252) 0x420a51 VMULSD	0x10(%R8,%R11,8),%XMM14,%XMM15

(252) 0x420a58 VADDSD	%XMM6,%XMM0,%XMM0

(252) 0x420a5c VFMADD132SD	0x8(%R8,%R11,8),%XMM15,%XMM11

(252) 0x420a63 VFMADD132SD	0x18(%R8,%R11,8),%XMM8,%XMM0

(252) 0x420a6a VMOVSD	-0xd0(%RBP),%XMM7

(252) 0x420a72 VADDSD	%XMM0,%XMM11,%XMM8

(252) 0x420a76 ADD	$0x4,%RAX

(252) 0x420a7a LEA	0x8(%R12),%RDX

(252) 0x420a7f CMP	%R10,%RAX

(252) 0x420a82 JE	420cfd

(252) 0x420a88 MOV	%R14,-0xd0(%RBP)

(252) 0x420a8f MOV	%RBX,-0x110(%RBP)

(252) 0x420a96 MOV	%R13,%R14

(252) 0x420a99 MOV	%R15,-0x48(%RBP)

(252) 0x420a9d MOV	%R10,%R13

(252) 0x420aa0 MOV	%RDX,%RBX

(252) 0x420aa3 MOV	%RAX,%R15

(252) 0x420aa6 VMOVSD	%XMM7,-0xf0(%RBP)

  (253) 0x420aae MOVSXD	(%R15),%R12

  (253) 0x420ab1 MOV	(%R14,%R12,8),%R12

  (253) 0x420ab5 TEST	%R12,%R12

  (253) 0x420ab8 JE	420bae

  (253) 0x420abe VMOVSD	(%RBX),%XMM4

  (253) 0x420ac2 VCOMISD	0x8(%R12),%XMM4

  (253) 0x420ac9 JAE	420bae

  (253) 0x420acf LEA	-0x38(%RBP),%RDI

  (253) 0x420ad3 VMOVSD	%XMM8,-0x70(%RBP)

  (253) 0x420ad8 VMULSD	0x238(%R12),%XMM4,%XMM0

  (253) 0x420ae2 CALL	404320 <modf@plt>

  (253) 0x420ae7 MOV	0x218(%R12),%RDI

  (253) 0x420aef VCVTTSD2SI	-0x38(%RBP),%ESI

  (253) 0x420af4 MOVSXD	%ESI,%RCX

  (253) 0x420af7 VMULSD	%XMM0,%XMM0,%XMM3

  (253) 0x420afb VMOVSD	0x28(%R12),%XMM2

  (253) 0x420b02 VMULSD	%XMM0,%XMM3,%XMM8

  (253) 0x420b06 VFMADD213SD	0x30(%R12),%XMM0,%XMM2

  (253) 0x420b0d VMULSD	0x20(%R12),%XMM3,%XMM6

  (253) 0x420b14 VMOVSD	-0x70(%RBP),%XMM9

  (253) 0x420b19 VFMADD231SD	0x18(%R12),%XMM8,%XMM6

  (253) 0x420b20 VMULSD	0x40(%R12),%XMM3,%XMM10

  (253) 0x420b27 VADDSD	%XMM2,%XMM6,%XMM7

  (253) 0x420b2b VFMADD231SD	0x38(%R12),%XMM8,%XMM10

  (253) 0x420b32 VMOVSD	0x48(%R12),%XMM11

  (253) 0x420b39 VMULSD	0x60(%R12),%XMM3,%XMM13

  (253) 0x420b40 VFMADD213SD	0x50(%R12),%XMM0,%XMM11

  (253) 0x420b47 VFMADD231SD	0x58(%R12),%XMM8,%XMM13

  (253) 0x420b4e VADDSD	%XMM11,%XMM10,%XMM12

  (253) 0x420b53 VMOVSD	0x68(%R12),%XMM14

  (253) 0x420b5a VFMADD132SD	(%RDI,%RCX,8),%XMM9,%XMM7

  (253) 0x420b60 VFMADD213SD	0x70(%R12),%XMM0,%XMM14

  (253) 0x420b67 VMULSD	0x80(%R12),%XMM3,%XMM1

  (253) 0x420b71 VADDSD	%XMM14,%XMM13,%XMM15

  (253) 0x420b76 VFMADD132SD	0x78(%R12),%XMM1,%XMM8

  (253) 0x420b7d VMULSD	0x10(%RDI,%RCX,8),%XMM15,%XMM5

  (253) 0x420b83 VMOVSD	0x90(%R12),%XMM4

  (253) 0x420b8d VFMADD132SD	0x8(%RDI,%RCX,8),%XMM5,%XMM12

  (253) 0x420b94 VFMADD132SD	0x88(%R12),%XMM4,%XMM0

  (253) 0x420b9e VADDSD	%XMM8,%XMM0,%XMM0

  (253) 0x420ba3 VFMADD132SD	0x18(%RDI,%RCX,8),%XMM7,%XMM0

  (253) 0x420baa VADDSD	%XMM0,%XMM12,%XMM8

  (253) 0x420bae LEA	0x4(%R15),%R8

  (253) 0x420bb2 MOVSXD	0x4(%R15),%R15

  (253) 0x420bb6 LEA	0x8(%RBX),%R9

  (253) 0x420bba MOV	(%R14,%R15,8),%R12

  (253) 0x420bbe TEST	%R12,%R12

  (253) 0x420bc1 JE	420cd2

  (253) 0x420bc7 VMOVSD	0x8(%RBX),%XMM3

  (253) 0x420bcc VCOMISD	0x8(%R12),%XMM3

  (253) 0x420bd3 JAE	420cd2

  (253) 0x420bd9 LEA	-0x38(%RBP),%RDI

  (253) 0x420bdd VMOVSD	%XMM8,-0xb0(%RBP)

  (253) 0x420be5 MOV	%R9,-0x90(%RBP)

  (253) 0x420bec MOV	%R8,-0x70(%RBP)

  (253) 0x420bf0 VMULSD	0x238(%R12),%XMM3,%XMM0

  (253) 0x420bfa CALL	404320 <modf@plt>

  (253) 0x420bff MOV	0x218(%R12),%RBX

  (253) 0x420c07 MOV	-0x90(%RBP),%R9

  (253) 0x420c0e MOV	-0x70(%RBP),%R8

  (253) 0x420c12 VCVTTSD2SI	-0x38(%RBP),%EAX

  (253) 0x420c17 CLTQ

  (253) 0x420c19 VMULSD	%XMM0,%XMM0,%XMM8

  (253) 0x420c1d VMOVSD	0x28(%R12),%XMM2

  (253) 0x420c24 VMULSD	%XMM0,%XMM8,%XMM7

  (253) 0x420c28 VMULSD	0x20(%R12),%XMM8,%XMM6

  (253) 0x420c2f VFMADD213SD	0x30(%R12),%XMM0,%XMM2

  (253) 0x420c36 VFMADD231SD	0x18(%R12),%XMM7,%XMM6

  (253) 0x420c3d VMULSD	0x40(%R12),%XMM8,%XMM11

  (253) 0x420c44 VMULSD	0x60(%R12),%XMM8,%XMM14

  (253) 0x420c4b VFMADD231SD	0x38(%R12),%XMM7,%XMM11

  (253) 0x420c52 VFMADD231SD	0x58(%R12),%XMM7,%XMM14

  (253) 0x420c59 VMULSD	0x80(%R12),%XMM8,%XMM4

  (253) 0x420c63 VADDSD	%XMM2,%XMM6,%XMM9

  (253) 0x420c67 VMOVSD	-0xb0(%RBP),%XMM10

  (253) 0x420c6f VMOVSD	0x48(%R12),%XMM12

  (253) 0x420c76 VFMADD132SD	(%RBX,%RAX,8),%XMM10,%XMM9

  (253) 0x420c7c VFMADD213SD	0x50(%R12),%XMM0,%XMM12

  (253) 0x420c83 VMOVSD	0x68(%R12),%XMM15

  (253) 0x420c8a VADDSD	%XMM12,%XMM11,%XMM13

  (253) 0x420c8f VFMADD213SD	0x70(%R12),%XMM0,%XMM15

  (253) 0x420c96 VFMADD132SD	0x78(%R12),%XMM4,%XMM7

  (253) 0x420c9d VADDSD	%XMM15,%XMM14,%XMM5

  (253) 0x420ca2 VMOVSD	0x90(%R12),%XMM3

  (253) 0x420cac VMULSD	0x10(%RBX,%RAX,8),%XMM5,%XMM1

  (253) 0x420cb2 VFMADD132SD	0x88(%R12),%XMM3,%XMM0

  (253) 0x420cbc VFMADD132SD	0x8(%RBX,%RAX,8),%XMM1,%XMM13

  (253) 0x420cc3 VADDSD	%XMM7,%XMM0,%XMM0

  (253) 0x420cc7 VFMADD132SD	0x18(%RBX,%RAX,8),%XMM9,%XMM0

  (253) 0x420cce VADDSD	%XMM0,%XMM13,%XMM8

  (253) 0x420cd2 LEA	0x4(%R8),%R15

  (253) 0x420cd6 LEA	0x8(%R9),%RBX

  (253) 0x420cda CMP	%R13,%R15

  (253) 0x420cdd JNE	420aae

(252) 0x420ce3 MOV	-0xd0(%RBP),%R14

(252) 0x420cea MOV	-0x110(%RBP),%RBX

(252) 0x420cf1 MOV	-0x48(%RBP),%R15

(252) 0x420cf5 VMOVSD	-0xf0(%RBP),%XMM7

(252) 0x420cfd VSUBSD	%XMM8,%XMM7,%XMM7

(252) 0x420d02 JMP	4208db

  (254) 0x420d07 XOR	%R9D,%R9D

  (254) 0x420d0a XOR	%ECX,%ECX

  (254) 0x420d0c VXORPD	%XMM0,%XMM0,%XMM0

  (254) 0x420d10 JMP	4203d1

0x420d15 NOPW	%CS:(%RAX,%RAX,1)

0x420d1f NOP

Coverage (%)	Name	Source Location	Module
►95.90+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.16+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	main	miniqmc.cpp:409	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	miniqmc.cpp:321	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131,1147-1150
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.25 to 1.00 cycles (4.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 4.25 to 0.31 cycles (13.77x speedup).

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132
VPBROADCASTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	37
nb uops	34
loop length	135
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.50	1.50	1.50	1.50	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50
cycles	1.50	1.50	1.50	1.50	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	1.50
Overall L1	4.25

Vectorization ratios

all	12%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.25 cycles. At this rate:

2% of peak load performance is reached (5.65 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.25 to 1.50 cycles (2.83x speedup).

ASM code

In the binary file, the address of the function is: 41fc20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.71	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VPBROADCASTD %EAX,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1	scal (6.3%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x1a0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %XMM5,-0x1a0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RSI,-0x1b8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %RCX,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 420904 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xce4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1a0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x8(%R11),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131,1147-1150
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.25 to 1.00 cycles (4.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132
VPBROADCASTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	37
nb uops	34
loop length	135
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.50	1.50	1.50	1.50	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50
cycles	1.50	1.50	1.50	1.50	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Dispatch	1.50
Overall L1	4.25

Vectorization ratios

all	12%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.25 cycles. At this rate:

2% of peak load performance is reached (5.65 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41fc20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.71	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VPBROADCASTD %EAX,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1	scal (6.3%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x1a0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %XMM5,-0x1a0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RSI,-0x1b8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %RCX,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 420904 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xce4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1a0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x8(%R11),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	0.02	0.04
▼Loop 252 - OneBodyJastrowRef.h:134-155 - exec–	0.00	0.01
▼Loop 254 - OneBodyJastrowRef.h:143-146 - exec–	0.00	0.01
○Loop 255 - BsplineFunctor.h:236-241 - exec	0.02	0.03
○Loop 256 - BsplineFunctor.h:246-260 - exec	0.00	0.00
○Loop 253 - OneBodyJastrowRef.h:151-155 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code