OV - exec - Loop 399

	Loop Id: 399	Module: exec	Source: BsplineFunctor.h:302-336 [...]	Coverage: 0.03%

0x42ce20 MOVAPD	(%R10,%RDI,8),%XMM3    [1]

0x42ce26 MOVAPD	%XMM1,%XMM0

0x42ce2a MULPD	%XMM3,%XMM0

0x42ce2e CVTTPD2DQ	%XMM0,%XMM6

0x42ce32 CVTDQ2PD	%XMM6,%XMM2

0x42ce36 SUBPD	%XMM2,%XMM0

0x42ce3a MOVAPD	%XMM0,%XMM13

0x42ce3f XORPD	%XMM2,%XMM2

0x42ce43 MULPD	%XMM0,%XMM13

0x42ce48 PCMPGTD	%XMM6,%XMM2

0x42ce4c PUNPCKLDQ	%XMM2,%XMM6

0x42ce50 PSLLQ	$0x3,%XMM6

0x42ce55 MOVQ	(%RAX,%RDI,4),%XMM2    [18]

0x42ce5a PADDQ	-0x540(%RBP),%XMM6    [5]

0x42ce62 MOVQ	%XMM6,%R11

0x42ce67 PSHUFD	$-0x12,%XMM6,%XMM5

0x42ce6c MOVQ	%XMM5,%R14

0x42ce71 MOVSD	(%R11),%XMM5    [4]

0x42ce76 MOVDQA	%XMM6,%XMM8

0x42ce7b PADDQ	0xfd88c(%RIP),%XMM8    [15]

0x42ce84 MOVQ	%XMM8,%R11

0x42ce89 PSHUFD	$-0x12,%XMM8,%XMM8

0x42ce8f MOVDQA	%XMM6,%XMM9

0x42ce94 MOVHPD	(%R14),%XMM5    [14]

0x42ce99 PADDQ	0xfd87e(%RIP),%XMM9    [15]

0x42cea2 MOVQ	%XMM9,%R13

0x42cea7 PSHUFD	$-0x12,%XMM9,%XMM9

0x42cead MOVQ	%XMM8,%R14

0x42ceb2 PADDQ	0xfd876(%RIP),%XMM6    [15]

0x42ceba MOVQ	%XMM6,%R12

0x42cebf PSHUFD	$-0x12,%XMM6,%XMM8

0x42cec5 MOVQ	%XMM9,%R15

0x42ceca MOVSD	(%R12),%XMM6    [8]

0x42ced0 MOVQ	%XMM8,%R12

0x42ced5 MOVAPD	-0x530(%RBP),%XMM11    [5]

0x42cede MOVSD	(%R11),%XMM9    [3]

0x42cee3 MULPD	%XMM0,%XMM11

0x42cee8 MOVAPD	-0x510(%RBP),%XMM10    [5]

0x42cef1 MULPD	%XMM0,%XMM10

0x42cef6 MOVSD	(%R13),%XMM8    [10]

0x42cefc PXOR	%XMM12,%XMM12

0x42cf01 PCMPGTD	%XMM2,%XMM12

0x42cf06 MOVHPD	(%R12),%XMM6    [7]

0x42cf0c PUNPCKLDQ	%XMM12,%XMM2

0x42cf11 PADDQ	-0x4a0(%RBP),%XMM2    [5]

0x42cf19 MOVHPD	(%R14),%XMM9    [13]

0x42cf1e PSLLQ	$0x3,%XMM2

0x42cf23 MOVDQA	-0x490(%RBP),%XMM12    [5]

0x42cf2c MOVHPD	(%R15),%XMM8    [17]

0x42cf31 PADDQ	%XMM2,%XMM12

0x42cf36 MOVQ	%XMM12,%R14

0x42cf3b PSHUFD	$-0x12,%XMM12,%XMM12

0x42cf41 ADDPD	-0x520(%RBP),%XMM11    [5]

0x42cf4a MOVQ	%XMM12,%R15

0x42cf4f MOVAPD	-0x480(%RBP),%XMM12    [5]

0x42cf58 MOVAPD	-0x470(%RBP),%XMM14    [5]

0x42cf61 ADDPD	-0x500(%RBP),%XMM10    [5]

0x42cf6a MULPD	%XMM0,%XMM14

0x42cf6f ADDPD	-0x460(%RBP),%XMM14    [5]

0x42cf78 MOVAPD	-0x450(%RBP),%XMM4    [5]

0x42cf80 MULPD	%XMM13,%XMM12

0x42cf85 MULPD	%XMM13,%XMM4

0x42cf8a MOVAPD	-0x440(%RBP),%XMM15    [5]

0x42cf93 MULPD	%XMM0,%XMM15

0x42cf98 ADDPD	%XMM12,%XMM14

0x42cf9d ADDPD	-0x430(%RBP),%XMM15    [5]

0x42cfa6 ADDPD	%XMM4,%XMM15

0x42cfab MOVAPD	-0x420(%RBP),%XMM4    [5]

0x42cfb3 MULPD	%XMM5,%XMM14

0x42cfb8 MULPD	%XMM13,%XMM4

0x42cfbd MOVAPD	-0x410(%RBP),%XMM7    [5]

0x42cfc5 MULPD	%XMM0,%XMM7

0x42cfc9 MULPD	%XMM9,%XMM15

0x42cfce ADDPD	-0x400(%RBP),%XMM7    [5]

0x42cfd6 ADDPD	%XMM4,%XMM7

0x42cfda MOVAPD	-0x3f0(%RBP),%XMM4    [5]

0x42cfe2 ADDPD	%XMM14,%XMM15

0x42cfe7 MULPD	%XMM13,%XMM4

0x42cfec MOVAPD	-0x3e0(%RBP),%XMM12    [5]

0x42cff5 MULPD	%XMM0,%XMM12

0x42cffa MULPD	%XMM8,%XMM7

0x42cfff ADDPD	-0x3d0(%RBP),%XMM12    [5]

0x42d008 ADDPD	%XMM4,%XMM12

0x42d00d MULPD	%XMM6,%XMM12

0x42d012 MOVAPD	%XMM13,%XMM14

0x42d017 ADDPD	%XMM7,%XMM12

0x42d01c MOVAPD	-0x4f0(%RBP),%XMM4    [5]

0x42d024 MULPD	%XMM0,%XMM4

0x42d028 MULPD	%XMM5,%XMM11

0x42d02d ADDPD	-0x4e0(%RBP),%XMM4    [5]

0x42d035 ADDPD	%XMM15,%XMM12

0x42d03a MOVAPD	-0x4d0(%RBP),%XMM15    [5]

0x42d043 MULPD	%XMM9,%XMM10

0x42d048 MULPD	%XMM0,%XMM15

0x42d04d ADDPD	-0x4c0(%RBP),%XMM15    [5]

0x42d056 MULPD	%XMM6,%XMM15

0x42d05b ADDPD	%XMM11,%XMM10

0x42d060 MOVDQA	-0x3c0(%RBP),%XMM7    [5]

0x42d068 PADDQ	%XMM2,%XMM7

0x42d06c MOVQ	%XMM7,%R12

0x42d071 MULPD	%XMM8,%XMM4

0x42d076 PSHUFD	$-0x12,%XMM7,%XMM7

0x42d07b MOVQ	%XMM7,%R13

0x42d080 MOVAPD	-0x3a0(%RBP),%XMM7    [5]

0x42d088 ADDPD	%XMM4,%XMM15

0x42d08d MULPD	%XMM13,%XMM7

0x42d092 MOVAPD	-0x390(%RBP),%XMM11    [5]

0x42d09b MULPD	%XMM0,%XMM11

0x42d0a0 MULPD	%XMM0,%XMM14

0x42d0a5 ADDPD	%XMM7,%XMM11

0x42d0aa MOVAPD	-0x3b0(%RBP),%XMM4    [5]

0x42d0b2 MULPD	%XMM14,%XMM4

0x42d0b7 ADDPD	%XMM10,%XMM15

0x42d0bc ADDPD	-0x380(%RBP),%XMM11    [5]

0x42d0c5 MOVAPD	-0x360(%RBP),%XMM7    [5]

0x42d0cd MULPD	%XMM13,%XMM7

0x42d0d2 ADDPD	%XMM4,%XMM11

0x42d0d7 MOVAPD	-0x350(%RBP),%XMM10    [5]

0x42d0e0 MULPD	%XMM0,%XMM10

0x42d0e5 ADDPD	%XMM7,%XMM10

0x42d0ea MOVAPD	-0x370(%RBP),%XMM4    [5]

0x42d0f2 MULPD	%XMM14,%XMM4

0x42d0f7 ADDPD	-0x340(%RBP),%XMM10    [5]

0x42d100 ADDPD	%XMM4,%XMM10

0x42d105 MULPD	%XMM5,%XMM11

0x42d10a MULPD	%XMM9,%XMM10

0x42d10f MOVAPD	-0x320(%RBP),%XMM4    [5]

0x42d117 MOVAPD	-0x310(%RBP),%XMM5    [5]

0x42d11f MULPD	%XMM13,%XMM4

0x42d124 MULPD	%XMM0,%XMM5

0x42d128 ADDPD	%XMM4,%XMM5

0x42d12c MOVAPD	-0x330(%RBP),%XMM4    [5]

0x42d134 MULPD	%XMM14,%XMM4

0x42d139 ADDPD	-0x300(%RBP),%XMM5    [5]

0x42d141 ADDPD	%XMM4,%XMM5

0x42d145 MULPD	%XMM1,%XMM12

0x42d14a DIVPD	%XMM3,%XMM12

0x42d14f MULPD	-0x2e0(%RBP),%XMM13    [5]

0x42d158 MULPD	-0x2d0(%RBP),%XMM0    [5]

0x42d160 ADDPD	%XMM13,%XMM0

0x42d165 MULPD	%XMM8,%XMM5

0x42d16a MULPD	-0x2f0(%RBP),%XMM14    [5]

0x42d173 ADDPD	-0x2c0(%RBP),%XMM0    [5]

0x42d17b ADDPD	%XMM14,%XMM0

0x42d180 ADDPD	%XMM11,%XMM10

0x42d185 MULPD	%XMM6,%XMM0

0x42d189 MULPD	-0x4b0(%RBP),%XMM15    [5]

0x42d192 MOVLPD	%XMM15,(%R14)    [12]

0x42d197 MOVHPD	%XMM15,(%R15)    [16]

0x42d19c ADDPD	%XMM5,%XMM0

0x42d1a0 ADDPD	%XMM10,%XMM0

0x42d1a5 PADDQ	-0x2b0(%RBP),%XMM2    [5]

0x42d1ad MOVQ	%XMM2,%R11

0x42d1b2 PSHUFD	$-0x12,%XMM2,%XMM2

0x42d1b7 MOVQ	%XMM2,%R14

0x42d1bc MOVLPD	%XMM12,(%R12)    [6]

0x42d1c2 MOVHPD	%XMM12,(%R13)    [9]

0x42d1c8 MOVLPD	%XMM0,(%R11)    [2]

0x42d1cd MOVHPD	%XMM0,(%R14)    [11]

0x42d1d2 ADD	$0x2,%RDI

0x42d1d6 CMP	%RBX,%RDI

0x42d1d9 JB	42ce20

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 302 - 336

--------------------------------------------------------------------------------

302:   #pragma omp simd

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1064 - 1064

--------------------------------------------------------------------------------

1064: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module
►52.90+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	_ZN11qmcplusplus12WaveFunction[...]	WaveFunction.cpp:201	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►35.01+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	_ZN11qmcplusplus12WaveFunction[...]	NewTimer.h:249	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►5.85+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	_ZN11qmcplusplus12WaveFunction[...]	WaveFunction.cpp:175	exec
○	main.extracted.112	miniqmc.cpp:397	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.87+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:218	exec
○	miniqmcreference::OneBodyJastr[...]	stl_vector.h:1169	exec
○	_ZN11qmcplusplus12WaveFunction[...]	WaveFunction.cpp:201	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.56+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	_ZN11qmcplusplus12WaveFunction[...]	WaveFunction.cpp:201	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stl_uninitialized.h:99	exec
►1.13+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	_ZN11qmcplusplus12WaveFunction[...]	NewTimer.h:249	exec
○	main.extracted.107	refwrap.h:338	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stl_uninitialized.h:99	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.74
CQA speedup if fully vectorized	4.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P10, P11, P12, P13,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:302-336,stl_vector.h:1064-1064
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	26.50
CQA cycles if no scalar integer	26.50
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	6.31
Front-end cycles	20.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	15.25
P7 cycles	15.25
P8 cycles	15.25
P9 cycles	15.25
P10 cycles	26.50
P11 cycles	26.50
P12 cycles	26.50
P13 cycles	26.50
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	164.00
Nb loads	55.00
Nb stores	6.00
Nb stack references	42.00
FLOP/cycle	5.74
Nb FLOP add-sub	68.00
Nb FLOP mul	82.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.30
Bytes prefetched	0.00
Bytes loaded	808.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	81.76
Vectorization ratio load	83.64
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	61.11
Vector-efficiency ratio all	22.48
Vector-efficiency ratio load	22.95
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	19.10

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.74
CQA speedup if fully vectorized	4.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P10, P11, P12, P13,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:302-336,stl_vector.h:1064-1064
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	26.50
CQA cycles if no scalar integer	26.50
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	6.31
Front-end cycles	20.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	15.25
P7 cycles	15.25
P8 cycles	15.25
P9 cycles	15.25
P10 cycles	26.50
P11 cycles	26.50
P12 cycles	26.50
P13 cycles	26.50
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	164.00
Nb loads	55.00
Nb stores	6.00
Nb stack references	42.00
FLOP/cycle	5.74
Nb FLOP add-sub	68.00
Nb FLOP mul	82.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.30
Bytes prefetched	0.00
Bytes loaded	808.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	81.76
Vectorization ratio load	83.64
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	61.11
Vector-efficiency ratio all	22.48
Vector-efficiency ratio load	22.95
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	19.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:302-336
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:302-336
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 26.50 to 6.31 cycles (4.20x speedup).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

83% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
61% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 26.50 to 20.50 cycles (1.29x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVHPD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 7 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTDQ2PD (INT32 to FP64, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

76 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 152 FP arithmetical operations:

68: addition or subtraction
82: multiply
2: divide

The binary loop is loading 808 bytes (101 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	162
nb uops	164
loop length	959
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	42
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	15.25	15.25	15.25	15.25	26.50	26.50	26.50	26.50	10.00	10.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	15.25	15.25	15.25	15.25	26.50	26.50	26.50	26.50	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	20.50
Dispatch	26.50
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	26.50

Vectorization ratios

INT

all	64%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	54%

all	88%
load	82%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	81%
load	83%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	61%

Vector efficiency ratios

INT

all	19%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	23%
load	22%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	22%
load	22%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.50 cycles. At this rate:

11% of peak load performance is reached (30.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ce20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVAPD (%R10,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
CVTTPD2DQ %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
CVTDQ2PD %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (12.5%)
SUBPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD %XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XORPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULPD %XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
PCMPGTD %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PSLLQ $0x3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVQ (%RAX,%RDI,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PADDQ -0x540(%RBP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM6,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM5,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%R11),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PADDQ 0xfd88c(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVHPD (%R14),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PADDQ 0xfd87e(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ 0xfd876(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM6,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVQ %XMM8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPD -0x530(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVSD (%R11),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x510(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVSD (%R13),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PXOR %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVHPD (%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PUNPCKLDQ %XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PADDQ -0x4a0(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVHPD (%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PSLLQ $0x3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA -0x490(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVHPD (%R15),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PADDQ %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM12,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ADDPD -0x520(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVQ %XMM12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPD -0x480(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x470(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x500(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x460(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x450(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x440(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD -0x430(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x420(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM5,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x410(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x400(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x3f0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x3e0(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x3d0(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADDPD %XMM7,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x4f0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM5,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x4e0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM15,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x4d0(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x4c0(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVDQA -0x3c0(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PADDQ %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM7,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM7,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPD -0x3a0(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM13,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x390(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM7,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x3b0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM10,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD -0x380(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x360(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM4,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x350(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x370(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x340(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM5,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x320(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x310(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x330(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x300(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
DIVPD %XMM3,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
MULPD -0x2e0(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD -0x2d0(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD -0x2f0(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x2c0(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD -0x4b0(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVLPD %XMM15,(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM15,(%R15)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
ADDPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
PADDQ -0x2b0(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM2,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVLPD %XMM12,(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM12,(%R13)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
MOVLPD %XMM0,(%R11)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM0,(%R14)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
ADD $0x2,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 42ce20 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x590>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:302-336
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:302-336
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

83% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
61% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 26.50 to 20.50 cycles (1.29x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVHPD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 7 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:315
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:318
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:316
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:317
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:321
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:327
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:333

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTDQ2PD (INT32 to FP64, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:310
CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

76 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 152 FP arithmetical operations:

68: addition or subtraction
82: multiply
2: divide

The binary loop is loading 808 bytes (101 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	162
nb uops	164
loop length	959
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	42
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	15.25	15.25	15.25	15.25	26.50	26.50	26.50	26.50	10.00	10.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	15.25	15.25	15.25	15.25	26.50	26.50	26.50	26.50	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	20.50
Dispatch	26.50
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	26.50

Vectorization ratios

INT

all	64%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	54%

all	88%
load	82%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	81%
load	83%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	61%

Vector efficiency ratios

INT

all	19%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	23%
load	22%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	22%
load	22%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.50 cycles. At this rate:

11% of peak load performance is reached (30.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ce20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVAPD (%R10,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
CVTTPD2DQ %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
CVTDQ2PD %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (12.5%)
SUBPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD %XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XORPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULPD %XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
PCMPGTD %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PSLLQ $0x3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVQ (%RAX,%RDI,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PADDQ -0x540(%RBP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM6,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM5,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%R11),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVDQA %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PADDQ 0xfd88c(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVHPD (%R14),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PADDQ 0xfd87e(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ 0xfd876(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM6,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVQ %XMM8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPD -0x530(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVSD (%R11),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x510(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVSD (%R13),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PXOR %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVHPD (%R12),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PUNPCKLDQ %XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PADDQ -0x4a0(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVHPD (%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PSLLQ $0x3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA -0x490(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVHPD (%R15),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PADDQ %XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM12,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ADDPD -0x520(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVQ %XMM12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPD -0x480(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x470(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x500(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x460(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x450(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x440(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD -0x430(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x420(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM5,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x410(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x400(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x3f0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x3e0(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x3d0(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADDPD %XMM7,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x4f0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM5,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x4e0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM15,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x4d0(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x4c0(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVDQA -0x3c0(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PADDQ %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM7,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM7,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPD -0x3a0(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM13,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x390(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM7,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x3b0(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM10,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD -0x380(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x360(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM4,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x350(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x370(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x340(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM5,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x320(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD -0x310(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVAPD -0x330(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MULPD %XMM14,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x300(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
DIVPD %XMM3,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (25.0%)
MULPD -0x2e0(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD -0x2d0(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD -0x2f0(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
ADDPD -0x2c0(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MULPD %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MULPD -0x4b0(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVLPD %XMM15,(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM15,(%R15)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
ADDPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
PADDQ -0x2b0(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM2,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM2,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVLPD %XMM12,(%R12)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM12,(%R13)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
MOVLPD %XMM0,(%R11)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM0,(%R14)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
ADD $0x2,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 42ce20 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x590>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

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Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

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Slow data structures access

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Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code