OV - exec - Function qmcplusplus::Vector<double, std::allocator<double> >::resize(unsigned long, double)

	Function: qmcplusplus::Vector<double, std::allocator<double> >::resize(unsigned long, double)	Module: exec	Source: OhmmsVector.h:182-302 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 111 - 145

--------------------------------------------------------------------------------

111: 	if (__builtin_expect(__n > this->_M_max_size(), false))

112: 	  {

113: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

114: 	    // 3190. allocator::allocate sometimes returns too little storage

115: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

116: 	      std::__throw_bad_array_new_length();

117: 	    std::__throw_bad_alloc();

[...]

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 924

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 182 - 302

--------------------------------------------------------------------------------

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

302:     nAllocated = n;

0x42b770 PUSH	%RBP

0x42b771 MOV	%RSP,%RBP

0x42b774 PUSH	%R14

0x42b776 PUSH	%RBX

0x42b777 SUB	$0x10,%RSP

0x42b77b MOV	0x8(%RDI),%RAX

0x42b77f MOV	0x10(%RDI),%RCX

0x42b783 CMP	%RCX,%RAX

0x42b786 JA	42b940

0x42b78c MOV	%RSI,%RBX

0x42b78f MOV	%RDI,%R14

0x42b792 CMP	%RSI,%RCX

0x42b795 JAE	42b86b

0x42b79b TEST	%RCX,%RCX

0x42b79e MOVSD	%XMM0,-0x18(%RBP)

0x42b7a3 JE	42b7ae

0x42b7a5 MOV	0x18(%R14),%RDI

0x42b7a9 CALL	4052f0 <_ZdlPv@plt>

0x42b7ae MOV	%RBX,%RAX

0x42b7b1 SHR	$0x3c,%RAX

0x42b7b5 JNE	42b930

0x42b7bb LEA	(,%RBX,8),%RDI

0x42b7c3 CALL	4056c0 <_Znwm@plt>

0x42b7c8 MOVSD	-0x18(%RBP),%XMM0

0x42b7cd MOV	%RAX,0x18(%R14)

0x42b7d1 MOV	%RBX,0x8(%R14)

0x42b7d5 MOV	%RBX,0x10(%R14)

0x42b7d9 CMP	$0x8,%RBX

0x42b7dd JB	42b820

0x42b7df MOV	%RBX,%RCX

0x42b7e2 SHR	$0x3,%RCX

0x42b7e6 LEA	0x38(%RAX),%RDX

0x42b7ea NOPW	(%RAX,%RAX,1)

(385) 0x42b7f0 MOVSD	%XMM0,-0x38(%RDX)

(385) 0x42b7f5 MOVSD	%XMM0,-0x30(%RDX)

(385) 0x42b7fa MOVSD	%XMM0,-0x28(%RDX)

(385) 0x42b7ff MOVSD	%XMM0,-0x20(%RDX)

(385) 0x42b804 MOVSD	%XMM0,-0x18(%RDX)

(385) 0x42b809 MOVSD	%XMM0,-0x10(%RDX)

(385) 0x42b80e MOVSD	%XMM0,-0x8(%RDX)

(385) 0x42b813 MOVSD	%XMM0,(%RDX)

(385) 0x42b817 ADD	$0x40,%RDX

(385) 0x42b81b DEC	%RCX

(385) 0x42b81e JNE	42b7f0

0x42b820 MOV	%EBX,%ECX

0x42b822 AND	$0x7,%ECX

0x42b825 DEC	%RCX

0x42b828 CMP	$0x6,%RCX

0x42b82c JA	42b927

0x42b832 AND	$-0x8,%RBX

0x42b836 JMP	0x52ab38(,%RCX,8)

0x42b83d MOVSD	%XMM0,0x30(%RAX,%RBX,8)

0x42b843 MOVSD	%XMM0,0x28(%RAX,%RBX,8)

0x42b849 MOVSD	%XMM0,0x20(%RAX,%RBX,8)

0x42b84f MOVSD	%XMM0,0x18(%RAX,%RBX,8)

0x42b855 MOVSD	%XMM0,0x10(%RAX,%RBX,8)

0x42b85b MOVSD	%XMM0,0x8(%RAX,%RBX,8)

0x42b861 MOVSD	%XMM0,(%RAX,%RBX,8)

0x42b866 JMP	42b927

0x42b86b MOV	%RBX,%RDX

0x42b86e SUB	%RAX,%RDX

0x42b871 JBE	42b923

0x42b877 MOV	0x18(%R14),%RCX

0x42b87b CMP	$0x8,%RDX

0x42b87f JB	42b8c0

0x42b881 MOV	%RDX,%RSI

0x42b884 SHR	$0x3,%RSI

0x42b888 LEA	(%RCX,%RAX,8),%RDI

0x42b88c ADD	$0x38,%RDI

(384) 0x42b890 MOVSD	%XMM0,-0x38(%RDI)

(384) 0x42b895 MOVSD	%XMM0,-0x30(%RDI)

(384) 0x42b89a MOVSD	%XMM0,-0x28(%RDI)

(384) 0x42b89f MOVSD	%XMM0,-0x20(%RDI)

(384) 0x42b8a4 MOVSD	%XMM0,-0x18(%RDI)

(384) 0x42b8a9 MOVSD	%XMM0,-0x10(%RDI)

(384) 0x42b8ae MOVSD	%XMM0,-0x8(%RDI)

(384) 0x42b8b3 MOVSD	%XMM0,(%RDI)

(384) 0x42b8b7 ADD	$0x40,%RDI

(384) 0x42b8bb DEC	%RSI

(384) 0x42b8be JNE	42b890

0x42b8c0 MOV	%EDX,%ESI

0x42b8c2 AND	$0x7,%ESI

0x42b8c5 DEC	%RSI

0x42b8c8 CMP	$0x6,%RSI

0x42b8cc JA	42b923

0x42b8ce AND	$-0x8,%RDX

0x42b8d2 JMP	0x52ab00(,%RSI,8)

0x42b8d9 ADD	%RDX,%RAX

0x42b8dc JMP	42b91e

0x42b8de ADD	%RDX,%RAX

0x42b8e1 JMP	42b918

0x42b8e3 ADD	%RDX,%RAX

0x42b8e6 JMP	42b912

0x42b8e8 ADD	%RDX,%RAX

0x42b8eb JMP	42b90c

0x42b8ed ADD	%RDX,%RAX

0x42b8f0 JMP	42b906

0x42b8f2 ADD	%RDX,%RAX

0x42b8f5 JMP	42b900

0x42b8f7 ADD	%RDX,%RAX

0x42b8fa MOVSD	%XMM0,0x30(%RCX,%RAX,8)

0x42b900 MOVSD	%XMM0,0x28(%RCX,%RAX,8)

0x42b906 MOVSD	%XMM0,0x20(%RCX,%RAX,8)

0x42b90c MOVSD	%XMM0,0x18(%RCX,%RAX,8)

0x42b912 MOVSD	%XMM0,0x10(%RCX,%RAX,8)

0x42b918 MOVSD	%XMM0,0x8(%RCX,%RAX,8)

0x42b91e MOVSD	%XMM0,(%RCX,%RAX,8)

0x42b923 MOV	%RBX,0x8(%R14)

0x42b927 ADD	$0x10,%RSP

0x42b92b POP	%RBX

0x42b92c POP	%R14

0x42b92e POP	%RBP

0x42b92f RET

0x42b930 SHR	$0x3d,%RBX

0x42b934 JE	42b93b

0x42b936 CALL	405880 <_ZSt28__throw_bad_array_new_lengthv@plt>

0x42b93b CALL	4056b0 <_ZSt17__throw_bad_allocv@plt>

0x42b940 MOV	$0x10,%EDI

0x42b945 CALL	405850 <__cxa_allocate_exception@plt>

0x42b94a MOV	%RAX,%RBX

0x42b94d MOV	$0x52c0e2,%ESI

0x42b952 MOV	%RAX,%RDI

0x42b955 CALL	405160 <_ZNSt13runtime_errorC1EPKc@plt>

0x42b95a MOV	$0x598880,%ESI

0x42b95f MOV	$0x405b30,%EDX

0x42b964 MOV	%RBX,%RDI

0x42b967 CALL	405350 <__cxa_throw@plt>

0x42b96c MOV	%RAX,%R14

0x42b96f MOV	%RBX,%RDI

0x42b972 CALL	405b80 <__cxa_free_exception@plt>

0x42b977 MOV	%R14,%RDI

0x42b97a CALL	4053a0 <_Unwind_Resume@plt>

0x42b97f NOP

Coverage (%)	Name	Source Location	Module
►19.10+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:70	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	build_WaveFunction	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►17.76+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:101	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	build_WaveFunction	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►17.06+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:101	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	build_WaveFunction	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►17.01+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:70	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	build_WaveFunction	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►14.73+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	build_WaveFunction	WaveFunction.cpp:80	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.00+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	build_WaveFunction	WaveFunction.cpp:81	exec
○	main.extracted.112	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_3

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 7.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 1.18 cycles (12.69x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_Unwind_Resume@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_allocate_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_free_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_throw@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
operator delete(void*): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
operator new(unsigned long): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127
std::__throw_bad_alloc(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:117
std::__throw_bad_array_new_length(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:116
std::runtime_error::runtime_error(char const*): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	111
nb uops	120
loop length	432
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	10.33	10.33	10.33	11.00	11.00	11.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	7.50	7.50
cycles	10.33	10.33	10.33	11.00	11.00	11.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	7.50	7.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Dispatch	11.00
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (3.73 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 11.00 cycles (1.36x speedup).

ASM code

In the binary file, the address of the function is: 42b770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 42b940 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 42b86b <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xfb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVSD %XMM0,-0x18(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
JE 42b7ae <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CALL 4052f0 <_ZdlPv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
JNE 42b930 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CALL 4056c0 <_Znwm@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOVSD -0x18(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 42b820 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
LEA 0x38(%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %EBX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
DEC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 42b927 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 0x52ab38(,%RCX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	1	N/A
MOVSD %XMM0,0x30(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x28(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x18(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x8(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
JMP 42b927 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 42b923 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP $0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 42b8c0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x150>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
ADD $0x38,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 42b923 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 0x52ab00(,%RSI,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b91e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b918 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b912 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b90c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x19c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b906 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x196>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b900 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSD %XMM0,0x30(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x28(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x18(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x8(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
SHR $0x3d,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
JE 42b93b <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1cb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CALL 405880 <_ZSt28__throw_bad_array_new_lengthv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
CALL 4056b0 <_ZSt17__throw_bad_allocv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV $0x10,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CALL 405850 <__cxa_allocate_exception@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x52c0e2,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405160 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV $0x598880,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x405b30,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405350 <__cxa_throw@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405b80 <__cxa_free_exception@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4053a0 <_Unwind_Resume@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_3

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 7.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_Unwind_Resume@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_allocate_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_free_exception@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
__cxa_throw@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
operator delete(void*): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
operator new(unsigned long): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127
std::__throw_bad_alloc(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:117
std::__throw_bad_array_new_length(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:116
std::runtime_error::runtime_error(char const*): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	111
nb uops	120
loop length	432
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	10.33	10.33	10.33	11.00	11.00	11.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	7.50	7.50
cycles	10.33	10.33	10.33	11.00	11.00	11.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	7.50	7.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Dispatch	11.00
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (3.73 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42b770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 42b940 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 42b86b <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xfb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVSD %XMM0,-0x18(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
JE 42b7ae <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CALL 4052f0 <_ZdlPv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
JNE 42b930 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CALL 4056c0 <_Znwm@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOVSD -0x18(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 42b820 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
LEA 0x38(%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %EBX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
DEC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 42b927 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 0x52ab38(,%RCX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	1	N/A
MOVSD %XMM0,0x30(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x28(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x18(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x8(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,(%RAX,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
JMP 42b927 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 42b923 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP $0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 42b8c0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x150>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
ADD $0x38,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 42b923 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
AND $-0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 0x52ab00(,%RSI,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b91e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b918 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b912 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b90c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x19c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b906 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x196>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JMP 42b900 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSD %XMM0,0x30(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x28(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x18(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,0x8(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
SHR $0x3d,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
JE 42b93b <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1cb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CALL 405880 <_ZSt28__throw_bad_array_new_lengthv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
CALL 4056b0 <_ZSt17__throw_bad_allocv@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV $0x10,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CALL 405850 <__cxa_allocate_exception@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x52c0e2,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405160 <_ZNSt13runtime_errorC1EPKc@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV $0x598880,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x405b30,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405350 <__cxa_throw@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405b80 <__cxa_free_exception@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4053a0 <_Unwind_Resume@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::Vector >::resize(unsigned long, double)–	0.02	0.04
○Loop 385 - stl_algobase.h:923-924 - exec	0.02	0.04
○Loop 384 - stl_algobase.h:923-924 - exec	0.00	0.00

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Workaround

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CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code