OV - exec - Loop 714

	Loop Id: 714	Module: exec	Source: MultiBsplineRef.hpp:227-262 [...]	Coverage: 0.01%

0x2547c0 MOV	-0x80(%RBP),%RCX

0x2547c4 MOV	-0x130(%RBP),%RAX

0x2547cb MOV	-0x120(%RBP),%R11

0x2547d2 INC	%RCX

0x2547d5 ADD	%RAX,%RSI

0x2547d8 ADD	%RAX,%RDI

0x2547db ADD	%RAX,%R8

0x2547de ADD	%RAX,%RDX

0x2547e1 MOV	%RCX,%RAX

0x2547e4 CMP	$0x4,%RCX

0x2547e8 MOV	-0x128(%RBP),%RCX

0x2547ef JE	2546e0

0x2547f5 VMOVSD	-0x3b0(%RBP,%RAX,8),%XMM2

0x2547fe VMOVSD	-0x98(%RBP),%XMM4

0x254806 VMOVSD	-0x48(%RBP),%XMM5

0x25480b CMPL	$0x4,-0x70(%RBP)

0x25480f MOV	%RAX,-0x80(%RBP)

0x254813 SETBB	-0x50(%RBP)

0x254817 VMULSD	%XMM1,%XMM2,%XMM21

0x25481d VMULSD	%XMM2,%XMM4,%XMM26

0x254823 VMULSD	%XMM2,%XMM5,%XMM27

0x254829 VMOVSD	-0x2a0(%RBP,%RAX,8),%XMM2

0x254832 VMULSD	%XMM4,%XMM2,%XMM25

0x254838 VMULSD	%XMM5,%XMM2,%XMM29

0x25483e VMULSD	-0x260(%RBP,%RAX,8),%XMM5,%XMM2

0x254847 MOVZX	-0x50(%RBP),%EAX

0x25484b OR	-0x29(%RBP),%AL

0x25484e TEST	$0x1,%AL

0x254850 JE	254870

0x254852 MOV	-0x70(%RBP),%R11

0x254856 XOR	%EAX,%EAX

0x254858 VMOVAPD	%XMM2,%XMM24

0x25485e JMP	254c50

0x254870 MOV	%RDI,-0x108(%RBP)

0x254877 MOV	-0x88(%RBP),%RAX

0x25487e MOV	-0x80(%RBP),%RDI

0x254882 MOV	%RDX,-0x118(%RBP)

0x254889 MOV	-0x100(%RBP),%RDX

0x254890 VMOVDDUP	%XMM21,%XMM1

0x254896 VMOVAPD	%XMM21,-0x200(%RBP)

0x25489d VMOVAPD	%XMM25,-0x1f0(%RBP)

0x2548a4 VMOVAPD	-0x310(%RBP),%XMM21

0x2548ab VMOVAPD	-0x340(%RBP),%XMM20

0x2548b2 VMOVAPD	-0x330(%RBP),%XMM24

0x2548b9 MOV	%R8,-0x110(%RBP)

0x2548c0 VMOVAPD	%XMM2,-0x1e0(%RBP)

0x2548c8 VMOVDDUP	%XMM2,%XMM2

0x2548cc VMOVDDUP	%XMM26,%XMM23

0x2548d2 VMOVDDUP	%XMM29,%XMM6

0x2548d8 VMOVDDUP	%XMM27,%XMM7

0x2548de VMOVAPD	%XMM1,-0xd0(%RBP)

0x2548e6 VMOVDDUP	%XMM25,%XMM1

0x2548ec VMOVAPD	-0x320(%RBP),%XMM25

0x2548f3 VMOVAPD	%XMM2,-0x140(%RBP)

0x2548fb VMOVAPD	%XMM1,-0x150(%RBP)

0x254903 VMOVAPD	%XMM3,%XMM1

0x254907 VMOVAPD	%XMM31,%XMM3

0x25490d VMOVAPD	%XMM30,%XMM31

0x254913 VMOVAPD	-0x300(%RBP),%XMM30

0x25491a ADD	%RDI,%RAX

0x25491d IMUL	-0xb8(%RBP),%RAX

0x254925 LEA	(%RDX,%RAX,8),%RDI

0x254929 MOV	-0x68(%RBP),%RAX

0x25492d MOV	%RDI,-0x50(%RBP)

0x254931 LEA	(%RDI,%RAX,8),%RDX

0x254935 MOV	-0x230(%RBP),%RAX

0x25493c LEA	(%RDI,%RAX,8),%R8

0x254940 MOV	-0x238(%RBP),%RAX

0x254947 LEA	(%RDI,%RAX,8),%RDI

0x25494b XOR	%EAX,%EAX

0x25494d NOPL	(%RAX)

  (712) 0x254950 MOV	-0x50(%RBP),%R9

  (712) 0x254954 VMOVUPD	(%RSI,%RAX,8),%XMM4

  (712) 0x254959 VMOVUPD	(%RDX,%RAX,8),%XMM11

  (712) 0x25495e VMOVUPD	0x10(%RDX,%RAX,8),%XMM12

  (712) 0x254964 VMOVUPD	(%R8,%RAX,8),%XMM13

  (712) 0x25496a VMOVUPD	0x10(%R8,%RAX,8),%XMM14

  (712) 0x254971 VMOVUPD	(%RDI,%RAX,8),%XMM15

  (712) 0x254976 VMOVUPD	0x10(%RDI,%RAX,8),%XMM16

  (712) 0x25497e VMOVUPD	0x10(%R9,%RAX,8),%XMM5

  (712) 0x254985 LEA	(%R15,%RAX,8),%R9

  (712) 0x254989 VMULPD	%XMM22,%XMM4,%XMM8

  (712) 0x25498f VMULPD	%XMM25,%XMM4,%XMM10

  (712) 0x254995 VMULPD	%XMM31,%XMM4,%XMM4

  (712) 0x25499b VMULPD	%XMM24,%XMM11,%XMM17

  (712) 0x2549a1 VMULPD	%XMM24,%XMM12,%XMM18

  (712) 0x2549a7 VFMADD231PD	%XMM19,%XMM11,%XMM8

  (712) 0x2549ad VFMADD231PD	%XMM11,%XMM3,%XMM4

  (712) 0x2549b2 VFMADD231PD	%XMM30,%XMM13,%XMM10

  (712) 0x2549b8 VMOVUPD	(%R15,%RAX,8),%XMM11

  (712) 0x2549be VFMADD231PD	%XMM28,%XMM15,%XMM17

  (712) 0x2549c4 VFMADD231PD	%XMM28,%XMM16,%XMM18

  (712) 0x2549ca VMULPD	%XMM22,%XMM5,%XMM9

  (712) 0x2549d0 VMULPD	%XMM25,%XMM5,%XMM2

  (712) 0x2549d6 VMULPD	%XMM31,%XMM5,%XMM5

  (712) 0x2549dc VFMADD231PD	%XMM20,%XMM13,%XMM8

  (712) 0x2549e2 VFMADD231PD	%XMM13,%XMM1,%XMM4

  (712) 0x2549e7 VMOVAPD	-0xd0(%RBP),%XMM13

  (712) 0x2549ef VFMADD231PD	%XMM17,%XMM0,%XMM10

  (712) 0x2549f5 VFMADD231PD	%XMM19,%XMM12,%XMM9

  (712) 0x2549fb VFMADD231PD	%XMM12,%XMM3,%XMM5

  (712) 0x254a00 VMOVUPD	0x10(%R15,%RAX,8),%XMM12

  (712) 0x254a07 VFMADD231PD	%XMM30,%XMM14,%XMM2

  (712) 0x254a0d VFMADD231PD	%XMM15,%XMM21,%XMM8

  (712) 0x254a13 VFMADD231PD	%XMM15,%XMM0,%XMM4

  (712) 0x254a18 VFMADD231PD	%XMM20,%XMM14,%XMM9

  (712) 0x254a1e VFMADD231PD	%XMM18,%XMM0,%XMM2

  (712) 0x254a24 VFMADD231PD	%XMM14,%XMM1,%XMM5

  (712) 0x254a29 VFMADD231PD	%XMM8,%XMM13,%XMM11

  (712) 0x254a2e VFMADD231PD	%XMM16,%XMM21,%XMM9

  (712) 0x254a34 VFMADD231PD	%XMM16,%XMM0,%XMM5

  (712) 0x254a3a VMOVUPD	%XMM11,(%R15,%RAX,8)

  (712) 0x254a40 VFMADD231PD	%XMM9,%XMM13,%XMM12

  (712) 0x254a45 VMOVAPD	-0x150(%RBP),%XMM13

  (712) 0x254a4d VMOVUPD	%XMM12,0x10(%R15,%RAX,8)

  (712) 0x254a54 VMOVUPD	(%R10,%R9,1),%XMM11

  (712) 0x254a5a VMOVUPD	0x10(%R10,%R9,1),%XMM12

  (712) 0x254a61 VFMADD231PD	%XMM8,%XMM13,%XMM11

  (712) 0x254a66 VFMADD231PD	%XMM9,%XMM13,%XMM12

  (712) 0x254a6b VMOVAPD	-0x140(%RBP),%XMM13

  (712) 0x254a73 VMOVUPD	%XMM11,(%R10,%R9,1)

  (712) 0x254a79 VMOVUPD	%XMM12,0x10(%R10,%R9,1)

  (712) 0x254a80 LEA	(%R9,%R10,1),%R9

  (712) 0x254a84 VMOVUPD	(%R10,%R9,1),%XMM11

  (712) 0x254a8a VMOVUPD	0x10(%R10,%R9,1),%XMM12

  (712) 0x254a91 VFMADD231PD	%XMM23,%XMM10,%XMM11

  (712) 0x254a97 VFMADD231PD	%XMM23,%XMM2,%XMM12

  (712) 0x254a9d VMOVUPD	%XMM11,(%R10,%R9,1)

  (712) 0x254aa3 VMOVUPD	%XMM12,0x10(%R10,%R9,1)

  (712) 0x254aaa LEA	(%R9,%R10,1),%R9

  (712) 0x254aae VMOVUPD	(%R10,%R9,1),%XMM11

  (712) 0x254ab4 VMOVUPD	0x10(%R10,%R9,1),%XMM12

  (712) 0x254abb VFMADD231PD	%XMM8,%XMM13,%XMM11

  (712) 0x254ac0 VFMADD231PD	%XMM9,%XMM13,%XMM12

  (712) 0x254ac5 VMOVUPD	%XMM11,(%R10,%R9,1)

  (712) 0x254acb VMOVUPD	%XMM12,0x10(%R10,%R9,1)

  (712) 0x254ad2 LEA	(%R9,%R10,1),%R9

  (712) 0x254ad6 VMOVUPD	(%R10,%R9,1),%XMM11

  (712) 0x254adc VMOVUPD	0x10(%R10,%R9,1),%XMM12

  (712) 0x254ae3 VFMADD231PD	%XMM6,%XMM10,%XMM11

  (712) 0x254ae8 VFMADD231PD	%XMM6,%XMM2,%XMM12

  (712) 0x254aed VMOVUPD	%XMM11,(%R10,%R9,1)

  (712) 0x254af3 VMOVUPD	%XMM12,0x10(%R10,%R9,1)

  (712) 0x254afa LEA	(%R9,%R10,1),%R9

  (712) 0x254afe VFMADD213PD	(%R10,%R9,1),%XMM7,%XMM4

  (712) 0x254b04 VFMADD213PD	0x10(%R10,%R9,1),%XMM7,%XMM5

  (712) 0x254b0b VMOVUPD	%XMM4,(%R10,%R9,1)

  (712) 0x254b11 VMOVUPD	%XMM5,0x10(%R10,%R9,1)

  (712) 0x254b18 VMOVUPD	(%R14,%RAX,8),%XMM4

  (712) 0x254b1e VMOVUPD	0x10(%R14,%RAX,8),%XMM5

  (712) 0x254b25 VFMADD231PD	%XMM23,%XMM8,%XMM4

  (712) 0x254b2b VFMADD231PD	%XMM23,%XMM9,%XMM5

  (712) 0x254b31 VMOVUPD	%XMM4,(%R14,%RAX,8)

  (712) 0x254b37 VMOVUPD	%XMM5,0x10(%R14,%RAX,8)

  (712) 0x254b3e VMOVUPD	-0x10(%RCX,%RAX,8),%XMM4

  (712) 0x254b44 VMOVUPD	(%RCX,%RAX,8),%XMM5

  (712) 0x254b49 VFMADD231PD	%XMM6,%XMM8,%XMM4

  (712) 0x254b4e VFMADD231PD	%XMM6,%XMM9,%XMM5

  (712) 0x254b53 VFMADD213PD	(%RBX,%RAX,8),%XMM7,%XMM8

  (712) 0x254b59 VFMADD213PD	0x10(%RBX,%RAX,8),%XMM7,%XMM9

  (712) 0x254b60 VMOVUPD	%XMM4,-0x10(%RCX,%RAX,8)

  (712) 0x254b66 VMOVUPD	%XMM5,(%RCX,%RAX,8)

  (712) 0x254b6b VFMADD213PD	-0x10(%R11,%RAX,8),%XMM7,%XMM10

  (712) 0x254b72 VFMADD213PD	(%R11,%RAX,8),%XMM7,%XMM2

  (712) 0x254b78 VMOVUPD	%XMM8,(%RBX,%RAX,8)

  (712) 0x254b7d VMOVUPD	%XMM9,0x10(%RBX,%RAX,8)

  (712) 0x254b83 VMOVUPD	%XMM10,-0x10(%R11,%RAX,8)

  (712) 0x254b8a VMOVUPD	%XMM2,(%R11,%RAX,8)

  (712) 0x254b90 ADD	$0x4,%RAX

  (712) 0x254b94 CMP	%RAX,-0x40(%RBP)

  (712) 0x254b98 JNE	254950

0x254b9e VMOVAPD	%XMM31,%XMM30

0x254ba4 VMOVAPD	%XMM3,%XMM31

0x254baa VMOVAPD	%XMM1,%XMM3

0x254bae VMOVAPD	-0x180(%RBP),%XMM10

0x254bb6 VMOVAPD	-0x1d0(%RBP),%XMM11

0x254bbe VMOVAPD	-0x1c0(%RBP),%XMM12

0x254bc6 VMOVAPD	-0x1b0(%RBP),%XMM13

0x254bce VMOVAPD	-0x1a0(%RBP),%XMM23

0x254bd5 VMOVAPD	-0x190(%RBP),%XMM15

0x254bdd VMOVAPD	-0x390(%RBP),%XMM16

0x254be4 VMOVAPD	-0x380(%RBP),%XMM17

0x254beb VMOVAPD	-0x370(%RBP),%XMM18

0x254bf2 VMOVAPD	-0x360(%RBP),%XMM14

0x254bfa VMOVAPD	-0x350(%RBP),%XMM20

0x254c01 VMOVSD	-0xf8(%RBP),%XMM1

0x254c09 VMOVAPD	-0x200(%RBP),%XMM21

0x254c10 VMOVAPD	-0x1f0(%RBP),%XMM25

0x254c17 VMOVAPD	-0x1e0(%RBP),%XMM24

0x254c1e MOV	-0x40(%RBP),%RAX

0x254c22 CMPQ	$0,-0x228(%RBP)

0x254c2a MOV	-0x90(%RBP),%R9

0x254c31 MOV	-0x70(%RBP),%R11

0x254c35 MOV	-0x118(%RBP),%RDX

0x254c3c MOV	-0x110(%RBP),%R8

0x254c43 MOV	-0x108(%RBP),%RDI

0x254c4a JE	2547c0

  (715) 0x254c50 VMOVSD	(%RDI,%RAX,8),%XMM4

  (715) 0x254c55 VMOVSD	(%R8,%RAX,8),%XMM5

  (715) 0x254c5b VMOVSD	(%RSI,%RAX,8),%XMM2

  (715) 0x254c60 VMOVAPD	%XMM20,%XMM8

  (715) 0x254c66 VMOVSD	(%RDX,%RAX,8),%XMM6

  (715) 0x254c6b MOV	%RSI,%RCX

  (715) 0x254c6e MOV	%R13,%RSI

  (715) 0x254c71 MOV	%RDI,%R13

  (715) 0x254c74 MOV	%R8,%RDI

  (715) 0x254c77 MOV	%RDX,%R8

  (715) 0x254c7a LEA	(%R15,%RAX,8),%RDX

  (715) 0x254c7e VUNPCKLPD	%XMM5,%XMM4,%XMM7

  (715) 0x254c82 VMULSD	%XMM4,%XMM15,%XMM9

  (715) 0x254c86 VMULPD	%XMM7,%XMM14,%XMM7

  (715) 0x254c8a VFMADD231SD	%XMM11,%XMM6,%XMM9

  (715) 0x254c8f VFMADD213SD	%XMM7,%XMM2,%XMM8

  (715) 0x254c94 VSHUFPD	$0x1,%XMM7,%XMM7,%XMM7

  (715) 0x254c99 VADDSD	%XMM7,%XMM8,%XMM7

  (715) 0x254c9d VMULSD	%XMM2,%XMM12,%XMM8

  (715) 0x254ca1 VMULSD	%XMM16,%XMM2,%XMM2

  (715) 0x254ca7 VFMADD231SD	%XMM4,%XMM17,%XMM2

  (715) 0x254cad VMOVSD	(%R15,%RAX,8),%XMM4

  (715) 0x254cb3 VFMADD231SD	%XMM6,%XMM23,%XMM7

  (715) 0x254cb9 VFMADD231SD	%XMM13,%XMM5,%XMM8

  (715) 0x254cbe VFMADD231SD	%XMM9,%XMM10,%XMM8

  (715) 0x254cc3 VFMADD231SD	%XMM5,%XMM18,%XMM2

  (715) 0x254cc9 VFMADD231SD	%XMM7,%XMM21,%XMM4

  (715) 0x254ccf VFMADD231SD	%XMM6,%XMM10,%XMM2

  (715) 0x254cd4 VMOVSD	%XMM4,(%R15,%RAX,8)

  (715) 0x254cda VMOVSD	(%RDX,%R12,8),%XMM4

  (715) 0x254ce0 VFMADD231SD	%XMM7,%XMM25,%XMM4

  (715) 0x254ce6 VMOVSD	%XMM4,(%RDX,%R12,8)

  (715) 0x254cec LEA	(%RDX,%R12,8),%RDX

  (715) 0x254cf0 VMOVSD	(%R10,%RDX,1),%XMM4

  (715) 0x254cf6 VFMADD231SD	%XMM26,%XMM8,%XMM4

  (715) 0x254cfc VMOVSD	%XMM4,(%R10,%RDX,1)

  (715) 0x254d02 LEA	(%RDX,%R10,1),%RDX

  (715) 0x254d06 VMOVSD	(%R10,%RDX,1),%XMM4

  (715) 0x254d0c VFMADD231SD	%XMM7,%XMM24,%XMM4

  (715) 0x254d12 VMOVSD	%XMM4,(%R10,%RDX,1)

  (715) 0x254d18 LEA	(%RDX,%R10,1),%RDX

  (715) 0x254d1c VMOVSD	(%R10,%RDX,1),%XMM4

  (715) 0x254d22 VFMADD231SD	%XMM29,%XMM8,%XMM4

  (715) 0x254d28 VMOVSD	%XMM4,(%R10,%RDX,1)

  (715) 0x254d2e LEA	(%RDX,%R10,1),%RDX

  (715) 0x254d32 VFMADD213SD	(%R10,%RDX,1),%XMM27,%XMM2

  (715) 0x254d39 VMOVSD	%XMM2,(%R10,%RDX,1)

  (715) 0x254d3f VMOVSD	(%R14,%RAX,8),%XMM2

  (715) 0x254d45 MOV	%R8,%RDX

  (715) 0x254d48 MOV	%RDI,%R8

  (715) 0x254d4b MOV	%R13,%RDI

  (715) 0x254d4e MOV	%RSI,%R13

  (715) 0x254d51 MOV	%RCX,%RSI

  (715) 0x254d54 VFMADD231SD	%XMM26,%XMM7,%XMM2

  (715) 0x254d5a VMOVSD	%XMM2,(%R14,%RAX,8)

  (715) 0x254d60 VMOVSD	(%R9,%RAX,8),%XMM2

  (715) 0x254d66 VFMADD231SD	%XMM29,%XMM7,%XMM2

  (715) 0x254d6c VFMADD213SD	(%RBX,%RAX,8),%XMM27,%XMM7

  (715) 0x254d73 VMOVSD	%XMM2,(%R9,%RAX,8)

  (715) 0x254d79 VFMADD213SD	(%R13,%RAX,8),%XMM27,%XMM8

  (715) 0x254d81 VMOVSD	%XMM7,(%RBX,%RAX,8)

  (715) 0x254d86 VMOVSD	%XMM8,(%R13,%RAX,8)

  (715) 0x254d8d INC	%RAX

  (715) 0x254d90 CMP	%RAX,%R11

  (715) 0x254d93 JNE	254c50

0x254d99 JMP	2547c0

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 227 - 262

--------------------------------------------------------------------------------

227:     for (int j = 0; j < 4; j++)

[...]

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►83.46+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.43+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►5.74+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.57+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.75
CQA speedup if FP arith vectorized	1.31
CQA speedup if fully vectorized	6.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.08
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	8.44
CQA cycles if fully vectorized	1.71
Front-end cycles	9.13
P0 cycles	3.22
P1 cycles	3.22
P2 cycles	3.22
P3 cycles	3.22
P4 cycles	3.22
P5 cycles	3.22
P6 cycles	10.92
P7 cycles	10.92
P8 cycles	10.92
P9 cycles	10.92
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.67
Nb uops	73.00
Nb loads	35.00
Nb stores	8.67
Nb stack references	32.33
FLOP/cycle	0.54
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.83
Bytes prefetched	0.00
Bytes loaded	363.33
Bytes stored	94.33
Stride 0	0.67
Stride 1	0.00
Stride n	0.00
Stride unknown	14.67
Stride indirect	0.00
Vectorization ratio all	33.74
Vectorization ratio load	39.58
Vectorization ratio store	36.36
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	39.68
Vector-efficiency ratio all	16.56
Vector-efficiency ratio load	17.11
Vector-efficiency ratio store	17.05
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.47

Metric	Value
CQA speedup if no scalar integer	1.42
CQA speedup if FP arith vectorized	1.48
CQA speedup if fully vectorized	9.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.25
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	2.88
CQA cycles if fully vectorized	0.43
Front-end cycles	4.25
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	13.00
Nb stores	2.00
Nb stack references	9.00
FLOP/cycle	1.41
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.35
Bytes prefetched	0.00
Bytes loaded	86.00
Bytes stored	9.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	11.00
Stride indirect	0.00
Vectorization ratio all	4.35
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	12.77
Vector-efficiency ratio load	11.88
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.81
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	6.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	11.22
CQA cycles if fully vectorized	2.34
Front-end cycles	11.63
P0 cycles	3.67
P1 cycles	3.67
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	3.00
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	93.00
Nb loads	46.00
Nb stores	12.00
Nb stack references	44.00
FLOP/cycle	0.41
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	44.07
Bytes prefetched	0.00
Bytes loaded	502.00
Bytes stored	137.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	0.00
Vectorization ratio all	48.44
Vectorization ratio load	59.38
Vectorization ratio store	54.55
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	42.86
Vector-efficiency ratio all	18.46
Vector-efficiency ratio load	19.73
Vector-efficiency ratio store	19.32
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.41

Metric	Value
CQA speedup if no scalar integer	1.81
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	6.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	11.22
CQA cycles if fully vectorized	2.34
Front-end cycles	11.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	3.50
P6 cycles	14.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	3.00
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	92.00
Nb loads	46.00
Nb stores	12.00
Nb stack references	44.00
FLOP/cycle	0.41
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	44.07
Bytes prefetched	0.00
Bytes loaded	502.00
Bytes stored	137.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	11.00
Stride indirect	0.00
Vectorization ratio all	48.44
Vectorization ratio load	59.38
Vectorization ratio store	54.55
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	42.86
Vector-efficiency ratio all	18.46
Vector-efficiency ratio load	19.73
Vector-efficiency ratio store	19.32
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-239,242.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.08 to 1.71 cycles (6.50x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

39% of SSE/AVX loads are used in vector version.
36% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 363 bytes (45 double precision FP elements). The binary loop is storing 94 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	73.67
nb uops	73
loop length	423
used x86 registers	8.67
used mmx registers	0
used xmm registers	20.67
used ymm registers	0
used zmm registers	0
nb stack references	32.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.22	3.22	3.22	3.22	3.22	3.22	10.92	10.92	10.92	10.92	3.00	3.00	2.00	2.00	2.00	2.00
cycles	3.22	3.22	3.22	3.22	3.22	3.22	10.92	10.92	10.92	10.92	3.00	3.00	2.00	2.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.13
Dispatch	10.92
Data deps.	1.00
Overall L1	11.08

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	46%
load	50%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	33%
load	39%
store	36%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	18%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	16%
load	17%
store	17%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.08 cycles. At this rate:

11% of peak load performance is reached (29.83 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.25 to 3.00 cycles (1.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.25 to 0.43 cycles (9.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:239

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 86 bytes (10 double precision FP elements). The binary loop is storing 9 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	34
nb uops	34
loop length	168
used x86 registers	8
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.50	2.50	2.50	2.50	2.50	2.50	3.75	3.75	3.75	3.75	3.00	3.00	0.00	0.00	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	3.75	3.75	3.75	3.75	3.00	3.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	3.75
Data deps.	1.00
Overall L1	4.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	9%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

7% of peak load performance is reached (20.24 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.25 to 3.75 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 2547f5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x120(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x128(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
JE 2546e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x9b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x3b0(%RBP,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x98(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x48(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
CMPL $0x4,-0x70(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (6.3%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
SETBB -0x50(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	N/A
VMULSD %XMM1,%XMM2,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM4,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM5,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VMOVSD -0x2a0(%RBP,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VMULSD -0x260(%RBP,%RAX,8),%XMM5,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
MOVZX -0x50(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
OR -0x29(%RBP),%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
TEST $0x1,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 254870 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVAPD %XMM2,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 254c50 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xf20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
JMP 2547c0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 8.00 cycles (1.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.50 to 2.34 cycles (6.19x speedup).

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

59% of SSE/AVX loads are used in vector version.
54% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 11.63 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 22 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:239

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 502 bytes (62 double precision FP elements). The binary loop is storing 137 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	93
loop length	553
used x86 registers	9
used mmx registers	0
used xmm registers	26
used ymm registers	0
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.67	3.67	3.67	3.67	3.67	3.67	14.50	14.50	14.50	14.50	3.00	3.00	3.00	3.00	3.00	3.00
cycles	3.67	3.67	3.67	3.67	3.67	3.67	14.50	14.50	14.50	14.50	3.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.63
Dispatch	14.50
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	64%
load	76%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	48%
load	59%
store	54%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	20%
load	22%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	18%
load	19%
store	19%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

13% of peak load performance is reached (34.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2547f5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x120(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x128(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JE 2546e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x9b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x3b0(%RBP,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x98(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x48(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMPL $0x4,-0x70(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SETBB -0x50(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	N/A
VMULSD %XMM1,%XMM2,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM4,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM5,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD -0x2a0(%RBP,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD -0x260(%RBP,%RAX,8),%XMM5,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVZX -0x50(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
OR -0x29(%RBP),%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST $0x1,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 254870 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x88(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x118(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x100(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDDUP %XMM21,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD %XMM21,-0x200(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM25,-0x1f0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD -0x310(%RBP),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x340(%RBP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x330(%RBP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R8,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM2,-0x1e0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDDUP %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM26,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM29,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM27,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD %XMM1,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDDUP %XMM25,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD -0x320(%RBP),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD %XMM2,-0x140(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM1,-0x150(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM31,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM30,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD -0x300(%RBP),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0xb8(%RBP),%RAX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDX,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x230(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RAX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x238(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %XMM31,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM3,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD -0x180(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1d0(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1c0(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1b0(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1a0(%RBP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x190(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x390(%RBP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x380(%RBP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x370(%RBP),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x360(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x350(%RBP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0xf8(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD -0x200(%RBP),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1f0(%RBP),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1e0(%RBP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMPQ $0,-0x228(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV -0x90(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x118(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x110(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x108(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 2547c0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2547c0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 8.00 cycles (1.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

59% of SSE/AVX loads are used in vector version.
54% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 11.50 cycles (1.26x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:239

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 502 bytes (62 double precision FP elements). The binary loop is storing 137 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	92
loop length	548
used x86 registers	9
used mmx registers	0
used xmm registers	26
used ymm registers	0
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.50	3.50	3.50	3.50	3.50	3.50	14.50	14.50	14.50	14.50	3.00	3.00	3.00	3.00	3.00	3.00
cycles	3.50	3.50	3.50	3.50	3.50	3.50	14.50	14.50	14.50	14.50	3.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.50
Dispatch	14.50
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	64%
load	76%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	48%
load	59%
store	54%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	20%
load	22%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	18%
load	19%
store	19%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

13% of peak load performance is reached (34.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2547f5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x120(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x128(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JE 2546e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x9b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x3b0(%RBP,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x98(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x48(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMPL $0x4,-0x70(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SETBB -0x50(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	N/A
VMULSD %XMM1,%XMM2,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM4,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM5,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD -0x2a0(%RBP,%RAX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM5,%XMM2,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD -0x260(%RBP,%RAX,8),%XMM5,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVZX -0x50(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
OR -0x29(%RBP),%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST $0x1,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 254870 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x88(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x118(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x100(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDDUP %XMM21,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD %XMM21,-0x200(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM25,-0x1f0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD -0x310(%RBP),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x340(%RBP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x330(%RBP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R8,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM2,-0x1e0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDDUP %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM26,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM29,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM27,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD %XMM1,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDDUP %XMM25,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD -0x320(%RBP),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD %XMM2,-0x140(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM1,-0x150(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM31,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM30,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD -0x300(%RBP),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0xb8(%RBP),%RAX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDX,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDI,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x230(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RAX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x238(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %XMM31,%XMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM3,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD -0x180(%RBP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1d0(%RBP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1c0(%RBP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1b0(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1a0(%RBP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x190(%RBP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x390(%RBP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x380(%RBP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x370(%RBP),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x360(%RBP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x350(%RBP),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0xf8(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD -0x200(%RBP),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1f0(%RBP),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x1e0(%RBP),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMPQ $0,-0x228(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV -0x90(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x118(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x110(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x108(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 2547c0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

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Vectorization

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Execution units bottlenecks

Slow data structures access

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Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

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Vectorization

Details

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Execution units bottlenecks

Workaround

Slow data structures access

Details

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Conversion instructions

Details

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Conversion instructions