OV - exec - Loop 712

	Loop Id: 712	Module: exec	Source: MultiBsplineRef.hpp:242-262	Coverage: 10.05%

0x254950 MOV	-0x50(%RBP),%R9    [4]

0x254954 VMOVUPD	(%RSI,%RAX,8),%XMM4    [10]

0x254959 VMOVUPD	(%RDX,%RAX,8),%XMM11    [5]

0x25495e VMOVUPD	0x10(%RDX,%RAX,8),%XMM12    [5]

0x254964 VMOVUPD	(%R8,%RAX,8),%XMM13    [8]

0x25496a VMOVUPD	0x10(%R8,%RAX,8),%XMM14    [8]

0x254971 VMOVUPD	(%RDI,%RAX,8),%XMM15    [12]

0x254976 VMOVUPD	0x10(%RDI,%RAX,8),%XMM16    [12]

0x25497e VMOVUPD	0x10(%R9,%RAX,8),%XMM5    [9]

0x254985 LEA	(%R15,%RAX,8),%R9

0x254989 VMULPD	%XMM22,%XMM4,%XMM8

0x25498f VMULPD	%XMM25,%XMM4,%XMM10

0x254995 VMULPD	%XMM31,%XMM4,%XMM4

0x25499b VMULPD	%XMM24,%XMM11,%XMM17

0x2549a1 VMULPD	%XMM24,%XMM12,%XMM18

0x2549a7 VFMADD231PD	%XMM19,%XMM11,%XMM8

0x2549ad VFMADD231PD	%XMM11,%XMM3,%XMM4

0x2549b2 VFMADD231PD	%XMM30,%XMM13,%XMM10

0x2549b8 VMOVUPD	(%R15,%RAX,8),%XMM11    [7]

0x2549be VFMADD231PD	%XMM28,%XMM15,%XMM17

0x2549c4 VFMADD231PD	%XMM28,%XMM16,%XMM18

0x2549ca VMULPD	%XMM22,%XMM5,%XMM9

0x2549d0 VMULPD	%XMM25,%XMM5,%XMM2

0x2549d6 VMULPD	%XMM31,%XMM5,%XMM5

0x2549dc VFMADD231PD	%XMM20,%XMM13,%XMM8

0x2549e2 VFMADD231PD	%XMM13,%XMM1,%XMM4

0x2549e7 VMOVAPD	-0xd0(%RBP),%XMM13    [4]

0x2549ef VFMADD231PD	%XMM17,%XMM0,%XMM10

0x2549f5 VFMADD231PD	%XMM19,%XMM12,%XMM9

0x2549fb VFMADD231PD	%XMM12,%XMM3,%XMM5

0x254a00 VMOVUPD	0x10(%R15,%RAX,8),%XMM12    [7]

0x254a07 VFMADD231PD	%XMM30,%XMM14,%XMM2

0x254a0d VFMADD231PD	%XMM15,%XMM21,%XMM8

0x254a13 VFMADD231PD	%XMM15,%XMM0,%XMM4

0x254a18 VFMADD231PD	%XMM20,%XMM14,%XMM9

0x254a1e VFMADD231PD	%XMM18,%XMM0,%XMM2

0x254a24 VFMADD231PD	%XMM14,%XMM1,%XMM5

0x254a29 VFMADD231PD	%XMM8,%XMM13,%XMM11

0x254a2e VFMADD231PD	%XMM16,%XMM21,%XMM9

0x254a34 VFMADD231PD	%XMM16,%XMM0,%XMM5

0x254a3a VMOVUPD	%XMM11,(%R15,%RAX,8)    [7]

0x254a40 VFMADD231PD	%XMM9,%XMM13,%XMM12

0x254a45 VMOVAPD	-0x150(%RBP),%XMM13    [4]

0x254a4d VMOVUPD	%XMM12,0x10(%R15,%RAX,8)    [7]

0x254a54 VMOVUPD	(%R10,%R9,1),%XMM11    [1]

0x254a5a VMOVUPD	0x10(%R10,%R9,1),%XMM12    [1]

0x254a61 VFMADD231PD	%XMM8,%XMM13,%XMM11

0x254a66 VFMADD231PD	%XMM9,%XMM13,%XMM12

0x254a6b VMOVAPD	-0x140(%RBP),%XMM13    [4]

0x254a73 VMOVUPD	%XMM11,(%R10,%R9,1)    [1]

0x254a79 VMOVUPD	%XMM12,0x10(%R10,%R9,1)    [1]

0x254a80 LEA	(%R9,%R10,1),%R9

0x254a84 VMOVUPD	(%R10,%R9,1),%XMM11    [1]

0x254a8a VMOVUPD	0x10(%R10,%R9,1),%XMM12    [1]

0x254a91 VFMADD231PD	%XMM23,%XMM10,%XMM11

0x254a97 VFMADD231PD	%XMM23,%XMM2,%XMM12

0x254a9d VMOVUPD	%XMM11,(%R10,%R9,1)    [1]

0x254aa3 VMOVUPD	%XMM12,0x10(%R10,%R9,1)    [1]

0x254aaa LEA	(%R9,%R10,1),%R9

0x254aae VMOVUPD	(%R10,%R9,1),%XMM11    [1]

0x254ab4 VMOVUPD	0x10(%R10,%R9,1),%XMM12    [1]

0x254abb VFMADD231PD	%XMM8,%XMM13,%XMM11

0x254ac0 VFMADD231PD	%XMM9,%XMM13,%XMM12

0x254ac5 VMOVUPD	%XMM11,(%R10,%R9,1)    [1]

0x254acb VMOVUPD	%XMM12,0x10(%R10,%R9,1)    [1]

0x254ad2 LEA	(%R9,%R10,1),%R9

0x254ad6 VMOVUPD	(%R10,%R9,1),%XMM11    [1]

0x254adc VMOVUPD	0x10(%R10,%R9,1),%XMM12    [1]

0x254ae3 VFMADD231PD	%XMM6,%XMM10,%XMM11

0x254ae8 VFMADD231PD	%XMM6,%XMM2,%XMM12

0x254aed VMOVUPD	%XMM11,(%R10,%R9,1)    [1]

0x254af3 VMOVUPD	%XMM12,0x10(%R10,%R9,1)    [1]

0x254afa LEA	(%R9,%R10,1),%R9

0x254afe VFMADD213PD	(%R10,%R9,1),%XMM7,%XMM4    [1]

0x254b04 VFMADD213PD	0x10(%R10,%R9,1),%XMM7,%XMM5    [1]

0x254b0b VMOVUPD	%XMM4,(%R10,%R9,1)    [1]

0x254b11 VMOVUPD	%XMM5,0x10(%R10,%R9,1)    [1]

0x254b18 VMOVUPD	(%R14,%RAX,8),%XMM4    [6]

0x254b1e VMOVUPD	0x10(%R14,%RAX,8),%XMM5    [6]

0x254b25 VFMADD231PD	%XMM23,%XMM8,%XMM4

0x254b2b VFMADD231PD	%XMM23,%XMM9,%XMM5

0x254b31 VMOVUPD	%XMM4,(%R14,%RAX,8)    [6]

0x254b37 VMOVUPD	%XMM5,0x10(%R14,%RAX,8)    [6]

0x254b3e VMOVUPD	-0x10(%RCX,%RAX,8),%XMM4    [3]

0x254b44 VMOVUPD	(%RCX,%RAX,8),%XMM5    [3]

0x254b49 VFMADD231PD	%XMM6,%XMM8,%XMM4

0x254b4e VFMADD231PD	%XMM6,%XMM9,%XMM5

0x254b53 VFMADD213PD	(%RBX,%RAX,8),%XMM7,%XMM8    [11]

0x254b59 VFMADD213PD	0x10(%RBX,%RAX,8),%XMM7,%XMM9    [11]

0x254b60 VMOVUPD	%XMM4,-0x10(%RCX,%RAX,8)    [3]

0x254b66 VMOVUPD	%XMM5,(%RCX,%RAX,8)    [3]

0x254b6b VFMADD213PD	-0x10(%R11,%RAX,8),%XMM7,%XMM10    [2]

0x254b72 VFMADD213PD	(%R11,%RAX,8),%XMM7,%XMM2    [2]

0x254b78 VMOVUPD	%XMM8,(%RBX,%RAX,8)    [11]

0x254b7d VMOVUPD	%XMM9,0x10(%RBX,%RAX,8)    [11]

0x254b83 VMOVUPD	%XMM10,-0x10(%R11,%RAX,8)    [2]

0x254b8a VMOVUPD	%XMM2,(%R11,%RAX,8)    [2]

0x254b90 ADD	$0x4,%RAX

0x254b94 CMP	%RAX,-0x40(%RBP)    [4]

0x254b98 JNE	254950

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 242 - 262

--------------------------------------------------------------------------------

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►81.80+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.30+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.99+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.61+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.74
Bottlenecks	P10, P11,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	23.00
CQA cycles if no scalar integer	23.00
CQA cycles if FP arith vectorized	12.88
CQA cycles if fully vectorized	5.75
Front-end cycles	12.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	13.25
P7 cycles	13.25
P8 cycles	13.25
P9 cycles	13.25
P10 cycles	23.00
P11 cycles	23.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	99.00
Nb loads	33.00
Nb stores	20.00
Nb stack references	5.00
FLOP/cycle	7.30
Nb FLOP add-sub	0.00
Nb FLOP mul	16.00
Nb FLOP fma	76.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.17
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	320.00
Stride 0	1.00
Stride 1	8.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.74
Bottlenecks	P10, P11,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	23.00
CQA cycles if no scalar integer	23.00
CQA cycles if FP arith vectorized	12.88
CQA cycles if fully vectorized	5.75
Front-end cycles	12.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	13.25
P7 cycles	13.25
P8 cycles	13.25
P9 cycles	13.25
P10 cycles	23.00
P11 cycles	23.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	99.00
Nb loads	33.00
Nb stores	20.00
Nb stack references	5.00
FLOP/cycle	7.30
Nb FLOP add-sub	0.00
Nb FLOP mul	16.00
Nb FLOP fma	76.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.17
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	320.00
Stride 0	1.00
Stride 1	8.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242-262.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 23.00 to 5.75 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 13.25 cycles (1.74x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 76 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

46 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

76: addition or subtraction (all inside FMA instructions)
92: multiply (76 inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	99
loop length	590
used x86 registers	13
used mmx registers	0
used xmm registers	29
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	13.25	13.25	13.25	13.25	23.00	23.00	0.00	0.00	10.00	10.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	13.25	13.25	13.25	13.25	23.00	23.00	0.00	0.00	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.38
Dispatch	23.00
Data deps.	1.00
Overall L1	23.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

8% of peak load performance is reached (22.26 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 254950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVUPD (%RSI,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RDX,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RDX,%RAX,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R8,%RAX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R8,%RAX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RDI,%RAX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RDI,%RAX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R9,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
LEA (%R15,%RAX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD %XMM22,%XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM25,%XMM4,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM31,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM24,%XMM11,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM24,%XMM12,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM19,%XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM11,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM30,%XMM13,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD (%R15,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM28,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM28,%XMM16,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMULPD %XMM22,%XMM5,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM25,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM31,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM20,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM13,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVAPD -0xd0(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM17,%XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM19,%XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM12,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD 0x10(%R15,%RAX,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM30,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM15,%XMM21,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM15,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM20,%XMM14,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM18,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM14,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM16,%XMM21,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM16,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVAPD -0x150(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVAPD -0x140(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%R10,%R9,1),%XMM7,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%R10,%R9,1),%XMM7,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM4,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM5,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD (%R14,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R14,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM4,(%R14,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM5,0x10(%R14,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD -0x10(%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RCX,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD (%RBX,%RAX,8),%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%RBX,%RAX,8),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM4,-0x10(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM5,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VFMADD213PD -0x10(%R11,%RAX,8),%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD (%R11,%RAX,8),%XMM7,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM9,0x10(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM10,-0x10(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM2,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 254950 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xc20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 23.00 to 5.75 cycles (4.00x speedup).

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 76 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

46 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 168 FP arithmetical operations:

76: addition or subtraction (all inside FMA instructions)
92: multiply (76 inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	99
loop length	590
used x86 registers	13
used mmx registers	0
used xmm registers	29
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	13.25	13.25	13.25	13.25	23.00	23.00	0.00	0.00	10.00	10.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	13.25	13.25	13.25	13.25	23.00	23.00	0.00	0.00	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.38
Dispatch	23.00
Data deps.	1.00
Overall L1	23.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

8% of peak load performance is reached (22.26 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 254950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVUPD (%RSI,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RDX,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RDX,%RAX,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R8,%RAX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R8,%RAX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RDI,%RAX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RDI,%RAX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R9,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
LEA (%R15,%RAX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD %XMM22,%XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM25,%XMM4,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM31,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM24,%XMM11,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM24,%XMM12,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM19,%XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM11,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM30,%XMM13,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD (%R15,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM28,%XMM15,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM28,%XMM16,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMULPD %XMM22,%XMM5,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM25,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMULPD %XMM31,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM20,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM13,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVAPD -0xd0(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM17,%XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM19,%XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM12,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD 0x10(%R15,%RAX,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM30,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM15,%XMM21,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM15,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM20,%XMM14,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM18,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM14,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM16,%XMM21,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM16,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVAPD -0x150(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVAPD -0x140(%RBP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R10,%R9,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R10,%R9,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM2,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM11,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM12,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
LEA (%R9,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%R10,%R9,1),%XMM7,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%R10,%R9,1),%XMM7,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM4,(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM5,0x10(%R10,%R9,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD (%R14,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R14,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM23,%XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM4,(%R14,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM5,0x10(%R14,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD -0x10(%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RCX,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM6,%XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD (%RBX,%RAX,8),%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%RBX,%RAX,8),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM4,-0x10(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM5,(%RCX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VFMADD213PD -0x10(%R11,%RAX,8),%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VFMADD213PD (%R11,%RAX,8),%XMM7,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM9,0x10(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM10,-0x10(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM2,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 254950 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xc20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

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FMA

Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

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Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code