OV - exec - Loop 269

	Loop Id: 269	Module: exec	Source: TwoBodyJastrowRef.h:324-331	Coverage: 0.23%

0x239550 VMOVUPD	(%RCX,%R12,8),%XMM9    [3]

0x239556 VMOVUPD	0x10(%RCX,%R12,8),%XMM10    [3]

0x23955d VMOVUPD	0x20(%RCX,%R12,8),%XMM11    [3]

0x239564 VMOVUPD	0x30(%RCX,%R12,8),%XMM12    [3]

0x23956b VMOVUPD	(%RSI,%R12,8),%XMM5    [4]

0x239571 VMOVUPD	0x10(%RSI,%R12,8),%XMM6    [4]

0x239578 VMOVUPD	0x20(%RSI,%R12,8),%XMM7    [4]

0x23957f VMOVUPD	0x30(%RSI,%R12,8),%XMM8    [4]

0x239586 VMOVUPD	(%R9,%R12,8),%XMM13    [2]

0x23958c VMOVUPD	0x10(%R9,%R12,8),%XMM14    [2]

0x239593 VMOVUPD	0x20(%R9,%R12,8),%XMM15    [2]

0x23959a VMOVUPD	0x30(%R9,%R12,8),%XMM16    [2]

0x2395a2 VFMADD213PD	(%R8,%R12,8),%XMM1,%XMM9    [1]

0x2395a8 VFMADD213PD	0x10(%R8,%R12,8),%XMM1,%XMM10    [1]

0x2395af VFMADD213PD	0x20(%R8,%R12,8),%XMM1,%XMM11    [1]

0x2395b6 VFMADD213PD	0x30(%R8,%R12,8),%XMM1,%XMM12    [1]

0x2395bd VSUBPD	(%RDI,%R12,8),%XMM5,%XMM5    [6]

0x2395c3 VSUBPD	0x10(%RDI,%R12,8),%XMM6,%XMM6    [6]

0x2395ca VSUBPD	0x20(%RDI,%R12,8),%XMM7,%XMM7    [6]

0x2395d1 VSUBPD	0x30(%RDI,%R12,8),%XMM8,%XMM8    [6]

0x2395d8 VADDPD	(%R10,%R12,8),%XMM5,%XMM5    [5]

0x2395de VADDPD	0x10(%R10,%R12,8),%XMM6,%XMM6    [5]

0x2395e5 VADDPD	0x20(%R10,%R12,8),%XMM7,%XMM7    [5]

0x2395ec VADDPD	0x30(%R10,%R12,8),%XMM8,%XMM8    [5]

0x2395f3 VSUBPD	%XMM9,%XMM13,%XMM13

0x2395f8 VSUBPD	%XMM10,%XMM14,%XMM14

0x2395fd VSUBPD	%XMM11,%XMM15,%XMM15

0x239602 VSUBPD	%XMM12,%XMM16,%XMM16

0x239608 VFMADD231PD	(%RDX,%R12,8),%XMM1,%XMM13    [8]

0x23960e VFMADD231PD	0x10(%RDX,%R12,8),%XMM1,%XMM14    [8]

0x239615 VFMADD231PD	0x20(%RDX,%R12,8),%XMM1,%XMM15    [8]

0x23961c VFMADD231PD	0x30(%RDX,%R12,8),%XMM1,%XMM16    [8]

0x239624 VSUBPD	%XMM9,%XMM0,%XMM0

0x239629 VSUBPD	%XMM10,%XMM2,%XMM2

0x23962e VSUBPD	%XMM11,%XMM3,%XMM3

0x239633 VSUBPD	%XMM12,%XMM4,%XMM4

0x239638 VMOVUPD	%XMM5,(%R10,%R12,8)    [5]

0x23963e VMOVUPD	%XMM6,0x10(%R10,%R12,8)    [5]

0x239645 VMOVUPD	%XMM7,0x20(%R10,%R12,8)    [5]

0x23964c VMOVUPD	%XMM8,0x30(%R10,%R12,8)    [5]

0x239653 VADDPD	(%R14,%R12,8),%XMM13,%XMM5    [7]

0x239659 VADDPD	0x10(%R14,%R12,8),%XMM14,%XMM6    [7]

0x239660 VADDPD	0x20(%R14,%R12,8),%XMM15,%XMM7    [7]

0x239667 VADDPD	0x30(%R14,%R12,8),%XMM16,%XMM8    [7]

0x23966f VMOVUPD	%XMM5,(%R14,%R12,8)    [7]

0x239675 VMOVUPD	%XMM6,0x10(%R14,%R12,8)    [7]

0x23967c VMOVUPD	%XMM7,0x20(%R14,%R12,8)    [7]

0x239683 VMOVUPD	%XMM8,0x30(%R14,%R12,8)    [7]

0x23968a ADD	$0x8,%R12

0x23968e CMP	%R12,%RAX

0x239691 JNE	239550

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 324 - 331

--------------------------------------------------------------------------------

324:   for (int jat = 0; jat < N; jat++)

325:   {

326:     const valT du   = cur_u[jat] - old_u[jat];

327:     const valT newl = cur_d2u[jat] + lapfac * cur_du[jat];

328:     const valT dl   = old_d2u[jat] + lapfac * old_du[jat] - newl;

329:     Uat[jat] += du;

330:     d2Uat[jat] += dl;

331:     cur_d2Uat -= newl;

Coverage (%)	Name	Source Location	Module
►96.51+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.89+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7, P8, P9, P12, P13,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:324-331
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	2.50
Front-end cycles	6.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	10.00
P13 cycles	10.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	50.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	40.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P6, P7, P8, P9, P12, P13,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:324-331
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	2.50
Front-end cycles	6.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	10.00
P13 cycles	10.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	50.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	7.20
Nb FLOP add-sub	40.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:324-331
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:324-331.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 10.00 to 2.50 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 6.25 cycles (1.60x speedup).

Workaround

Reduce the number of FP add instructions
Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 16 FMA (fused multiply-add) operations.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

56: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	50
loop length	327
used x86 registers	10
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.25
Dispatch	10.00
Data deps.	2.00
Overall L1	10.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

20% of peak load performance is reached (51.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (12.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 239550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%RCX,%R12,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RCX,%R12,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x20(%RCX,%R12,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x30(%RCX,%R12,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RSI,%R12,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RSI,%R12,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x20(%RSI,%R12,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x30(%RSI,%R12,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R9,%R12,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R9,%R12,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x20(%R9,%R12,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x30(%R9,%R12,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VFMADD213PD (%R8,%R12,8),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%R8,%R12,8),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x20(%R8,%R12,8),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x30(%R8,%R12,8),%XMM1,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSUBPD (%RDI,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD 0x10(%RDI,%R12,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD 0x20(%RDI,%R12,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD 0x30(%RDI,%R12,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD (%R10,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x10(%R10,%R12,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x20(%R10,%R12,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x30(%R10,%R12,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM9,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM10,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM11,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM12,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VFMADD231PD (%RDX,%R12,8),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x10(%RDX,%R12,8),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x20(%RDX,%R12,8),%XMM1,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x30(%RDX,%R12,8),%XMM1,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSUBPD %XMM9,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM10,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM11,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM12,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM5,(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM6,0x10(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM7,0x20(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM8,0x30(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VADDPD (%R14,%R12,8),%XMM13,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x10(%R14,%R12,8),%XMM14,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x20(%R14,%R12,8),%XMM15,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x30(%R14,%R12,8),%XMM16,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM5,(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM6,0x10(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM7,0x20(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM8,0x30(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x8,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 239550 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x4d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:324-331
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 10.00 to 2.50 cycles (4.00x speedup).

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 6.25 cycles (1.60x speedup).

Workaround

Reduce the number of FP add instructions
Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 16 FMA (fused multiply-add) operations.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

56: addition or subtraction (16 inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	50
loop length	327
used x86 registers	10
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.25
Dispatch	10.00
Data deps.	2.00
Overall L1	10.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

20% of peak load performance is reached (51.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (12.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 239550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%RCX,%R12,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RCX,%R12,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x20(%RCX,%R12,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x30(%RCX,%R12,8),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RSI,%R12,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%RSI,%R12,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x20(%RSI,%R12,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x30(%RSI,%R12,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R9,%R12,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x10(%R9,%R12,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x20(%R9,%R12,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD 0x30(%R9,%R12,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VFMADD213PD (%R8,%R12,8),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%R8,%R12,8),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x20(%R8,%R12,8),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD213PD 0x30(%R8,%R12,8),%XMM1,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSUBPD (%RDI,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD 0x10(%RDI,%R12,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD 0x20(%RDI,%R12,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD 0x30(%RDI,%R12,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD (%R10,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x10(%R10,%R12,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x20(%R10,%R12,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x30(%R10,%R12,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM9,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM10,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM11,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM12,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VFMADD231PD (%RDX,%R12,8),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x10(%RDX,%R12,8),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x20(%RDX,%R12,8),%XMM1,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x30(%RDX,%R12,8),%XMM1,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSUBPD %XMM9,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM10,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM11,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSUBPD %XMM12,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM5,(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM6,0x10(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM7,0x20(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM8,0x30(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VADDPD (%R14,%R12,8),%XMM13,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x10(%R14,%R12,8),%XMM14,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x20(%R14,%R12,8),%XMM15,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD 0x30(%R14,%R12,8),%XMM16,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM5,(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM6,0x10(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM7,0x20(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD %XMM8,0x30(%R14,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x8,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 239550 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x4d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code