OV - exec - Loop 1118

	Loop Id: 1118	Module: exec	Source: ParticleBConds3DSoa.h:234-255	Coverage: 1.08%

0x27b8d0 MOVSXD	%R13D,%R13

0x27b8d3 VMOVUPD	(%RDX,%R13,8),%XMM7    [8]

0x27b8d9 VMOVUPD	(%R10,%R13,8),%XMM8    [3]

0x27b8df VMOVUPD	(%RSI,%R13,8),%XMM9    [5]

0x27b8e5 VSUBPD	%XMM2,%XMM7,%XMM7

0x27b8e9 VMULPD	0x48(%RDI){1to2},%XMM7,%XMM10    [2]

0x27b8f0 VSUBPD	%XMM3,%XMM8,%XMM8

0x27b8f4 VMULPD	0x60(%RDI){1to2},%XMM7,%XMM11    [2]

0x27b8fb VMULPD	0x78(%RDI){1to2},%XMM7,%XMM7    [2]

0x27b902 VSUBPD	%XMM4,%XMM9,%XMM9

0x27b906 VFMADD231PD	0x50(%RDI){1to2},%XMM8,%XMM10    [2]

0x27b90d VFMADD231PD	0x80(%RDI){1to2},%XMM8,%XMM7    [2]

0x27b914 VFMADD231PD	0x68(%RDI){1to2},%XMM8,%XMM11    [2]

0x27b91b VMOVDQA	%XMM6,%XMM8

0x27b91f VFMADD231PD	0x58(%RDI){1to2},%XMM9,%XMM10    [2]

0x27b926 VFMADD231PD	0x88(%RDI){1to2},%XMM9,%XMM7    [2]

0x27b92d VFMADD231PD	0x70(%RDI){1to2},%XMM9,%XMM11    [2]

0x27b934 VMOVDQA	%XMM6,%XMM9

0x27b938 VPTERNLOGQ	$-0x8,%XMM5,%XMM10,%XMM8

0x27b93f VPTERNLOGQ	$-0x8,%XMM5,%XMM11,%XMM9

0x27b946 VADDPD	%XMM8,%XMM10,%XMM8

0x27b94b VADDPD	%XMM9,%XMM11,%XMM9

0x27b950 VROUNDPD	$0xb,%XMM8,%XMM8

0x27b956 VROUNDPD	$0xb,%XMM9,%XMM9

0x27b95c VSUBPD	%XMM8,%XMM10,%XMM8

0x27b961 VMOVDQA	%XMM6,%XMM10

0x27b965 VPTERNLOGQ	$-0x8,%XMM5,%XMM7,%XMM10

0x27b96c VSUBPD	%XMM9,%XMM11,%XMM9

0x27b971 VADDPD	%XMM7,%XMM10,%XMM10

0x27b975 VROUNDPD	$0xb,%XMM10,%XMM10

0x27b97b VSUBPD	%XMM10,%XMM7,%XMM7

0x27b980 VMULPD	(%RDI){1to2},%XMM8,%XMM10    [2]

0x27b986 VFMADD231PD	0x8(%RDI){1to2},%XMM9,%XMM10    [2]

0x27b98d VFMADD231PD	0x10(%RDI){1to2},%XMM7,%XMM10    [2]

0x27b994 VMOVUPD	%XMM10,(%R8,%R13,8)    [1]

0x27b99a VMULPD	0x18(%RDI){1to2},%XMM8,%XMM10    [2]

0x27b9a1 VFMADD231PD	0x20(%RDI){1to2},%XMM9,%XMM10    [2]

0x27b9a8 VFMADD231PD	0x28(%RDI){1to2},%XMM7,%XMM10    [2]

0x27b9af VMOVUPD	%XMM10,(%RBX,%R13,8)    [6]

0x27b9b5 VMULPD	0x30(%RDI){1to2},%XMM8,%XMM8    [2]

0x27b9bc VFMADD231PD	0x38(%RDI){1to2},%XMM9,%XMM8    [2]

0x27b9c3 VFMADD231PD	0x40(%RDI){1to2},%XMM7,%XMM8    [2]

0x27b9ca VMOVUPD	%XMM8,(%R11,%R13,8)    [4]

0x27b9d0 VMOVUPD	(%R8,%R13,8),%XMM7    [1]

0x27b9d6 VMOVUPD	(%RBX,%R13,8),%XMM9    [6]

0x27b9dc VMULPD	%XMM7,%XMM7,%XMM7

0x27b9e0 VFMADD231PD	%XMM8,%XMM8,%XMM7

0x27b9e5 VFMADD231PD	%XMM9,%XMM9,%XMM7

0x27b9ea VSQRTPD	%XMM7,%XMM7

0x27b9ee VMOVUPD	%XMM7,(%RCX,%R13,8)    [7]

0x27b9f4 ADD	$0x2,%R13D

0x27b9f8 ADD	$-0x2,%R12D

0x27b9fc JNE	27b8d0

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 234 - 255

--------------------------------------------------------------------------------

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:234-255
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	2.75
Front-end cycles	6.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	52.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	8.18
Nb FLOP add-sub	18.00
Nb FLOP mul	14.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.18
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source	ParticleBConds3DSoa.h:234-255
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	2.75
Front-end cycles	6.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	52.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	8.18
Nb FLOP add-sub	18.00
Nb FLOP mul	14.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.18
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:234-255
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-255.

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.75 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

46: addition or subtraction (28 inside FMA instructions)
42: multiply (28 inside FMA instructions)
2: square root

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	52
loop length	306
used x86 registers	10
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.50
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

7% of peak load performance is reached (20.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 27b8d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD %R13D,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RDX,%R13,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R10,%R13,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RSI,%R13,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM2,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD 0x48(%RDI){1to2},%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM3,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD 0x60(%RDI){1to2},%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMULPD 0x78(%RDI){1to2},%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM4,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VFMADD231PD 0x50(%RDI){1to2},%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x80(%RDI){1to2},%XMM8,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x68(%RDI){1to2},%XMM8,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVDQA %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231PD 0x58(%RDI){1to2},%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x88(%RDI){1to2},%XMM9,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x70(%RDI){1to2},%XMM9,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVDQA %XMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM5,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM5,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPD %XMM8,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VROUNDPD $0xb,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VROUNDPD $0xb,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM8,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVDQA %XMM6,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM5,%XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBPD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM7,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VROUNDPD $0xb,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM10,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD (%RDI){1to2},%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0x8(%RDI){1to2},%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x10(%RDI){1to2},%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM10,(%R8,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULPD 0x18(%RDI){1to2},%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0x20(%RDI){1to2},%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x28(%RDI){1to2},%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM10,(%RBX,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULPD 0x30(%RDI){1to2},%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0x38(%RDI){1to2},%XMM9,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x40(%RDI){1to2},%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%R11,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD (%R8,%R13,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RBX,%R13,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSQRTPD %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (25.0%)
VMOVUPD %XMM7,(%RCX,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x2,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x2,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 27b8d0 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines	ParticleBConds3DSoa.h:234-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.75 cycles (4.00x speedup).

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

46: addition or subtraction (28 inside FMA instructions)
42: multiply (28 inside FMA instructions)
2: square root

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	52
loop length	306
used x86 registers	10
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.50
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	2.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

7% of peak load performance is reached (20.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 27b8d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVSXD %R13D,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RDX,%R13,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R10,%R13,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RSI,%R13,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM2,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD 0x48(%RDI){1to2},%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM3,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD 0x60(%RDI){1to2},%XMM7,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMULPD 0x78(%RDI){1to2},%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM4,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VFMADD231PD 0x50(%RDI){1to2},%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x80(%RDI){1to2},%XMM8,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x68(%RDI){1to2},%XMM8,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVDQA %XMM6,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231PD 0x58(%RDI){1to2},%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x88(%RDI){1to2},%XMM9,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x70(%RDI){1to2},%XMM9,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVDQA %XMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM5,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM5,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPD %XMM8,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VROUNDPD $0xb,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VROUNDPD $0xb,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM8,%XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVDQA %XMM6,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM5,%XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBPD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM7,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VROUNDPD $0xb,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VSUBPD %XMM10,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD (%RDI){1to2},%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0x8(%RDI){1to2},%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x10(%RDI){1to2},%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM10,(%R8,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULPD 0x18(%RDI){1to2},%XMM8,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0x20(%RDI){1to2},%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x28(%RDI){1to2},%XMM7,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM10,(%RBX,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULPD 0x30(%RDI){1to2},%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0x38(%RDI){1to2},%XMM9,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x40(%RDI){1to2},%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%R11,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVUPD (%R8,%R13,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%RBX,%R13,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD %XMM8,%XMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD %XMM9,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSQRTPD %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (25.0%)
VMOVUPD %XMM7,(%RCX,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x2,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x2,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 27b8d0 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xa0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code