OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:221-257 [...]	Coverage (incl. loops): 1.08% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 221 - 257

--------------------------------------------------------------------------------

221:   {

[...]

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x27b830 PUSH	%RBP

0x27b831 MOV	%RSP,%RBP

0x27b834 PUSH	%R15

0x27b836 PUSH	%R14

0x27b838 PUSH	%R13

0x27b83a PUSH	%R12

0x27b83c PUSH	%RBX

0x27b83d MOV	0x10(%RBP),%EAX

0x27b840 MOV	%EAX,%R15D

0x27b843 SUB	%R9D,%R15D

0x27b846 JLE	27bb62

0x27b84c VMOVUPD	(%RSI),%XMM0

0x27b850 VMOVSD	0x10(%RSI),%XMM1

0x27b855 MOV	0x8(%RDX),%RSI

0x27b859 MOV	0x18(%RDX),%RDX

0x27b85d MOV	0x8(%R8),%R11

0x27b861 MOV	0x18(%R8),%R8

0x27b865 XOR	%R14D,%R14D

0x27b868 LEA	(%RDX,%RSI,8),%R10

0x27b86c SAL	$0x4,%RSI

0x27b870 LEA	(%R8,%R11,8),%RBX

0x27b874 SAL	$0x4,%R11

0x27b878 ADD	%RDX,%RSI

0x27b87b ADD	%R8,%R11

0x27b87e CMP	$0x2,%R15D

0x27b882 JB	27ba0b

0x27b888 LEA	-0x1(%RAX),%R12D

0x27b88c CMP	%R9D,%R12D

0x27b88f JL	27ba0b

0x27b895 VPBROADCASTQ	-0x7771e(%RIP),%XMM5

0x27b89e VPBROADCASTQ	-0x777af(%RIP),%XMM6

0x27b8a7 VMOVDDUP	%XMM0,%XMM2

0x27b8ab VMOVDDUP	%XMM1,%XMM4

0x27b8af MOV	%R15D,%R14D

0x27b8b2 AND	$-0x2,%R14D

0x27b8b6 VSHUFPD	$0x3,%XMM0,%XMM0,%XMM3

0x27b8bb MOV	%R9D,%R13D

0x27b8be MOV	%R14D,%R12D

0x27b8c1 NOPW	%CS:(%RAX,%RAX,1)

(1118) 0x27b8d0 MOVSXD	%R13D,%R13

(1118) 0x27b8d3 VMOVUPD	(%RDX,%R13,8),%XMM7

(1118) 0x27b8d9 VMOVUPD	(%R10,%R13,8),%XMM8

(1118) 0x27b8df VMOVUPD	(%RSI,%R13,8),%XMM9

(1118) 0x27b8e5 VSUBPD	%XMM2,%XMM7,%XMM7

(1118) 0x27b8e9 VMULPD	0x48(%RDI){1to2},%XMM7,%XMM10

(1118) 0x27b8f0 VSUBPD	%XMM3,%XMM8,%XMM8

(1118) 0x27b8f4 VMULPD	0x60(%RDI){1to2},%XMM7,%XMM11

(1118) 0x27b8fb VMULPD	0x78(%RDI){1to2},%XMM7,%XMM7

(1118) 0x27b902 VSUBPD	%XMM4,%XMM9,%XMM9

(1118) 0x27b906 VFMADD231PD	0x50(%RDI){1to2},%XMM8,%XMM10

(1118) 0x27b90d VFMADD231PD	0x80(%RDI){1to2},%XMM8,%XMM7

(1118) 0x27b914 VFMADD231PD	0x68(%RDI){1to2},%XMM8,%XMM11

(1118) 0x27b91b VMOVDQA	%XMM6,%XMM8

(1118) 0x27b91f VFMADD231PD	0x58(%RDI){1to2},%XMM9,%XMM10

(1118) 0x27b926 VFMADD231PD	0x88(%RDI){1to2},%XMM9,%XMM7

(1118) 0x27b92d VFMADD231PD	0x70(%RDI){1to2},%XMM9,%XMM11

(1118) 0x27b934 VMOVDQA	%XMM6,%XMM9

(1118) 0x27b938 VPTERNLOGQ	$-0x8,%XMM5,%XMM10,%XMM8

(1118) 0x27b93f VPTERNLOGQ	$-0x8,%XMM5,%XMM11,%XMM9

(1118) 0x27b946 VADDPD	%XMM8,%XMM10,%XMM8

(1118) 0x27b94b VADDPD	%XMM9,%XMM11,%XMM9

(1118) 0x27b950 VROUNDPD	$0xb,%XMM8,%XMM8

(1118) 0x27b956 VROUNDPD	$0xb,%XMM9,%XMM9

(1118) 0x27b95c VSUBPD	%XMM8,%XMM10,%XMM8

(1118) 0x27b961 VMOVDQA	%XMM6,%XMM10

(1118) 0x27b965 VPTERNLOGQ	$-0x8,%XMM5,%XMM7,%XMM10

(1118) 0x27b96c VSUBPD	%XMM9,%XMM11,%XMM9

(1118) 0x27b971 VADDPD	%XMM7,%XMM10,%XMM10

(1118) 0x27b975 VROUNDPD	$0xb,%XMM10,%XMM10

(1118) 0x27b97b VSUBPD	%XMM10,%XMM7,%XMM7

(1118) 0x27b980 VMULPD	(%RDI){1to2},%XMM8,%XMM10

(1118) 0x27b986 VFMADD231PD	0x8(%RDI){1to2},%XMM9,%XMM10

(1118) 0x27b98d VFMADD231PD	0x10(%RDI){1to2},%XMM7,%XMM10

(1118) 0x27b994 VMOVUPD	%XMM10,(%R8,%R13,8)

(1118) 0x27b99a VMULPD	0x18(%RDI){1to2},%XMM8,%XMM10

(1118) 0x27b9a1 VFMADD231PD	0x20(%RDI){1to2},%XMM9,%XMM10

(1118) 0x27b9a8 VFMADD231PD	0x28(%RDI){1to2},%XMM7,%XMM10

(1118) 0x27b9af VMOVUPD	%XMM10,(%RBX,%R13,8)

(1118) 0x27b9b5 VMULPD	0x30(%RDI){1to2},%XMM8,%XMM8

(1118) 0x27b9bc VFMADD231PD	0x38(%RDI){1to2},%XMM9,%XMM8

(1118) 0x27b9c3 VFMADD231PD	0x40(%RDI){1to2},%XMM7,%XMM8

(1118) 0x27b9ca VMOVUPD	%XMM8,(%R11,%R13,8)

(1118) 0x27b9d0 VMOVUPD	(%R8,%R13,8),%XMM7

(1118) 0x27b9d6 VMOVUPD	(%RBX,%R13,8),%XMM9

(1118) 0x27b9dc VMULPD	%XMM7,%XMM7,%XMM7

(1118) 0x27b9e0 VFMADD231PD	%XMM8,%XMM8,%XMM7

(1118) 0x27b9e5 VFMADD231PD	%XMM9,%XMM9,%XMM7

(1118) 0x27b9ea VSQRTPD	%XMM7,%XMM7

(1118) 0x27b9ee VMOVUPD	%XMM7,(%RCX,%R13,8)

(1118) 0x27b9f4 ADD	$0x2,%R13D

(1118) 0x27b9f8 ADD	$-0x2,%R12D

(1118) 0x27b9fc JNE	27b8d0

0x27ba02 CMP	%R14D,%R15D

0x27ba05 JE	27bb62

0x27ba0b VMOVQ	-0x7791b(%RIP),%XMM2

0x27ba13 VPBROADCASTQ	-0x778bc(%RIP),%XMM3

0x27ba1c VPBROADCASTQ	-0x7792d(%RIP),%XMM4

0x27ba25 VPBROADCASTQ	-0x778ae(%RIP),%XMM5

0x27ba2e ADD	%R9D,%R14D

0x27ba31 NOPW	%CS:(%RAX,%RAX,1)

(1117) 0x27ba40 MOVSXD	%R14D,%R14

(1117) 0x27ba43 VMOVUPD	0x68(%RDI),%XMM8

(1117) 0x27ba48 VMOVUPD	0x60(%RDI),%XMM7

(1117) 0x27ba4d VMOVUPD	0x70(%RDI),%XMM9

(1117) 0x27ba52 VMOVSD	(%RSI,%R14,8),%XMM6

(1117) 0x27ba58 VMOVSD	(%RDX,%R14,8),%XMM10

(1117) 0x27ba5e VMOVHPD	0x78(%RDI),%XMM8,%XMM8

(1117) 0x27ba63 VMOVHPD	0x80(%RDI),%XMM7,%XMM7

(1117) 0x27ba6b VMOVHPD	(%R10,%R14,8),%XMM10,%XMM10

(1117) 0x27ba71 VSUBSD	%XMM1,%XMM6,%XMM6

(1117) 0x27ba75 VSUBPD	%XMM0,%XMM10,%XMM10

(1117) 0x27ba79 VMOVDDUP	%XMM6,%XMM6

(1117) 0x27ba7d VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

(1117) 0x27ba83 VUNPCKHPD	%XMM6,%XMM10,%XMM12

(1117) 0x27ba87 VMULPD	0x50(%RDI),%XMM12,%XMM12

(1117) 0x27ba8c VMULPD	%XMM11,%XMM8,%XMM8

(1117) 0x27ba91 VFMADD213PD	%XMM8,%XMM10,%XMM7

(1117) 0x27ba96 VMOVHPD	0x88(%RDI),%XMM9,%XMM8

(1117) 0x27ba9e VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

(1117) 0x27baa4 VFMADD231SD	0x48(%RDI),%XMM10,%XMM12

(1117) 0x27baaa VFMADD213PD	%XMM7,%XMM6,%XMM8

(1117) 0x27baaf VMOVDQA	%XMM4,%XMM7

(1117) 0x27bab3 VPTERNLOGQ	$-0x8,%XMM5,%XMM8,%XMM7

(1117) 0x27baba VADDPD	%XMM7,%XMM8,%XMM7

(1117) 0x27babe VROUNDPD	$0xb,%XMM7,%XMM7

(1117) 0x27bac4 VADDSD	%XMM13,%XMM12,%XMM12

(1117) 0x27bac9 VSUBPD	%XMM7,%XMM8,%XMM7

(1117) 0x27bacd VMOVAPD	%XMM12,%XMM6

(1117) 0x27bad1 VPTERNLOGQ	$-0x28,%XMM3,%XMM2,%XMM6

(1117) 0x27bad8 VADDSD	%XMM6,%XMM12,%XMM6

(1117) 0x27badc VSHUFPD	$0x1,%XMM7,%XMM7,%XMM9

(1117) 0x27bae1 VROUNDSD	$0xb,%XMM6,%XMM6,%XMM6

(1117) 0x27bae7 VSUBSD	%XMM6,%XMM12,%XMM6

(1117) 0x27baeb VMULSD	(%RDI),%XMM6,%XMM8

(1117) 0x27baef VFMADD231SD	0x8(%RDI),%XMM7,%XMM8

(1117) 0x27baf5 VFMADD231SD	0x10(%RDI),%XMM9,%XMM8

(1117) 0x27bafb VMOVSD	%XMM8,(%R8,%R14,8)

(1117) 0x27bb01 VMULSD	0x18(%RDI),%XMM6,%XMM8

(1117) 0x27bb06 VFMADD231SD	0x20(%RDI),%XMM7,%XMM8

(1117) 0x27bb0c VFMADD231SD	0x28(%RDI),%XMM9,%XMM8

(1117) 0x27bb12 VMOVSD	%XMM8,(%RBX,%R14,8)

(1117) 0x27bb18 VMULPD	0x38(%RDI),%XMM7,%XMM7

(1117) 0x27bb1d VSHUFPD	$0x1,%XMM7,%XMM7,%XMM8

(1117) 0x27bb22 VFMADD231SD	0x30(%RDI),%XMM6,%XMM7

(1117) 0x27bb28 VADDSD	%XMM7,%XMM8,%XMM6

(1117) 0x27bb2c VMOVSD	%XMM6,(%R11,%R14,8)

(1117) 0x27bb32 VMOVSD	(%R8,%R14,8),%XMM7

(1117) 0x27bb38 VMOVSD	(%RBX,%R14,8),%XMM8

(1117) 0x27bb3e VMULSD	%XMM7,%XMM7,%XMM7

(1117) 0x27bb42 VFMADD231SD	%XMM6,%XMM6,%XMM7

(1117) 0x27bb47 VFMADD231SD	%XMM8,%XMM8,%XMM7

(1117) 0x27bb4c VSQRTSD	%XMM7,%XMM7,%XMM6

(1117) 0x27bb50 VMOVSD	%XMM6,(%RCX,%R14,8)

(1117) 0x27bb56 INC	%R14D

(1117) 0x27bb59 CMP	%R14D,%EAX

(1117) 0x27bb5c JNE	27ba40

0x27bb62 POP	%RBX

0x27bb63 POP	%R12

0x27bb65 POP	%R13

0x27bb67 POP	%R14

0x27bb69 POP	%R15

0x27bb6b POP	%RBP

0x27bb6c RET

0x27bb6d INT	$0x3

0x27bb6e INT	$0x3

0x27bb6f INT	$0x3

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_4

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221,234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 2.38 cycles (2.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.50 to 0.50 cycles (13.03x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes.

General properties

nb instructions	57
nb uops	52
loop length	236
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	3.25	3.25	3.25	3.25	2.00	2.00	2.00	2.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	3.25	3.25	3.25	3.25	2.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	3.25
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	40%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	17%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	11%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

6% of peak load performance is reached (16.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.50 to 3.25 cycles (2.00x speedup).

ASM code

In the binary file, the address of the function is: 27b830

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %R9D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 27bb62 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x332>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RDX,%RSI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 27ba0b <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x1db>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 27ba0b <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x1db>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ -0x7771e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x777af(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSHUFPD $0x3,%XMM0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %R9D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 27bb62 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x332>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ -0x7791b(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x778bc(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x7792d(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x778ae(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD %R9D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_4

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221,234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 2.38 cycles (2.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes.

General properties

nb instructions	57
nb uops	52
loop length	236
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	3.25	3.25	3.25	3.25	2.00	2.00	2.00	2.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	3.25	3.25	3.25	3.25	2.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	3.25
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	40%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	17%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	11%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

6% of peak load performance is reached (16.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 27b830

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %R9D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 27bb62 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x332>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RDX,%RSI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 27ba0b <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x1db>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 27ba0b <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x1db>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ -0x7771e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x777af(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP %XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSHUFPD $0x3,%XMM0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %R9D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 27bb62 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x332>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ -0x7791b(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x778bc(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x7792d(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x778ae(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD %R9D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	1.08	1.79
○Loop 1118 - ParticleBConds3DSoa.h:234-255 - exec	1.08	1.78
○Loop 1117 - ParticleBConds3DSoa.h:234-255 - exec	0.00	0.00

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Vectorization

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Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code