OV - exec - Loop 624

	Loop Id: 624	Module: exec	Source: :0-0	Coverage: 0.25%

0x45e181 VMOVSD	(%RBX,%RDX,1),%XMM6    [7]

0x45e186 VMOVAPD	%XMM6,%XMM7

0x45e18a VMOVSD	(%R8,%RDX,1),%XMM14    [1]

0x45e190 VFMADD213SD	(%RDI,%RDX,1),%XMM1,%XMM14    [3]

0x45e196 VFMSUB132SD	%XMM1,%XMM14,%XMM7

0x45e19b VMOVSD	(%R14,%RDX,1),%XMM13    [5]

0x45e1a1 VMOVSD	(%RAX,%RDX,1),%XMM15    [6]

0x45e1a6 VADDSD	(%RCX,%RDX,1),%XMM13,%XMM4    [8]

0x45e1ab VSUBSD	(%R13,%RDX,1),%XMM4,%XMM3    [4]

0x45e1b2 VMOVSD	%XMM3,(%RCX,%RDX,1)    [8]

0x45e1b7 VADDSD	(%R9,%RDX,1),%XMM15,%XMM2    [2]

0x45e1bd VSUBSD	%XMM14,%XMM0,%XMM9

0x45e1c2 VADDSD	%XMM7,%XMM2,%XMM8

0x45e1c6 VMOVSD	%XMM8,(%R9,%RDX,1)    [2]

0x45e1cc VMOVSD	0x8(%R8,%RDX,1),%XMM11    [1]

0x45e1d3 VMOVSD	0x8(%RBX,%RDX,1),%XMM12    [7]

0x45e1d9 VFMADD213SD	0x8(%RDI,%RDX,1),%XMM1,%XMM11    [3]

0x45e1e0 VFMSUB132SD	%XMM1,%XMM11,%XMM12

0x45e1e5 VMOVSD	0x8(%R14,%RDX,1),%XMM10    [5]

0x45e1ec VMOVSD	0x8(%RAX,%RDX,1),%XMM5    [6]

0x45e1f2 VADDSD	0x8(%RCX,%RDX,1),%XMM10,%XMM0    [8]

0x45e1f8 VSUBSD	0x8(%R13,%RDX,1),%XMM0,%XMM13    [4]

0x45e1ff VMOVSD	%XMM13,0x8(%RCX,%RDX,1)    [8]

0x45e205 VADDSD	0x8(%R9,%RDX,1),%XMM5,%XMM14    [2]

0x45e20c VSUBSD	%XMM11,%XMM9,%XMM7

0x45e211 VADDSD	%XMM12,%XMM14,%XMM6

0x45e216 VMOVSD	%XMM6,0x8(%R9,%RDX,1)    [2]

0x45e21d VMOVSD	0x10(%R8,%RDX,1),%XMM8    [1]

0x45e224 VMOVSD	0x10(%RBX,%RDX,1),%XMM2    [7]

0x45e22a VFMADD213SD	0x10(%RDI,%RDX,1),%XMM1,%XMM8    [3]

0x45e231 VFMSUB132SD	%XMM1,%XMM8,%XMM2

0x45e236 VMOVSD	0x10(%RAX,%RDX,1),%XMM3    [6]

0x45e23c VMOVSD	0x10(%R14,%RDX,1),%XMM4    [5]

0x45e243 VADDSD	0x10(%RCX,%RDX,1),%XMM4,%XMM9    [8]

0x45e249 VSUBSD	0x10(%R13,%RDX,1),%XMM9,%XMM10    [4]

0x45e250 VMOVSD	%XMM10,0x10(%RCX,%RDX,1)    [8]

0x45e256 VADDSD	0x10(%R9,%RDX,1),%XMM3,%XMM11    [2]

0x45e25d VSUBSD	%XMM8,%XMM7,%XMM12

0x45e262 VADDSD	%XMM2,%XMM11,%XMM5

0x45e266 VMOVSD	%XMM5,0x10(%R9,%RDX,1)    [2]

0x45e26d VMOVSD	0x18(%R14,%RDX,1),%XMM0    [5]

0x45e274 VMOVSD	0x18(%R8,%RDX,1),%XMM13    [1]

0x45e27b VFMADD213SD	0x18(%RDI,%RDX,1),%XMM1,%XMM13    [3]

0x45e282 VMOVSD	0x18(%RBX,%RDX,1),%XMM15    [7]

0x45e288 VFMSUB132SD	%XMM1,%XMM13,%XMM15

0x45e28d VADDSD	0x18(%RCX,%RDX,1),%XMM0,%XMM6    [8]

0x45e293 VMOVSD	0x18(%RAX,%RDX,1),%XMM14    [6]

0x45e299 VSUBSD	0x18(%R13,%RDX,1),%XMM6,%XMM7    [4]

0x45e2a0 VMOVSD	%XMM7,0x18(%RCX,%RDX,1)    [8]

0x45e2a6 VADDSD	0x18(%R9,%RDX,1),%XMM14,%XMM8    [2]

0x45e2ad VSUBSD	%XMM13,%XMM12,%XMM0

0x45e2b2 VADDSD	%XMM15,%XMM8,%XMM3

0x45e2b7 VMOVSD	%XMM3,0x18(%R9,%RDX,1)    [2]

0x45e2be ADD	$0x20,%RDX

0x45e2c2 CMP	%R15,%RDX

0x45e2c5 JNE	45e181

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.64+	qmcplusplus::WaveFunction::acc[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P6, P7, P8, P9, P12, P13,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	1.25
Front-end cycles	6.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	10.00
P13 cycles	10.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	55.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.60
Nb FLOP add-sub	20.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	1.89
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	12.74
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P6, P7, P8, P9, P12, P13,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	1.25
Front-end cycles	6.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	10.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	10.00
P13 cycles	10.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	55.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.60
Nb FLOP add-sub	20.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	1.89
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	12.74
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.00 to 1.25 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 6.88 cycles (1.45x speedup).

Workaround

Reduce the number of FP add instructions
Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	55
loop length	330
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.88
Dispatch	10.00
Data deps.	8.00
Overall L1	10.00

Vectorization ratios

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

10% of peak load performance is reached (25.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45e181

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%RBX,%RDX,1),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD (%R8,%RDX,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RDI,%RDX,1),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM14,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,1),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%RDX,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RCX,%RDX,1),%XMM13,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD (%R13,%RDX,1),%XMM4,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM3,(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R9,%RDX,1),%XMM15,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM8,(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RDX,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBX,%RDX,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RDI,%RDX,1),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x8(%R14,%RDX,1),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX,%RDX,1),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%RCX,%RDX,1),%XMM10,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x8(%R13,%RDX,1),%XMM0,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,0x8(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD 0x8(%R9,%RDX,1),%XMM5,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM12,%XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM6,0x8(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R8,%RDX,1),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RBX,%RDX,1),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RDI,%RDX,1),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX,%RDX,1),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%R14,%RDX,1),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x10(%RCX,%RDX,1),%XMM4,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x10(%R13,%RDX,1),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM10,0x10(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD 0x10(%R9,%RDX,1),%XMM3,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM8,%XMM7,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM11,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM5,0x10(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x18(%R14,%RDX,1),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%R8,%RDX,1),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x18(%RDI,%RDX,1),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x18(%RBX,%RDX,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD 0x18(%RCX,%RDX,1),%XMM0,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x18(%RAX,%RDX,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x18(%R13,%RDX,1),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM7,0x18(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD 0x18(%R9,%RDX,1),%XMM14,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM15,%XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM3,0x18(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 45e181 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x211>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 6.88 cycles (1.45x speedup).

Workaround

Reduce the number of FP add instructions
Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	55
loop length	330
used x86 registers	10
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	10.00	10.00	10.00	10.00	4.00	4.00	10.00	10.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.88
Dispatch	10.00
Data deps.	8.00
Overall L1	10.00

Vectorization ratios

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

10% of peak load performance is reached (25.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45e181

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSD (%RBX,%RDX,1),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD (%R8,%RDX,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RDI,%RDX,1),%XMM1,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM14,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,1),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX,%RDX,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RCX,%RDX,1),%XMM13,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD (%R13,%RDX,1),%XMM4,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM3,(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD (%R9,%RDX,1),%XMM15,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM7,%XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM8,(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x8(%R8,%RDX,1),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBX,%RDX,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x8(%RDI,%RDX,1),%XMM1,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x8(%R14,%RDX,1),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX,%RDX,1),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x8(%RCX,%RDX,1),%XMM10,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x8(%R13,%RDX,1),%XMM0,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,0x8(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD 0x8(%R9,%RDX,1),%XMM5,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM11,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM12,%XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM6,0x8(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x10(%R8,%RDX,1),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RBX,%RDX,1),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x10(%RDI,%RDX,1),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x10(%RAX,%RDX,1),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%R14,%RDX,1),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x10(%RCX,%RDX,1),%XMM4,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x10(%R13,%RDX,1),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM10,0x10(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD 0x10(%R9,%RDX,1),%XMM3,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM8,%XMM7,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM11,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM5,0x10(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x18(%R14,%RDX,1),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%R8,%RDX,1),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD 0x18(%RDI,%RDX,1),%XMM1,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x18(%RBX,%RDX,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMSUB132SD %XMM1,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD 0x18(%RCX,%RDX,1),%XMM0,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x18(%RAX,%RDX,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD 0x18(%R13,%RDX,1),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM7,0x18(%RCX,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDSD 0x18(%R9,%RDX,1),%XMM14,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM13,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM15,%XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM3,0x18(%R9,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 45e181 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x211>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code