OV - exec - Loop 623

	Loop Id: 623	Module: exec	Source: :0-0	Coverage: 0.58%

0x45e515 VMOVUPD	(%R15,%R8,1),%ZMM4    [4]

0x45e51c VMOVUPD	(%RAX,%R8,1),%ZMM1    [5]

0x45e523 VMOVUPD	(%RCX,%R8,1),%ZMM3    [1]

0x45e52a VMOVUPD	(%R12,%R8,1),%ZMM2    [3]

0x45e531 VFMADD132PD	(%R9,%R8,1),%ZMM2,%ZMM3    [2]

0x45e538 VMOVUPD	0x40(%R12,%R8,1),%ZMM5    [3]

0x45e540 VMOVUPD	0x80(%R12,%R8,1),%ZMM2    [3]

0x45e548 VFNMADD231PD	%ZMM4,%ZMM1,%ZMM3

0x45e54e VFMADD231PD	%ZMM4,%ZMM1,%ZMM0

0x45e554 VMOVUPD	%ZMM3,(%R12,%R8,1)    [3]

0x45e55b VMOVUPD	0x40(%R15,%R8,1),%ZMM11    [4]

0x45e563 VMOVUPD	0x40(%RAX,%R8,1),%ZMM12    [5]

0x45e56b VMOVUPD	0x40(%RCX,%R8,1),%ZMM13    [1]

0x45e573 VFMADD132PD	0x40(%R9,%R8,1),%ZMM5,%ZMM13    [2]

0x45e57b VFNMADD231PD	%ZMM11,%ZMM12,%ZMM13

0x45e581 VFMADD132PD	%ZMM11,%ZMM0,%ZMM12

0x45e587 VMOVUPD	%ZMM13,0x40(%R12,%R8,1)    [3]

0x45e58f VMOVUPD	0x80(%R15,%R8,1),%ZMM4    [4]

0x45e597 VMOVUPD	0x80(%RAX,%R8,1),%ZMM1    [5]

0x45e59f VMOVUPD	0x80(%RCX,%R8,1),%ZMM3    [1]

0x45e5a7 VFMADD132PD	0x80(%R9,%R8,1),%ZMM2,%ZMM3    [2]

0x45e5af VMOVUPD	0xc0(%R12,%R8,1),%ZMM13    [3]

0x45e5b7 VFNMADD231PD	%ZMM4,%ZMM1,%ZMM3

0x45e5bd VFMADD132PD	%ZMM4,%ZMM12,%ZMM1

0x45e5c3 VMOVUPD	%ZMM3,0x80(%R12,%R8,1)    [3]

0x45e5cb VMOVUPD	0xc0(%R15,%R8,1),%ZMM11    [4]

0x45e5d3 VMOVUPD	0xc0(%RAX,%R8,1),%ZMM0    [5]

0x45e5db VMOVUPD	0xc0(%RCX,%R8,1),%ZMM12    [1]

0x45e5e3 VFMADD132PD	0xc0(%R9,%R8,1),%ZMM13,%ZMM12    [2]

0x45e5eb VFNMADD231PD	%ZMM11,%ZMM0,%ZMM12

0x45e5f1 VFMADD132PD	%ZMM11,%ZMM1,%ZMM0

0x45e5f7 VMOVUPD	%ZMM12,0xc0(%R12,%R8,1)    [3]

0x45e5ff ADD	$0x100,%R8

0x45e606 CMP	%R8,%RDX

0x45e609 JNE	45e515

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.70+	qmcplusplus::WaveFunction::acc[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	20.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	1280.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	4.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	20.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	1280.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 96 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 20 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 20 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1280 bytes (160 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	34
loop length	250
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	9
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	4.25
Dispatch	6.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

31% of peak load performance is reached (80.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45e515

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R15,%R8,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RAX,%R8,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R8,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R12,%R8,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD (%R9,%R8,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD 0x40(%R12,%R8,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R12,%R8,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD231PD %ZMM4,%ZMM1,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x40(%R15,%R8,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RAX,%R8,1),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R8,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x40(%R9,%R8,1),%ZMM5,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD231PD %ZMM11,%ZMM12,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM11,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x40(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x80(%R15,%R8,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RAX,%R8,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RCX,%R8,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x80(%R9,%R8,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD 0xc0(%R12,%R8,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD231PD %ZMM4,%ZMM1,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM4,%ZMM12,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,0x80(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0xc0(%R15,%R8,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%RAX,%R8,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%RCX,%R8,1),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0xc0(%R9,%R8,1),%ZMM13,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD231PD %ZMM11,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM11,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM12,0xc0(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x100,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 45e515 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x5a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 96 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 20 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 20 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1280 bytes (160 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	34
loop length	250
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	9
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	4.25
Dispatch	6.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

31% of peak load performance is reached (80.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45e515

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R15,%R8,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RAX,%R8,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R8,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R12,%R8,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD (%R9,%R8,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD 0x40(%R12,%R8,1),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R12,%R8,1),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD231PD %ZMM4,%ZMM1,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x40(%R15,%R8,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RAX,%R8,1),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R8,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x40(%R9,%R8,1),%ZMM5,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD231PD %ZMM11,%ZMM12,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM11,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM13,0x40(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0x80(%R15,%R8,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RAX,%R8,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%RCX,%R8,1),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x80(%R9,%R8,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD 0xc0(%R12,%R8,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFNMADD231PD %ZMM4,%ZMM1,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM4,%ZMM12,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,0x80(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD 0xc0(%R15,%R8,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%RAX,%R8,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%RCX,%R8,1),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0xc0(%R9,%R8,1),%ZMM13,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD231PD %ZMM11,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM11,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM12,0xc0(%R12,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x100,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 45e515 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x5a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code