OV - exec - Loop 388

	Loop Id: 388	Module: exec	Source: :0-0	Coverage: 0.04%

0x4383d0 VMULPD	0x40(%R15),%ZMM28,%ZMM8    [1]

0x4383d7 VMULPD	(%R15),%ZMM28,%ZMM7    [1]

0x4383dd KMOVB	%K1,%K2

0x4383e1 KMOVB	%K1,%K3

0x4383e5 VMOVAPD	%ZMM31,%ZMM10

0x4383eb VMOVAPD	%ZMM31,%ZMM11

0x4383f1 SUB	$-0x80,%R15

0x4383f5 KMOVB	%K1,%K4

0x4383f9 KMOVB	%K1,%K5

0x4383fd KMOVB	%K1,%K6

0x438401 KMOVB	%K1,%K7

0x438405 VRNDSCALEPD	$0xb,%ZMM8,%ZMM1

0x43840c VCVTTPD2DQ	%ZMM7,%YMM9

0x438412 VCVTTPD2DQ	%ZMM8,%YMM4

0x438418 VINSERTI32X8	$0x1,%YMM4,%ZMM9,%ZMM2

0x43841f VGATHERDPD	(%RAX,%YMM9,8),%ZMM6{%K2}    [4]

0x438426 VMOVAPD	%ZMM6,-0x70(%RBP)    [2]

0x438430 VSHUFI32X4	$-0x12,%ZMM2,%ZMM2,%ZMM3

0x438437 KMOVB	%K1,%K2

0x43843b VGATHERDPD	(%RAX,%YMM3,8),%ZMM24{%K3}    [4]

0x438442 KMOVB	%K1,%K3

0x438446 VRNDSCALEPD	$0xb,%ZMM7,%ZMM5

0x43844d VSUBPD	%ZMM1,%ZMM8,%ZMM1

0x438453 VFMADD132PD	%ZMM1,%ZMM25,%ZMM10

0x438459 VSUBPD	%ZMM5,%ZMM7,%ZMM0

0x43845f VMULPD	%ZMM1,%ZMM1,%ZMM5

0x438465 VPADDD	-0x170(%RBP),%ZMM2,%ZMM3    [2]

0x43846f VMULPD	%ZMM0,%ZMM0,%ZMM4

0x438475 VFMADD132PD	%ZMM0,%ZMM25,%ZMM11

0x43847b VMULPD	%ZMM1,%ZMM5,%ZMM7

0x438481 VMULPD	%ZMM5,%ZMM26,%ZMM13

0x438487 VMULPD	%ZMM0,%ZMM4,%ZMM8

0x43848d VMULPD	%ZMM4,%ZMM26,%ZMM12

0x438493 VFMADD231PD	%ZMM7,%ZMM27,%ZMM13

0x438499 VFMADD231PD	%ZMM8,%ZMM27,%ZMM12

0x43849f VADDPD	%ZMM13,%ZMM10,%ZMM9

0x4384a5 VMOVAPD	-0xf0(%RBP),%ZMM10    [2]

0x4384af VSHUFI32X4	$-0x12,%ZMM3,%ZMM3,%ZMM13

0x4384b6 VADDPD	%ZMM12,%ZMM11,%ZMM11

0x4384bc VGATHERDPD	(%RAX,%YMM3,8),%ZMM12{%K4}    [4]

0x4384c3 VMOVAPD	%ZMM12,-0xb0(%RBP)    [2]

0x4384cd VGATHERDPD	(%RAX,%YMM13,8),%ZMM6{%K5}    [4]

0x4384d4 VMULPD	%ZMM10,%ZMM4,%ZMM12

0x4384da VMULPD	%ZMM10,%ZMM5,%ZMM13

0x4384e0 VMOVAPD	-0x130(%RBP),%ZMM10    [2]

0x4384ea VFMADD231PD	%ZMM23,%ZMM7,%ZMM13

0x4384f0 VFMADD231PD	%ZMM23,%ZMM8,%ZMM12

0x4384f6 VMOVAPD	%ZMM10,%ZMM3

0x4384fc VFMADD132PD	%ZMM1,%ZMM30,%ZMM10

0x438502 VFMADD132PD	%ZMM0,%ZMM30,%ZMM3

0x438508 VADDPD	%ZMM13,%ZMM10,%ZMM13

0x43850e VMOVAPD	%ZMM1,%ZMM10

0x438514 VFMADD132PD	%ZMM17,%ZMM16,%ZMM1

0x43851a VADDPD	%ZMM12,%ZMM3,%ZMM12

0x438520 VMULPD	-0xb0(%RBP),%ZMM12,%ZMM3    [2]

0x43852a VFMADD132PD	%ZMM21,%ZMM20,%ZMM10

0x438530 VMULPD	%ZMM13,%ZMM6,%ZMM6

0x438536 VFMADD231PD	-0x70(%RBP),%ZMM11,%ZMM3    [2]

0x438540 VFMADD231PD	%ZMM9,%ZMM24,%ZMM6

0x438546 VPADDD	-0x1b0(%RBP),%ZMM2,%ZMM9    [2]

0x438550 VPADDD	0x19fae6(%RIP),%ZMM2,%ZMM2    [3]

0x43855a VMOVAPD	%ZMM0,%ZMM24

0x438560 VFMADD132PD	%ZMM17,%ZMM16,%ZMM0

0x438566 VFMADD132PD	%ZMM21,%ZMM20,%ZMM24

0x43856c VSHUFI32X4	$-0x12,%ZMM9,%ZMM9,%ZMM13

0x438573 VGATHERDPD	(%RAX,%YMM9,8),%ZMM11{%K6}    [4]

0x43857a VGATHERDPD	(%RAX,%YMM13,8),%ZMM12{%K7}    [4]

0x438581 VMULPD	%ZMM22,%ZMM4,%ZMM9

0x438587 VMULPD	%ZMM22,%ZMM5,%ZMM13

0x43858d VMULPD	%ZMM18,%ZMM4,%ZMM4

0x438593 VMULPD	%ZMM18,%ZMM5,%ZMM5

0x438599 VFMADD231PD	%ZMM29,%ZMM8,%ZMM9

0x43859f VFMADD231PD	%ZMM29,%ZMM7,%ZMM13

0x4385a5 VFMADD231PD	%ZMM19,%ZMM8,%ZMM4

0x4385ab VFMADD231PD	%ZMM19,%ZMM7,%ZMM5

0x4385b1 VADDPD	%ZMM24,%ZMM9,%ZMM9

0x4385b7 VADDPD	%ZMM13,%ZMM10,%ZMM10

0x4385bd VADDPD	%ZMM4,%ZMM0,%ZMM0

0x4385c3 VGATHERDPD	(%RAX,%YMM2,8),%ZMM13{%K2}    [4]

0x4385ca VSHUFI32X4	$-0x12,%ZMM2,%ZMM2,%ZMM2

0x4385d1 VADDPD	%ZMM5,%ZMM1,%ZMM1

0x4385d7 VGATHERDPD	(%RAX,%YMM2,8),%ZMM24{%K3}    [4]

0x4385de VMULPD	%ZMM13,%ZMM0,%ZMM8

0x4385e4 VMULPD	%ZMM1,%ZMM24,%ZMM24

0x4385ea VFMADD132PD	%ZMM9,%ZMM8,%ZMM11

0x4385f0 VFMADD231PD	%ZMM10,%ZMM12,%ZMM24

0x4385f6 VADDPD	%ZMM11,%ZMM3,%ZMM7

0x4385fc VADDPD	%ZMM24,%ZMM6,%ZMM24

0x438602 VADDPD	%ZMM7,%ZMM14,%ZMM14

0x438608 VADDPD	%ZMM24,%ZMM15,%ZMM15

0x43860e CMP	%R15,%R14

0x438611 JNE	4383d0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.10+	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	56.88
CQA cycles if no scalar integer	55.88
CQA cycles if FP arith vectorized	56.88
CQA cycles if fully vectorized	55.33
Front-end cycles	56.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	18.75
P7 cycles	18.75
P8 cycles	18.75
P9 cycles	18.75
P10 cycles	44.50
P11 cycles	44.50
P12 cycles	44.50
P13 cycles	44.50
P14 cycles	42.00
P15 cycles	42.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	7 - 39
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	92.00
Nb uops	455.00
Nb loads	17.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	10.13
Nb FLOP add-sub	112.00
Nb FLOP mul	144.00
Nb FLOP fma	160.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.38
Bytes prefetched	0.00
Bytes loaded	1088.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	96.91
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	88.64

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	56.88
CQA cycles if no scalar integer	55.88
CQA cycles if FP arith vectorized	56.88
CQA cycles if fully vectorized	55.33
Front-end cycles	56.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	18.75
P7 cycles	18.75
P8 cycles	18.75
P9 cycles	18.75
P10 cycles	44.50
P11 cycles	44.50
P12 cycles	44.50
P13 cycles	44.50
P14 cycles	42.00
P15 cycles	42.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	7 - 39
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	92.00
Nb uops	455.00
Nb loads	17.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	10.13
Nb FLOP add-sub	112.00
Nb FLOP mul	144.00
Nb FLOP fma	160.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.38
Bytes prefetched	0.00
Bytes loaded	1088.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	96.91
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	88.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 96% register length (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 56.88 to 55.33 cycles (1.03x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 160 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
VGATHERDPD: 8 occurrences►
VMOVAPD: 2 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

54 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 576 FP arithmetical operations:

272: addition or subtraction (160 inside FMA instructions)
304: multiply (160 inside FMA instructions)

The binary loop is loading 1088 bytes (136 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.47 FP operations per loaded or stored byte.

General properties

nb instructions	92
nb uops	455
loop length	583
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	32
nb stack references	6
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	56.88 cycles
front end	56.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	18.75	18.75	18.75	18.75	44.50	44.50	44.50	44.50	42.00	42.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	18.75	18.75	18.75	18.75	44.50	44.50	44.50	44.50	42.00	42.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00-39.00

Cycles summary

Front-end	56.88
Dispatch	44.50
Data deps.	7.00-39.00
Overall L1	56.88

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	68%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	88%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.88 cycles. At this rate:

7% of peak load performance is reached (19.13 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 56.88 to 44.50 cycles (1.28x speedup).

ASM code

In the binary file, the address of the loop is: 4383d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD 0x40(%R15),%ZMM28,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%R15),%ZMM28,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVAPD %ZMM31,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM31,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
SUB $-0x80,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VRNDSCALEPD $0xb,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM7,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VCVTTPD2DQ %ZMM8,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VINSERTI32X8 $0x1,%YMM4,%ZMM9,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM9,8),%ZMM6{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM6,-0x70(%RBP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM2,%ZMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%RAX,%YMM3,8),%ZMM24{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VRNDSCALEPD $0xb,%ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM1,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM25,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPADDD -0x170(%RBP),%ZMM2,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM25,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM26,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM4,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM26,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM27,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM27,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM10,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0xf0(%RBP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM3,%ZMM3,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VADDPD %ZMM12,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM3,8),%ZMM12{%K4}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM12,-0xb0(%RBP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VGATHERDPD (%RAX,%YMM13,8),%ZMM6{%K5}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM10,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM5,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x130(%RBP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM7,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM8,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM30,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM30,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM10,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM1,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM16,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM3,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD -0xb0(%RBP),%ZMM12,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM20,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD -0x70(%RBP),%ZMM11,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM24,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VPADDD -0x1b0(%RBP),%ZMM2,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPADDD 0x19fae6(%RIP),%ZMM2,%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM16,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM20,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM9,%ZMM9,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM9,8),%ZMM11{%K6}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM13,8),%ZMM12{%K7}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM22,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM22,%ZMM5,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM7,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM2,8),%ZMM13{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM2,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VADDPD %ZMM5,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM2,8),%ZMM24{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM13,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM9,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM12,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM7,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
CMP %R15,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4383d0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 160 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
VGATHERDPD: 8 occurrences►
VMOVAPD: 2 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

54 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 576 FP arithmetical operations:

272: addition or subtraction (160 inside FMA instructions)
304: multiply (160 inside FMA instructions)

The binary loop is loading 1088 bytes (136 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.47 FP operations per loaded or stored byte.

General properties

nb instructions	92
nb uops	455
loop length	583
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	32
nb stack references	6
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	56.88 cycles
front end	56.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	18.75	18.75	18.75	18.75	44.50	44.50	44.50	44.50	42.00	42.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	18.75	18.75	18.75	18.75	44.50	44.50	44.50	44.50	42.00	42.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00-39.00

Cycles summary

Front-end	56.88
Dispatch	44.50
Data deps.	7.00-39.00
Overall L1	56.88

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	68%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	96%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	88%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.88 cycles. At this rate:

7% of peak load performance is reached (19.13 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4383d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD 0x40(%R15),%ZMM28,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD (%R15),%ZMM28,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVAPD %ZMM31,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM31,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
SUB $-0x80,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VRNDSCALEPD $0xb,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM7,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VCVTTPD2DQ %ZMM8,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VINSERTI32X8 $0x1,%YMM4,%ZMM9,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM9,8),%ZMM6{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM6,-0x70(%RBP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM2,%ZMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%RAX,%YMM3,8),%ZMM24{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VRNDSCALEPD $0xb,%ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM1,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM25,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPADDD -0x170(%RBP),%ZMM2,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM25,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM26,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM4,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM26,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM27,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM27,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM10,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0xf0(%RBP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM3,%ZMM3,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VADDPD %ZMM12,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM3,8),%ZMM12{%K4}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM12,-0xb0(%RBP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VGATHERDPD (%RAX,%YMM13,8),%ZMM6{%K5}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM10,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM5,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x130(%RBP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM7,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM8,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM30,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM30,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM10,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM1,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM16,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM3,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD -0xb0(%RBP),%ZMM12,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM20,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM13,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD -0x70(%RBP),%ZMM11,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM24,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VPADDD -0x1b0(%RBP),%ZMM2,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPADDD 0x19fae6(%RIP),%ZMM2,%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM16,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM20,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM9,%ZMM9,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM9,8),%ZMM11{%K6}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM13,8),%ZMM12{%K7}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM22,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM22,%ZMM5,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM7,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM2,8),%ZMM13{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM2,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VADDPD %ZMM5,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM2,8),%ZMM24{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM13,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM9,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM12,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM7,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
CMP %R15,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4383d0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code