OV - exec - Loop 297

	Loop Id: 297	Module: exec	Source: :0-0	Coverage: 0.01%

0x428540 VMOVAPD	(%RCX,%RDX,2),%ZMM11    [8]

0x428547 VMOVAPD	0x40(%RCX,%RDX,2),%ZMM10    [8]

0x42854f KMOVB	%K1,%K2

0x428553 KMOVB	%K1,%K3

0x428557 VMOVAPD	-0x2f0(%RBP),%ZMM24    [4]

0x428561 VMOVDQA32	(%RDI,%RDX,1),%ZMM7    [3]

0x428568 ADD	$0x40,%RDX

0x42856c KMOVB	%K1,%K5

0x428570 KMOVB	%K1,%K4

0x428574 KMOVB	%K1,%K6

0x428578 KMOVB	%K1,%K7

0x42857c VMULPD	%ZMM18,%ZMM11,%ZMM0

0x428582 VMULPD	%ZMM18,%ZMM10,%ZMM1

0x428588 VCVTTPD2DQ	%ZMM0,%YMM9

0x42858e VCVTTPD2DQ	%ZMM1,%YMM2

0x428594 VINSERTI32X8	$0x1,%YMM2,%ZMM9,%ZMM5

0x42859b VPADDD	0x1afa1b(%RIP),%ZMM5,%ZMM8    [6]

0x4285a5 VPADDD	0x1afa51(%RIP),%ZMM5,%ZMM15    [6]

0x4285af VSHUFI32X4	$-0x12,%ZMM5,%ZMM5,%ZMM4

0x4285b6 VPADDD	0x1afa80(%RIP),%ZMM5,%ZMM5    [6]

0x4285c0 VGATHERDPD	(%RAX,%YMM9,8),%ZMM22{%K2}    [7]

0x4285c7 VGATHERDPD	(%RAX,%YMM4,8),%ZMM21{%K3}    [7]

0x4285ce KMOVB	%K1,%K2

0x4285d2 KMOVB	%K1,%K3

0x4285d6 VRNDSCALEPD	$0xb,%ZMM0,%ZMM12

0x4285dd VSHUFI32X4	$-0x12,%ZMM8,%ZMM8,%ZMM6

0x4285e4 VGATHERDPD	(%RAX,%YMM8,8),%ZMM23{%K4}    [7]

0x4285eb VGATHERDPD	(%RAX,%YMM6,8),%ZMM4{%K5}    [7]

0x4285f2 VGATHERDPD	(%RAX,%YMM5,8),%ZMM20{%K2}    [7]

0x4285f9 VSHUFI32X4	$-0x12,%ZMM5,%ZMM5,%ZMM6

0x428600 VGATHERDPD	(%RAX,%YMM15,8),%ZMM8{%K6}    [7]

0x428607 VMOVAPD	-0x130(%RBP),%ZMM5    [4]

0x428611 VSHUFI32X4	$-0x12,%ZMM15,%ZMM15,%ZMM9

0x428618 VMOVAPD	-0x170(%RBP),%ZMM15    [4]

0x428622 VSUBPD	%ZMM12,%ZMM0,%ZMM0

0x428628 VRNDSCALEPD	$0xb,%ZMM1,%ZMM13

0x42862f KMOVB	%K1,%K4

0x428633 KMOVB	%K1,%K5

0x428637 VGATHERDPD	(%RAX,%YMM9,8),%ZMM12{%K7}    [7]

0x42863e VMULPD	%ZMM0,%ZMM0,%ZMM2

0x428644 KMOVB	%K1,%K6

0x428648 KMOVB	%K1,%K7

0x42864c KMOVB	%K1,%K2

0x428650 VSUBPD	%ZMM13,%ZMM1,%ZMM1

0x428656 VMOVAPD	-0x1b0(%RBP),%ZMM9    [4]

0x428660 VGATHERDPD	(%RAX,%YMM6,8),%ZMM13{%K3}    [7]

0x428667 VMOVAPD	%ZMM5,%ZMM6

0x42866d VFMADD132PD	%ZMM0,%ZMM15,%ZMM6

0x428673 VFMADD132PD	%ZMM1,%ZMM15,%ZMM5

0x428679 VMOVAPD	-0x1f0(%RBP),%ZMM15    [4]

0x428683 VMULPD	%ZMM1,%ZMM1,%ZMM3

0x428689 VMULPD	%ZMM2,%ZMM0,%ZMM17

0x42868f KMOVB	%K1,%K3

0x428693 VMULPD	%ZMM3,%ZMM1,%ZMM16

0x428699 VMOVAPD	%ZMM9,%ZMM14

0x42869f VFMADD132PD	%ZMM0,%ZMM15,%ZMM14

0x4286a5 VFMADD132PD	%ZMM1,%ZMM15,%ZMM9

0x4286ab VMOVAPD	-0x230(%RBP),%ZMM15    [4]

0x4286b5 VMULPD	%ZMM9,%ZMM4,%ZMM9

0x4286bb VMULPD	%ZMM14,%ZMM23,%ZMM14

0x4286c1 VMOVAPD	%ZMM15,%ZMM19

0x4286c7 VFMADD132PD	%ZMM22,%ZMM14,%ZMM6

0x4286cd VFMADD132PD	%ZMM21,%ZMM9,%ZMM5

0x4286d3 VMOVAPD	-0x270(%RBP),%ZMM14    [4]

0x4286dd VMOVAPD	-0x2b0(%RBP),%ZMM9    [4]

0x4286e7 VFMADD132PD	%ZMM0,%ZMM14,%ZMM19

0x4286ed VFMADD132PD	%ZMM1,%ZMM14,%ZMM15

0x4286f3 VMOVAPD	%ZMM9,%ZMM14

0x4286f9 VFMADD132PD	%ZMM0,%ZMM24,%ZMM14

0x4286ff VFMADD132PD	%ZMM1,%ZMM24,%ZMM9

0x428705 VMULPD	%ZMM14,%ZMM20,%ZMM14

0x42870b VMULPD	%ZMM9,%ZMM13,%ZMM9

0x428711 VFMADD231PD	%ZMM19,%ZMM8,%ZMM14

0x428717 VFMADD231PD	%ZMM15,%ZMM12,%ZMM9

0x42871d VMOVAPD	-0x330(%RBP),%ZMM15    [4]

0x428727 VMOVDQA32	%YMM7,%YMM19

0x42872d VADDPD	%ZMM14,%ZMM6,%ZMM6

0x428733 VADDPD	%ZMM9,%ZMM5,%ZMM5

0x428739 VMULPD	%ZMM15,%ZMM6,%ZMM14

0x42873f VMULPD	%ZMM15,%ZMM5,%ZMM9

0x428745 VBROADCASTSD	0x1afa81(%RIP),%ZMM6    [6]

0x42874f VSCATTERDPD	%ZMM14,(%R13,%YMM7,8){%K4}    [5]

0x428757 VSHUFI32X4	$-0x12,%ZMM7,%ZMM7,%ZMM7

0x42875e VSCATTERDPD	%ZMM9,(%R13,%YMM7,8){%K5}    [5]

0x428766 VMOVAPD	-0x3b0(%RBP),%ZMM5    [4]

0x428770 VMOVAPD	-0x3f0(%RBP),%ZMM15    [4]

0x42877a VMOVAPD	-0x370(%RBP),%ZMM14    [4]

0x428784 VMOVAPD	-0x470(%RBP),%ZMM9    [4]

0x42878e VDIVPD	%ZMM11,%ZMM6,%ZMM11

0x428794 VDIVPD	%ZMM10,%ZMM6,%ZMM10

0x42879a VMOVAPD	%ZMM5,%ZMM6

0x4287a0 VFMADD132PD	%ZMM1,%ZMM15,%ZMM5

0x4287a6 VFMADD132PD	%ZMM0,%ZMM15,%ZMM6

0x4287ac VMOVAPD	-0x4b0(%RBP),%ZMM15    [4]

0x4287b6 VFMADD231PD	%ZMM14,%ZMM3,%ZMM5

0x4287bc VMULPD	%ZMM18,%ZMM11,%ZMM11

0x4287c2 VFMADD231PD	%ZMM14,%ZMM2,%ZMM6

0x4287c8 VMOVAPD	%ZMM9,%ZMM14

0x4287ce VFMADD132PD	%ZMM0,%ZMM15,%ZMM14

0x4287d4 VFMADD132PD	%ZMM1,%ZMM15,%ZMM9

0x4287da VMOVAPD	-0x430(%RBP),%ZMM15    [4]

0x4287e4 VFMADD231PD	%ZMM15,%ZMM2,%ZMM14

0x4287ea VFMADD231PD	%ZMM15,%ZMM3,%ZMM9

0x4287f0 VMULPD	%ZMM18,%ZMM10,%ZMM10

0x4287f6 VMULPD	%ZMM14,%ZMM23,%ZMM14

0x4287fc VMULPD	%ZMM9,%ZMM4,%ZMM9

0x428802 VFMADD132PD	%ZMM22,%ZMM14,%ZMM6

0x428808 VMOVAPD	-0x530(%RBP),%ZMM14    [4]

0x428812 VMOVAPD	-0x570(%RBP),%ZMM15    [4]

0x42881c VFMADD132PD	%ZMM21,%ZMM9,%ZMM5

0x428822 VMOVAPD	-0x4f0(%RBP),%ZMM9    [4]

0x42882c VMOVAPD	%ZMM14,%ZMM24

0x428832 VFMADD132PD	%ZMM1,%ZMM15,%ZMM14

0x428838 VFMADD132PD	%ZMM0,%ZMM15,%ZMM24

0x42883e VMOVAPD	-0x5b0(%RBP),%ZMM15    [4]

0x428848 VFMADD231PD	%ZMM9,%ZMM3,%ZMM14

0x42884e VFMADD231PD	%ZMM9,%ZMM2,%ZMM24

0x428854 VMOVAPD	%ZMM15,%ZMM9

0x42885a VFMADD213PD	-0xf0(%RBP),%ZMM1,%ZMM15    [4]

0x428864 VFMADD213PD	-0xf0(%RBP),%ZMM0,%ZMM9    [4]

0x42886e VFMADD231PD	-0xb0(%RBP),%ZMM3,%ZMM15    [4]

0x428878 VFMADD231PD	-0xb0(%RBP),%ZMM2,%ZMM9    [4]

0x428882 VMULPD	%ZMM15,%ZMM13,%ZMM15

0x428888 VMULPD	%ZMM9,%ZMM20,%ZMM9

0x42888e VFMADD132PD	%ZMM12,%ZMM15,%ZMM14

0x428894 VFMADD231PD	%ZMM24,%ZMM8,%ZMM9

0x42889a VADDPD	%ZMM14,%ZMM5,%ZMM5

0x4288a0 VADDPD	%ZMM9,%ZMM6,%ZMM6

0x4288a6 VMULPD	%ZMM10,%ZMM5,%ZMM10

0x4288ac VMULPD	%ZMM11,%ZMM6,%ZMM11

0x4288b2 VSCATTERDPD	%ZMM11,(%R12,%YMM19,8){%K6}    [2]

0x4288b9 VSCATTERDPD	%ZMM10,(%R12,%YMM7,8){%K7}    [2]

0x4288c0 VMOVAPD	-0x630(%RBP),%ZMM14    [4]

0x4288ca VMOVAPD	-0x670(%RBP),%ZMM6    [4]

0x4288d4 VMOVAPD	-0x5f0(%RBP),%ZMM15    [4]

0x4288de VMOVAPD	-0x6b0(%RBP),%ZMM11    [4]

0x4288e8 VMULPD	%ZMM14,%ZMM2,%ZMM9

0x4288ee VMULPD	%ZMM14,%ZMM3,%ZMM5

0x4288f4 VMOVAPD	%ZMM6,%ZMM10

0x4288fa VMOVAPD	-0x6f0(%RBP),%ZMM14    [4]

0x428904 VFMADD132PD	%ZMM0,%ZMM11,%ZMM10

0x42890a VFMADD132PD	%ZMM1,%ZMM11,%ZMM6

0x428910 VFMADD231PD	%ZMM15,%ZMM17,%ZMM9

0x428916 VFMADD231PD	%ZMM15,%ZMM16,%ZMM5

0x42891c VMULPD	%ZMM14,%ZMM2,%ZMM11

0x428922 VMULPD	%ZMM14,%ZMM3,%ZMM14

0x428928 VADDPD	%ZMM9,%ZMM10,%ZMM10

0x42892e VMOVAPD	-0x7f0(%RBP),%ZMM9    [4]

0x428938 VADDPD	%ZMM5,%ZMM6,%ZMM6

0x42893e VFMADD231PD	%ZMM9,%ZMM17,%ZMM11

0x428944 VFMADD231PD	%ZMM9,%ZMM16,%ZMM14

0x42894a VMOVAPD	-0x730(%RBP),%ZMM9    [4]

0x428954 VMOVAPD	%ZMM9,%ZMM15

0x42895a VFMADD132PD	%ZMM1,%ZMM31,%ZMM9

0x428960 VFMADD132PD	%ZMM0,%ZMM31,%ZMM15

0x428966 VADDPD	%ZMM14,%ZMM9,%ZMM14

0x42896c VMOVAPD	%ZMM0,%ZMM9

0x428972 VFMADD132PD	%ZMM26,%ZMM25,%ZMM0

0x428978 VADDPD	%ZMM11,%ZMM15,%ZMM5

0x42897e VMOVAPD	-0x770(%RBP),%ZMM11    [4]

0x428988 VFMADD132PD	%ZMM30,%ZMM29,%ZMM9

0x42898e VMULPD	%ZMM14,%ZMM4,%ZMM4

0x428994 VMULPD	%ZMM23,%ZMM5,%ZMM15

0x42899a VMOVAPD	%ZMM1,%ZMM5

0x4289a0 VFMADD132PD	%ZMM26,%ZMM25,%ZMM1

0x4289a6 VFMADD132PD	%ZMM30,%ZMM29,%ZMM5

0x4289ac VFMADD231PD	%ZMM6,%ZMM21,%ZMM4

0x4289b2 VMOVAPD	-0x7b0(%RBP),%ZMM6    [4]

0x4289bc VFMADD231PD	%ZMM10,%ZMM22,%ZMM15

0x4289c2 VMULPD	%ZMM6,%ZMM3,%ZMM14

0x4289c8 VMULPD	%ZMM6,%ZMM2,%ZMM10

0x4289ce VMULPD	%ZMM27,%ZMM3,%ZMM3

0x4289d4 VMULPD	%ZMM27,%ZMM2,%ZMM2

0x4289da VFMADD231PD	%ZMM11,%ZMM17,%ZMM10

0x4289e0 VFMADD231PD	%ZMM11,%ZMM16,%ZMM14

0x4289e6 VFMADD231PD	%ZMM28,%ZMM17,%ZMM2

0x4289ec VFMADD231PD	%ZMM28,%ZMM16,%ZMM3

0x4289f2 VADDPD	%ZMM10,%ZMM9,%ZMM10

0x4289f8 VADDPD	%ZMM14,%ZMM5,%ZMM6

0x4289fe VADDPD	%ZMM1,%ZMM3,%ZMM1

0x428a04 VADDPD	%ZMM0,%ZMM2,%ZMM0

0x428a0a VMULPD	%ZMM1,%ZMM13,%ZMM13

0x428a10 VMULPD	%ZMM20,%ZMM0,%ZMM11

0x428a16 VFMADD132PD	%ZMM6,%ZMM13,%ZMM12

0x428a1c VFMADD132PD	%ZMM10,%ZMM11,%ZMM8

0x428a22 VADDPD	%ZMM12,%ZMM4,%ZMM12

0x428a28 VADDPD	%ZMM15,%ZMM8,%ZMM8

0x428a2e VSCATTERDPD	%ZMM8,(%R11,%YMM19,8){%K2}    [1]

0x428a35 VSCATTERDPD	%ZMM12,(%R11,%YMM7,8){%K3}    [1]

0x428a3c CMP	%R14,%RDX

0x428a3f JNE	428540

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.58+	qmcplusplus::WaveFunction::rat[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	104.25
CQA cycles if no scalar integer	102.50
CQA cycles if FP arith vectorized	104.25
CQA cycles if fully vectorized	102.13
Front-end cycles	104.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	37.75
P7 cycles	37.75
P8 cycles	37.75
P9 cycles	37.75
P10 cycles	69.25
P11 cycles	69.25
P12 cycles	69.17
P13 cycles	69.33
P14 cycles	94.00
P15 cycles	94.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	1 - 16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	191.00
Nb uops	834.00
Nb loads	47.00
Nb stores	6.00
Nb stack references	30.00
FLOP/cycle	11.82
Nb FLOP add-sub	128.00
Nb FLOP mul	256.00
Nb FLOP fma	416.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	2952.00
Bytes stored	384.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	99.43
Vectorization ratio load	97.87
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	96.88
Vector-efficiency ratio all	97.49
Vector-efficiency ratio load	98.14
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	86.33

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	104.25
CQA cycles if no scalar integer	102.50
CQA cycles if FP arith vectorized	104.25
CQA cycles if fully vectorized	102.13
Front-end cycles	104.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	37.75
P7 cycles	37.75
P8 cycles	37.75
P9 cycles	37.75
P10 cycles	69.25
P11 cycles	69.25
P12 cycles	69.17
P13 cycles	69.33
P14 cycles	94.00
P15 cycles	94.00
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	1 - 16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	191.00
Nb uops	834.00
Nb loads	47.00
Nb stores	6.00
Nb stack references	30.00
FLOP/cycle	11.82
Nb FLOP add-sub	128.00
Nb FLOP mul	256.00
Nb FLOP fma	416.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	2952.00
Bytes stored	384.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	99.43
Vectorization ratio load	97.87
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	96.88
Vector-efficiency ratio all	97.49
Vector-efficiency ratio load	98.14
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	86.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 104.25 to 102.13 cycles (1.02x speedup).

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 416 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
VGATHERDPD: 8 occurrences►
VSCATTERDPD: 6 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►
VSCATTERDPD: 6 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

104 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1232 FP arithmetical operations:

544: addition or subtraction (416 inside FMA instructions)
672: multiply (416 inside FMA instructions)
16: divide

The binary loop is loading 2952 bytes (369 double precision FP elements). The binary loop is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	191
nb uops	834
loop length	1285
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	32
nb stack references	30
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	104.25 cycles
front end	104.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	37.75	37.75	37.75	37.75	69.25	69.25	69.17	69.33	94.00	94.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	37.75	37.75	37.75	37.75	69.25	69.25	69.17	69.33	94.00	94.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	1.00-16.00

Cycles summary

Front-end	104.25
Dispatch	94.00
DIV/SQRT	8.00
Data deps.	1.00-16.00
Overall L1	104.25

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

INT+FP

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

Vector efficiency ratios

INT

all	68%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

INT+FP

all	97%
load	98%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	86%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 104.25 cycles. At this rate:

11% of peak load performance is reached (28.32 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 104.25 to 94.00 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 428540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%RCX,%RDX,2),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x40(%RCX,%RDX,2),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVAPD -0x2f0(%RBP),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA32 (%RDI,%RDX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMULPD %ZMM18,%ZMM11,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM0,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VCVTTPD2DQ %ZMM1,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VINSERTI32X8 $0x1,%YMM2,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (50.0%)
VPADDD 0x1afa1b(%RIP),%ZMM5,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPADDD 0x1afa51(%RIP),%ZMM5,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM5,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VPADDD 0x1afa80(%RIP),%ZMM5,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM9,8),%ZMM22{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM4,8),%ZMM21{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VRNDSCALEPD $0xb,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM8,%ZMM8,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM8,8),%ZMM23{%K4}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM6,8),%ZMM4{%K5}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM5,8),%ZMM20{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM5,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM15,8),%ZMM8{%K6}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD -0x130(%RBP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM15,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VMOVAPD -0x170(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM1,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%RAX,%YMM9,8),%ZMM12{%K7}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSUBPD %ZMM13,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0x1b0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM6,8),%ZMM13{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x1f0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM0,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMULPD %ZMM3,%ZMM1,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x230(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM23,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM15,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM22,%ZMM14,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x270(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x2b0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM14,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM24,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM24,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM20,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM13,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM8,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM12,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x330(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA32 %YMM7,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %ZMM14,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM6,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM5,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x1afa81(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSCATTERDPD %ZMM14,(%R13,%YMM7,8){%K4}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM7,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VSCATTERDPD %ZMM9,(%R13,%YMM7,8){%K5}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VMOVAPD -0x3b0(%RBP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x3f0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x370(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x470(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM11,%ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VDIVPD %ZMM10,%ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVAPD %ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x4b0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM14,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM14,%ZMM2,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x430(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM2,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM3,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM23,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM22,%ZMM14,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x530(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x570(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x4f0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM14,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x5b0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM3,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM2,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD -0xf0(%RBP),%ZMM1,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD -0xf0(%RBP),%ZMM0,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD -0xb0(%RBP),%ZMM3,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD -0xb0(%RBP),%ZMM2,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM13,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM20,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM12,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM24,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM5,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM11,%ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSCATTERDPD %ZMM11,(%R12,%YMM19,8){%K6}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VSCATTERDPD %ZMM10,(%R12,%YMM7,8){%K7}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VMOVAPD -0x630(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x670(%RBP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x5f0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x6b0(%RBP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM2,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD -0x6f0(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM11,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM11,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM17,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM16,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM2,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM3,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0x7f0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM17,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x730(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM31,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM31,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM25,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0x770(%RBP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM30,%ZMM29,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM5,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM1,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM25,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM30,%ZMM29,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM21,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x7b0(%RBP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM22,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM3,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM2,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM17,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM17,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM16,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM10,%ZMM9,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM20,%ZMM0,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM6,%ZMM13,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM10,%ZMM11,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSCATTERDPD %ZMM8,(%R11,%YMM19,8){%K2}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VSCATTERDPD %ZMM12,(%R11,%YMM7,8){%K3}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
CMP %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 428540 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Details

99% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

97% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 416 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
VGATHERDPD: 8 occurrences►
VSCATTERDPD: 6 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 8 occurrences►
VSCATTERDPD: 6 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

104 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1232 FP arithmetical operations:

544: addition or subtraction (416 inside FMA instructions)
672: multiply (416 inside FMA instructions)
16: divide

The binary loop is loading 2952 bytes (369 double precision FP elements). The binary loop is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	191
nb uops	834
loop length	1285
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	32
nb stack references	30
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	104.25 cycles
front end	104.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	37.75	37.75	37.75	37.75	69.25	69.25	69.17	69.33	94.00	94.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	37.75	37.75	37.75	37.75	69.25	69.25	69.17	69.33	94.00	94.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	1.00-16.00

Cycles summary

Front-end	104.25
Dispatch	94.00
DIV/SQRT	8.00
Data deps.	1.00-16.00
Overall L1	104.25

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

INT+FP

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

Vector efficiency ratios

INT

all	68%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	99%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

INT+FP

all	97%
load	98%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	86%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 104.25 cycles. At this rate:

11% of peak load performance is reached (28.32 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.68 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 428540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%RCX,%RDX,2),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x40(%RCX,%RDX,2),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVAPD -0x2f0(%RBP),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA32 (%RDI,%RDX,1),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMULPD %ZMM18,%ZMM11,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM0,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VCVTTPD2DQ %ZMM1,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VINSERTI32X8 $0x1,%YMM2,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (50.0%)
VPADDD 0x1afa1b(%RIP),%ZMM5,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPADDD 0x1afa51(%RIP),%ZMM5,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM5,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VPADDD 0x1afa80(%RIP),%ZMM5,%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM9,8),%ZMM22{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM4,8),%ZMM21{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VRNDSCALEPD $0xb,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM8,%ZMM8,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM8,8),%ZMM23{%K4}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM6,8),%ZMM4{%K5}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VGATHERDPD (%RAX,%YMM5,8),%ZMM20{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM5,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VGATHERDPD (%RAX,%YMM15,8),%ZMM8{%K6}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD -0x130(%RBP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM15,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VMOVAPD -0x170(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM1,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K4	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K5	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%RAX,%YMM9,8),%ZMM12{%K7}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K6	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K7	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSUBPD %ZMM13,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0x1b0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VGATHERDPD (%RAX,%YMM6,8),%ZMM13{%K3}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x1f0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM1,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM0,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVB %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMULPD %ZMM3,%ZMM1,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x230(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM23,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM15,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM22,%ZMM14,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x270(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x2b0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM14,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM24,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM24,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM20,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM13,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM8,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM12,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x330(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA32 %YMM7,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %ZMM14,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM6,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM5,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x1afa81(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSCATTERDPD %ZMM14,(%R13,%YMM7,8){%K4}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM7,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (50.0%)
VSCATTERDPD %ZMM9,(%R13,%YMM7,8){%K5}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VMOVAPD -0x3b0(%RBP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x3f0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x370(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x470(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM11,%ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VDIVPD %ZMM10,%ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVAPD %ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x4b0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM14,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM14,%ZMM2,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x430(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM2,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM3,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM23,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM22,%ZMM14,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x530(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x570(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM21,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x4f0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM14,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x5b0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM3,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM2,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD -0xf0(%RBP),%ZMM1,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD -0xf0(%RBP),%ZMM0,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD -0xb0(%RBP),%ZMM3,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD -0xb0(%RBP),%ZMM2,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM13,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM20,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM12,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM24,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM10,%ZMM5,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM11,%ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSCATTERDPD %ZMM11,(%R12,%YMM19,8){%K6}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VSCATTERDPD %ZMM10,(%R12,%YMM7,8){%K7}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VMOVAPD -0x630(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x670(%RBP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x5f0(%RBP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x6b0(%RBP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM2,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD -0x6f0(%RBP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM11,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM11,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM17,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM15,%ZMM16,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM2,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM3,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM9,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0x7f0(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM5,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM17,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x730(%RBP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM1,%ZMM31,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM0,%ZMM31,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM25,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD -0x770(%RBP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM30,%ZMM29,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM14,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM5,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM1,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM25,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM30,%ZMM29,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM21,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD -0x7b0(%RBP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM22,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM3,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM6,%ZMM2,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM27,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM17,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM17,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM16,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM10,%ZMM9,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM14,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM20,%ZMM0,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM6,%ZMM13,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM10,%ZMM11,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM12,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM15,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSCATTERDPD %ZMM8,(%R11,%YMM19,8){%K2}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
VSCATTERDPD %ZMM12,(%R11,%YMM7,8){%K3}	48	0	0	0	0	0	0	2	2	2	2	0	2.17	3.17	1.67	9	9	4-35	9	vect (100.0%)
CMP %R14,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 428540 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code