OV - exec - Loop 2876

	Loop Id: 2876	Module: exec	Source: :0-0	Coverage: 0.08%

0x5af130 VMOVAPD	(%R9,%R13,1),%ZMM15    [2]

0x5af137 VMOVAPD	(%RDI,%R13,1),%ZMM0    [3]

0x5af13e VMOVAPD	(%R10,%R13,1),%ZMM11    [1]

0x5af145 VSUBPD	%ZMM9,%ZMM15,%ZMM12

0x5af14b VSUBPD	%ZMM8,%ZMM0,%ZMM7

0x5af151 VSUBPD	%ZMM14,%ZMM11,%ZMM10

0x5af157 VMULPD	0x130(%RBX){1to8},%ZMM12,%ZMM0    [6]

0x5af15e VMULPD	0x118(%RBX){1to8},%ZMM12,%ZMM11    [6]

0x5af165 VMULPD	0x148(%RBX){1to8},%ZMM12,%ZMM3    [6]

0x5af16c VFMADD231PD	0x128(%RBX){1to8},%ZMM10,%ZMM0    [6]

0x5af173 VMOVAPD	%ZMM11,%ZMM13

0x5af179 VMOVAPD	%ZMM6,%ZMM11

0x5af17f VFMADD231PD	0x110(%RBX){1to8},%ZMM10,%ZMM13    [6]

0x5af186 VFMADD132PD	0x140(%RBX){1to8},%ZMM3,%ZMM10    [6]

0x5af18d VFMADD231PD	0x138(%RBX){1to8},%ZMM7,%ZMM0    [6]

0x5af194 VFMADD231PD	0x120(%RBX){1to8},%ZMM7,%ZMM13    [6]

0x5af19b VFMADD132PD	0x150(%RBX){1to8},%ZMM10,%ZMM7    [6]

0x5af1a2 VMOVAPD	%ZMM6,%ZMM10

0x5af1a8 VPTERNLOGQ	$-0x8,%ZMM5,%ZMM0,%ZMM11

0x5af1af VADDPD	%ZMM11,%ZMM0,%ZMM3

0x5af1b5 VPTERNLOGQ	$-0x8,%ZMM5,%ZMM13,%ZMM10

0x5af1bc VADDPD	%ZMM10,%ZMM13,%ZMM15

0x5af1c2 VRNDSCALEPD	$0x3,%ZMM3,%ZMM10

0x5af1c9 VRNDSCALEPD	$0x3,%ZMM15,%ZMM12

0x5af1d0 VSUBPD	%ZMM10,%ZMM0,%ZMM15

0x5af1d6 VMOVAPD	%ZMM6,%ZMM0

0x5af1dc VPTERNLOGQ	$-0x8,%ZMM5,%ZMM7,%ZMM0

0x5af1e3 VMULPD	0xd0(%RBX){1to8},%ZMM15,%ZMM3    [6]

0x5af1ea VSUBPD	%ZMM12,%ZMM13,%ZMM13

0x5af1f0 VADDPD	%ZMM0,%ZMM7,%ZMM12

0x5af1f6 VRNDSCALEPD	$0x3,%ZMM12,%ZMM11

0x5af1fd VFMADD231PD	0xc8(%RBX){1to8},%ZMM13,%ZMM3    [6]

0x5af204 VSUBPD	%ZMM11,%ZMM7,%ZMM7

0x5af20a VFMADD231PD	0xd8(%RBX){1to8},%ZMM7,%ZMM3    [6]

0x5af211 VMOVAPD	%ZMM3,(%RCX,%R13,1)    [7]

0x5af218 VMULPD	0xe8(%RBX){1to8},%ZMM15,%ZMM10    [6]

0x5af21f VFMADD231PD	0xe0(%RBX){1to8},%ZMM13,%ZMM10    [6]

0x5af226 VFMADD231PD	0xf0(%RBX){1to8},%ZMM7,%ZMM10    [6]

0x5af22d VMOVAPD	%ZMM10,(%RDX,%R13,1)    [8]

0x5af234 VMULPD	0x100(%RBX){1to8},%ZMM15,%ZMM15    [6]

0x5af23b VFMADD231PD	0xf8(%RBX){1to8},%ZMM13,%ZMM15    [6]

0x5af242 VFMADD132PD	0x108(%RBX){1to8},%ZMM15,%ZMM7    [6]

0x5af249 VMOVAPD	%ZMM7,(%RSI,%R13,1)    [4]

0x5af250 VMOVAPD	(%RDX,%R13,1),%ZMM0    [8]

0x5af257 VMOVAPD	(%RCX,%R13,1),%ZMM13    [7]

0x5af25e VMULPD	%ZMM0,%ZMM0,%ZMM12

0x5af264 VFMADD132PD	%ZMM13,%ZMM12,%ZMM13

0x5af26a VFMADD132PD	%ZMM7,%ZMM13,%ZMM7

0x5af270 VSQRTPD	%ZMM7,%ZMM11

0x5af276 VMOVAPD	%ZMM11,(%R12,%R13,1)    [5]

0x5af27d ADD	$0x40,%R13

0x5af281 CMP	%R11,%R13

0x5af284 JNE	5af130

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.55+	qmcplusplus::ParticleSet::make[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	7.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	56.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	32.73
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.45
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	7.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	56.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	32.73
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.45
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 4 occurrences►

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	56
loop length	346
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

16% of peak load performance is reached (42.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5af130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%R9,%R13,1),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%RDI,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%R10,%R13,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM15,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM0,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM14,%ZMM11,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD 0x130(%RBX){1to8},%ZMM12,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x118(%RBX){1to8},%ZMM12,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x148(%RBX){1to8},%ZMM12,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x128(%RBX){1to8},%ZMM10,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM11,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD 0x110(%RBX){1to8},%ZMM10,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x140(%RBX){1to8},%ZMM3,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x138(%RBX){1to8},%ZMM7,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x120(%RBX){1to8},%ZMM7,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x150(%RBX){1to8},%ZMM10,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM5,%ZMM0,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM11,%ZMM0,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM5,%ZMM13,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM10,%ZMM13,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM15,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM0,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM5,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMULPD 0xd0(%RBX){1to8},%ZMM15,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM7,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM12,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0xc8(%RBX){1to8},%ZMM13,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD 0xd8(%RBX){1to8},%ZMM7,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM3,(%RCX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0xe8(%RBX){1to8},%ZMM15,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0xe0(%RBX){1to8},%ZMM13,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0xf0(%RBX){1to8},%ZMM7,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,(%RDX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0x100(%RBX){1to8},%ZMM15,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0xf8(%RBX){1to8},%ZMM13,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x108(%RBX){1to8},%ZMM15,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM7,(%RSI,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPD (%RDX,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%RCX,%R13,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM13,%ZMM12,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM7,%ZMM13,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM7,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVAPD %ZMM11,(%R12,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
ADD $0x40,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5af130 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x940>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 4 occurrences►

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	56
loop length	346
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

16% of peak load performance is reached (42.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5af130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%R9,%R13,1),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%RDI,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%R10,%R13,1),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM15,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM0,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM14,%ZMM11,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD 0x130(%RBX){1to8},%ZMM12,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x118(%RBX){1to8},%ZMM12,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x148(%RBX){1to8},%ZMM12,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x128(%RBX){1to8},%ZMM10,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM11,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD 0x110(%RBX){1to8},%ZMM10,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x140(%RBX){1to8},%ZMM3,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x138(%RBX){1to8},%ZMM7,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x120(%RBX){1to8},%ZMM7,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x150(%RBX){1to8},%ZMM10,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM5,%ZMM0,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM11,%ZMM0,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM5,%ZMM13,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM10,%ZMM13,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM15,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM0,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM5,%ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VMULPD 0xd0(%RBX){1to8},%ZMM15,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM7,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM12,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0xc8(%RBX){1to8},%ZMM13,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM11,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD 0xd8(%RBX){1to8},%ZMM7,%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM3,(%RCX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0xe8(%RBX){1to8},%ZMM15,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0xe0(%RBX){1to8},%ZMM13,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0xf0(%RBX){1to8},%ZMM7,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,(%RDX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0x100(%RBX){1to8},%ZMM15,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0xf8(%RBX){1to8},%ZMM13,%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x108(%RBX){1to8},%ZMM15,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM7,(%RSI,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPD (%RDX,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%RCX,%R13,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM13,%ZMM12,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM7,%ZMM13,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM7,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVAPD %ZMM11,(%R12,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
ADD $0x40,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5af130 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x940>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code