OV - exec - Loop 2639

	Loop Id: 2639	Module: exec	Source: :0-0	Coverage: 0.29%

0x58af80 VMOVAPD	(%RDI,%R13,1),%ZMM0    [6]

0x58af87 VMOVAPD	(%R9,%R13,1),%ZMM4    [1]

0x58af8e VMOVAPD	(%RSI,%R13,1),%ZMM13    [4]

0x58af95 VSUBPD	%ZMM10,%ZMM0,%ZMM5

0x58af9b VSUBPD	%ZMM15,%ZMM4,%ZMM12

0x58afa1 VSUBPD	%ZMM14,%ZMM13,%ZMM8

0x58afa7 VMULPD	0x168(%RBX){1to8},%ZMM5,%ZMM1    [7]

0x58afae VMULPD	0x180(%RBX){1to8},%ZMM5,%ZMM7    [7]

0x58afb5 VMULPD	0x198(%RBX){1to8},%ZMM5,%ZMM4    [7]

0x58afbc VFMADD231PD	0x160(%RBX){1to8},%ZMM12,%ZMM1    [7]

0x58afc3 VFMADD231PD	0x178(%RBX){1to8},%ZMM12,%ZMM7    [7]

0x58afca VFMADD231PD	0x190(%RBX){1to8},%ZMM12,%ZMM4    [7]

0x58afd1 VMOVAPD	%ZMM6,%ZMM12

0x58afd7 VFMADD231PD	0x170(%RBX){1to8},%ZMM8,%ZMM1    [7]

0x58afde VFMADD231PD	0x188(%RBX){1to8},%ZMM8,%ZMM7    [7]

0x58afe5 VFMADD132PD	0x1a0(%RBX){1to8},%ZMM4,%ZMM8    [7]

0x58afec VPTERNLOGQ	$-0x8,%ZMM9,%ZMM1,%ZMM12

0x58aff3 VADDPD	%ZMM12,%ZMM1,%ZMM0

0x58aff9 VRNDSCALEPD	$0x3,%ZMM0,%ZMM5

0x58b000 VMOVAPD	%ZMM6,%ZMM0

0x58b006 VPTERNLOGQ	$-0x8,%ZMM9,%ZMM8,%ZMM0

0x58b00d VSUBPD	%ZMM5,%ZMM1,%ZMM13

0x58b013 VMOVAPD	%ZMM6,%ZMM1

0x58b019 VADDPD	%ZMM0,%ZMM8,%ZMM5

0x58b01f VPTERNLOGQ	$-0x8,%ZMM9,%ZMM7,%ZMM1

0x58b026 VADDPD	%ZMM1,%ZMM7,%ZMM4

0x58b02c VRNDSCALEPD	$0x3,%ZMM5,%ZMM1

0x58b033 VRNDSCALEPD	$0x3,%ZMM4,%ZMM12

0x58b03a VSUBPD	%ZMM1,%ZMM8,%ZMM8

0x58b040 VSUBPD	%ZMM12,%ZMM7,%ZMM7

0x58b046 VMULPD	0x120(%RBX){1to8},%ZMM7,%ZMM4    [7]

0x58b04d VFMADD231PD	0x118(%RBX){1to8},%ZMM13,%ZMM4    [7]

0x58b054 VFMADD231PD	0x128(%RBX){1to8},%ZMM8,%ZMM4    [7]

0x58b05b VMOVAPD	%ZMM4,(%R12,%R13,1)    [3]

0x58b062 VMULPD	0x138(%RBX){1to8},%ZMM7,%ZMM12    [7]

0x58b069 VFMADD231PD	0x130(%RBX){1to8},%ZMM13,%ZMM12    [7]

0x58b070 VFMADD231PD	0x140(%RBX){1to8},%ZMM8,%ZMM12    [7]

0x58b077 VMOVAPD	%ZMM12,(%RDX,%R13,1)    [8]

0x58b07e VMULPD	0x150(%RBX){1to8},%ZMM7,%ZMM7    [7]

0x58b085 VFMADD132PD	0x148(%RBX){1to8},%ZMM7,%ZMM13    [7]

0x58b08c VFMADD132PD	0x158(%RBX){1to8},%ZMM13,%ZMM8    [7]

0x58b093 VMOVAPD	%ZMM8,(%RCX,%R13,1)    [2]

0x58b09a VMOVAPD	(%RDX,%R13,1),%ZMM0    [8]

0x58b0a1 VMOVAPD	(%R12,%R13,1),%ZMM13    [3]

0x58b0a8 VMULPD	%ZMM0,%ZMM0,%ZMM5

0x58b0ae VFMADD132PD	%ZMM13,%ZMM5,%ZMM13

0x58b0b4 VFMADD132PD	%ZMM8,%ZMM13,%ZMM8

0x58b0ba VSQRTPD	%ZMM8,%ZMM1

0x58b0c0 VMOVAPD	%ZMM1,(%R14,%R13,1)    [5]

0x58b0c7 ADD	$0x40,%R13

0x58b0cb CMP	%R11,%R13

0x58b0ce JNE	58af80

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►96.66+	qmcplusplus::ParticleSet::make[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	6.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	55.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	32.73
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.45
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	11.00
Front-end cycles	6.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	7.50
P13 cycles	7.50
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	55.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	32.73
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.45
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 4 occurrences►

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	52
nb uops	55
loop length	340
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.88
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

16% of peak load performance is reached (42.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 58af80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%RDI,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%R9,%R13,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%RSI,%R13,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM0,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM15,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM14,%ZMM13,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD 0x168(%RBX){1to8},%ZMM5,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x180(%RBX){1to8},%ZMM5,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x198(%RBX){1to8},%ZMM5,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x160(%RBX){1to8},%ZMM12,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x178(%RBX){1to8},%ZMM12,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x190(%RBX){1to8},%ZMM12,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD 0x170(%RBX){1to8},%ZMM8,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x188(%RBX){1to8},%ZMM8,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x1a0(%RBX){1to8},%ZMM4,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM9,%ZMM1,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM12,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM0,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM9,%ZMM8,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VSUBPD %ZMM5,%ZMM1,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM0,%ZMM8,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM9,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM1,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM5,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM1,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD 0x120(%RBX){1to8},%ZMM7,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x118(%RBX){1to8},%ZMM13,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x128(%RBX){1to8},%ZMM8,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM4,(%R12,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0x138(%RBX){1to8},%ZMM7,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x130(%RBX){1to8},%ZMM13,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x140(%RBX){1to8},%ZMM8,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM12,(%RDX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0x150(%RBX){1to8},%ZMM7,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x148(%RBX){1to8},%ZMM7,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x158(%RBX){1to8},%ZMM13,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM8,(%RCX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPD (%RDX,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%R12,%R13,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM13,%ZMM5,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM8,%ZMM13,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVAPD %ZMM1,(%R14,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
ADD $0x40,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 58af80 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x9b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::SoaDistanceTableAAOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 4 occurrences►

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	52
nb uops	55
loop length	340
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	6.75	6.75	6.75	6.75	11.00	11.00	7.50	7.50	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.88
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

16% of peak load performance is reached (42.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 58af80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPD (%RDI,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%R9,%R13,1),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%RSI,%R13,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM0,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM15,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM14,%ZMM13,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD 0x168(%RBX){1to8},%ZMM5,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x180(%RBX){1to8},%ZMM5,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD 0x198(%RBX){1to8},%ZMM5,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x160(%RBX){1to8},%ZMM12,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x178(%RBX){1to8},%ZMM12,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x190(%RBX){1to8},%ZMM12,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD 0x170(%RBX){1to8},%ZMM8,%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x188(%RBX){1to8},%ZMM8,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x1a0(%RBX){1to8},%ZMM4,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM9,%ZMM1,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM12,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM0,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM9,%ZMM8,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VSUBPD %ZMM5,%ZMM1,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM0,%ZMM8,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM9,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM1,%ZMM7,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM5,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VRNDSCALEPD $0x3,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM1,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD 0x120(%RBX){1to8},%ZMM7,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x118(%RBX){1to8},%ZMM13,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x128(%RBX){1to8},%ZMM8,%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM4,(%R12,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0x138(%RBX){1to8},%ZMM7,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD 0x130(%RBX){1to8},%ZMM13,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD 0x140(%RBX){1to8},%ZMM8,%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM12,(%RDX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMULPD 0x150(%RBX){1to8},%ZMM7,%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x148(%RBX){1to8},%ZMM7,%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD 0x158(%RBX){1to8},%ZMM13,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM8,(%RCX,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPD (%RDX,%R13,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD (%R12,%R13,1),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM0,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM13,%ZMM5,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM8,%ZMM13,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVAPD %ZMM1,(%R14,%R13,1)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
ADD $0x40,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 58af80 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x9b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code