OV - exec - Loop 1144

	Loop Id: 1144	Module: exec	Source: :0-0	Coverage: 0.06%

0x4ab14b VMOVUPD	(%R11),%ZMM29    [2]

0x4ab151 VMOVUPD	0x40(%R11),%ZMM30    [2]

0x4ab158 VMOVUPD	0x80(%R11),%ZMM31    [2]

0x4ab15f VMOVUPD	(%R14),%ZMM28    [4]

0x4ab165 VMOVUPD	0xc0(%R11),%ZMM23    [2]

0x4ab16c VMOVUPD	0x100(%R11),%ZMM22    [2]

0x4ab173 VMOVUPD	0x140(%R11),%ZMM21    [2]

0x4ab17a VMOVUPD	0x40(%R14),%ZMM26    [4]

0x4ab181 VMOVUPD	0x180(%R11),%ZMM0    [2]

0x4ab188 VMOVUPD	0x200(%R11),%ZMM20    [2]

0x4ab18f VMOVUPD	0x80(%R14),%ZMM27    [4]

0x4ab196 ADD	$0x100,%R14

0x4ab19d ADD	$0x300,%R11

0x4ab1a4 VMOVAPD	%ZMM29,%ZMM17

0x4ab1aa VMOVAPD	%ZMM29,%ZMM18

0x4ab1b0 VPERMT2PD	%ZMM30,%ZMM4,%ZMM29

0x4ab1b6 VPERMT2PD	%ZMM31,%ZMM3,%ZMM29

0x4ab1bc VPERMT2PD	%ZMM30,%ZMM8,%ZMM17

0x4ab1c2 VPERMT2PD	%ZMM30,%ZMM6,%ZMM18

0x4ab1c8 VMOVAPD	%ZMM23,%ZMM19

0x4ab1ce VFMADD231PD	%ZMM28,%ZMM29,%ZMM9

0x4ab1d4 VPERMT2PD	%ZMM31,%ZMM7,%ZMM17

0x4ab1da VPERMT2PD	%ZMM31,%ZMM5,%ZMM18

0x4ab1e0 VPERMT2PD	%ZMM22,%ZMM8,%ZMM19

0x4ab1e6 VFMADD231PD	%ZMM28,%ZMM17,%ZMM10

0x4ab1ec VFMADD132PD	%ZMM28,%ZMM2,%ZMM18

0x4ab1f2 VMOVUPD	-0x140(%R11),%ZMM28    [1]

0x4ab1f9 VMOVAPD	%ZMM23,%ZMM2

0x4ab1ff VPERMT2PD	%ZMM22,%ZMM4,%ZMM23

0x4ab205 VPERMT2PD	%ZMM22,%ZMM6,%ZMM2

0x4ab20b VPERMT2PD	%ZMM21,%ZMM7,%ZMM19

0x4ab211 VMOVUPD	-0x40(%R14),%ZMM17    [3]

0x4ab218 VPERMT2PD	%ZMM21,%ZMM3,%ZMM23

0x4ab21e VPERMT2PD	%ZMM21,%ZMM5,%ZMM2

0x4ab224 VMOVAPD	%ZMM0,%ZMM29

0x4ab22a VFMADD132PD	%ZMM26,%ZMM9,%ZMM23

0x4ab230 VMOVUPD	-0xc0(%R11),%ZMM9    [1]

0x4ab237 VMOVAPD	%ZMM0,%ZMM1

0x4ab23d VFMADD132PD	%ZMM26,%ZMM18,%ZMM2

0x4ab243 VMOVUPD	-0x80(%R11),%ZMM18    [1]

0x4ab24a VFMADD132PD	%ZMM26,%ZMM10,%ZMM19

0x4ab250 VMOVUPD	-0x40(%R11),%ZMM26    [1]

0x4ab257 VPERMT2PD	%ZMM28,%ZMM8,%ZMM29

0x4ab25d VPERMT2PD	%ZMM28,%ZMM6,%ZMM1

0x4ab263 VPERMT2PD	%ZMM28,%ZMM4,%ZMM0

0x4ab269 VPERMT2PD	%ZMM20,%ZMM7,%ZMM29

0x4ab26f VPERMT2PD	%ZMM20,%ZMM5,%ZMM1

0x4ab275 VPERMT2PD	%ZMM20,%ZMM3,%ZMM0

0x4ab27b VFMADD132PD	%ZMM27,%ZMM2,%ZMM1

0x4ab281 VFMADD132PD	%ZMM27,%ZMM23,%ZMM0

0x4ab287 VFMADD132PD	%ZMM27,%ZMM19,%ZMM29

0x4ab28d VMOVAPD	%ZMM9,%ZMM10

0x4ab293 VMOVAPD	%ZMM9,%ZMM2

0x4ab299 VPERMT2PD	%ZMM18,%ZMM8,%ZMM10

0x4ab29f VPERMT2PD	%ZMM18,%ZMM6,%ZMM2

0x4ab2a5 VPERMT2PD	%ZMM18,%ZMM4,%ZMM9

0x4ab2ab VPERMT2PD	%ZMM26,%ZMM7,%ZMM10

0x4ab2b1 VPERMT2PD	%ZMM26,%ZMM5,%ZMM2

0x4ab2b7 VPERMT2PD	%ZMM26,%ZMM3,%ZMM9

0x4ab2bd VFMADD132PD	%ZMM17,%ZMM0,%ZMM9

0x4ab2c3 VFMADD132PD	%ZMM17,%ZMM1,%ZMM2

0x4ab2c9 VFMADD132PD	%ZMM17,%ZMM29,%ZMM10

0x4ab2cf CMP	%R14,%RDI

0x4ab2d2 JNE	4ab14b

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►64.11+	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.0		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►33.21+	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.0		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.77+	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.0		exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	7.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	7.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 96 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	63
loop length	397
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	24
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	7.88
Dispatch	12.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

25% of peak load performance is reached (64.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ab14b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11),%ZMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R11),%ZMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R11),%ZMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R14),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%R11),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x100(%R11),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x140(%R11),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R14),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x180(%R11),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x200(%R11),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R14),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
ADD $0x100,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x300,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %ZMM29,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM29,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM4,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM31,%ZMM3,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM8,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM6,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM29,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VPERMT2PD %ZMM31,%ZMM7,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM31,%ZMM5,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM8,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM17,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM28,%ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0x140(%R11),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM21,%ZMM7,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VMOVUPD -0x40(%R14),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM21,%ZMM3,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM21,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0xc0(%R11),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM18,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0x80(%R11),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0x40(%R11),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM28,%ZMM8,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM28,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM28,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM7,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM5,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VFMADD132PD %ZMM27,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM27,%ZMM23,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM27,%ZMM19,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM9,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM8,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM7,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM3,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM29,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
CMP %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4ab14b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0xceb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 96 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 16 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 16 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	63
loop length	397
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	24
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.00	4.00	4.00	4.00	12.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	7.88
Dispatch	12.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

25% of peak load performance is reached (64.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ab14b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11),%ZMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R11),%ZMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R11),%ZMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R14),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%R11),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x100(%R11),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x140(%R11),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R14),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x180(%R11),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x200(%R11),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R14),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
ADD $0x100,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x300,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %ZMM29,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM29,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM4,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM31,%ZMM3,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM8,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM6,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM29,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VPERMT2PD %ZMM31,%ZMM7,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM31,%ZMM5,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM8,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM17,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM28,%ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0x140(%R11),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM21,%ZMM7,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VMOVUPD -0x40(%R14),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM21,%ZMM3,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM21,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0xc0(%R11),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM18,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0x80(%R11),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD %ZMM26,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVUPD -0x40(%R11),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM28,%ZMM8,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM28,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM28,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM7,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM5,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VFMADD132PD %ZMM27,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM27,%ZMM23,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM27,%ZMM19,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM9,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM8,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM4,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM7,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM3,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
VFMADD132PD %ZMM17,%ZMM29,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (100.0%)
CMP %R14,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4ab14b <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0xceb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code