OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.28% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4922a0 PUSH	%R15

0x4922a2 PUSH	%R14

0x4922a4 PUSH	%R13

0x4922a6 PUSH	%R12

0x4922a8 PUSH	%RBP

0x4922a9 PUSH	%RBX

0x4922aa MOV	%RSI,%RBP

0x4922ad MOV	%RDI,%RBX

0x4922b0 SUB	$0x48,%RSP

0x4922b4 MOV	0x358(%RDI),%R12

0x4922bb MOVSXD	%EDX,%R15

0x4922be MOV	%RCX,0x28(%RSP)

0x4922c3 MOV	%R8,0x30(%RSP)

0x4922c8 MOV	%R9,0x38(%RSP)

0x4922cd MOV	%R12,%RDI

0x4922d0 CALL	544ee0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x4922d5 LEA	0x128(%RBP),%RCX

0x4922dc CMP	0x124(%RBP),%R15D

0x4922e3 JE	4922f1

0x4922e5 MOV	0x40(%RBP),%RAX

0x4922e9 LEA	(%R15,%R15,2),%RDX

0x4922ed LEA	(%RAX,%RDX,8),%RCX

0x4922f1 VMOVUPD	(%RCX),%XMM0

0x4922f5 VMOVSD	0x10(%RCX),%XMM1

0x4922fa VXORPD	%XMM9,%XMM9,%XMM9

0x4922ff VMOVDDUP	%XMM1,%XMM2

0x492303 VMOVDDUP	0x146815(%RIP),%XMM10

0x49230b VMULSD	0x118(%RBX),%XMM1,%XMM6

0x492313 VMOVSD	(%RCX),%XMM5

0x492317 VFMADD231SD	0xe8(%RBX),%XMM5,%XMM6

0x492320 VPERMILPD	$0x3,%XMM0,%XMM4

0x492326 VMULPD	0xf0(%RBX),%XMM4,%XMM8

0x49232e VPERMILPD	$0,%XMM0,%XMM3

0x492334 VUNPCKHPD	%XMM0,%XMM0,%XMM7

0x492338 VFMADD231PD	0xd8(%RBX),%XMM3,%XMM8

0x492341 VFMADD132PD	0x108(%RBX),%XMM8,%XMM2

0x49234a VCMPPD	$0x1,%XMM9,%XMM2,%K1

0x492351 VFMADD132SD	0x100(%RBX),%XMM6,%XMM7

0x49235a VRNDSCALEPD	$0x9,%XMM2,%XMM11

0x492361 VCMPPD	$0xe,%XMM10,%XMM2,%K0{%K1}

0x492368 KNOTB	%K0,%K2

0x49236c KMOVB	%K2,%ESI

0x492370 AND	$0x3,%ESI

0x492373 VCOMISD	0x1467a5(%RIP),%XMM7

0x49237b KMOVB	%ESI,%K3

0x49237f VSUBPD	%XMM11,%XMM2,%XMM12{%K3}{z}

0x492385 JBE	492396

0x492387 VXORPD	%XMM13,%XMM13,%XMM13

0x49238c VCOMISD	%XMM7,%XMM13

0x492390 JA	49277d

0x492396 VRNDSCALESD	$0x9,%XMM7,%XMM7,%XMM14

0x49239d VSUBSD	%XMM14,%XMM7,%XMM15

0x4923a2 MOV	0x30(%RBX),%R8D

0x4923a6 VMOVHPD	%XMM12,0x8(%RSP)

0x4923ac VMOVLPD	%XMM12,0x10(%RSP)

0x4923b2 XOR	%R13D,%R13D

0x4923b5 TEST	%R8D,%R8D

0x4923b8 JLE	492491

0x4923be VMOVSD	%XMM15,0x18(%RSP)

(1031) 0x4923c4 MOV	0x310(%RBX),%R14

(1031) 0x4923cb MOV	0x340(%RBX),%R9

(1031) 0x4923d2 MOV	0x328(%RBX),%R10

(1031) 0x4923d9 MOV	0x2f8(%RBX),%R15

(1031) 0x4923e0 LEA	(%R13,%R13,4),%RDI

(1031) 0x4923e5 LEA	(%R13,%R13,2),%R11

(1031) 0x4923ea MOVSXD	0x40(%RBX),%R8

(1031) 0x4923ee VMOVSD	0x18(%RSP),%XMM2

(1031) 0x4923f4 VMOVSD	0x8(%RSP),%XMM1

(1031) 0x4923fa VMOVSD	0x10(%RSP),%XMM0

(1031) 0x492400 SAL	$0x3,%RDI

(1031) 0x492404 LEA	(%R14,%R11,8),%RBP

(1031) 0x492408 MOV	0x18(%R9,%RDI,1),%RCX

(1031) 0x49240d MOV	0x18(%R10,%RDI,1),%RDX

(1031) 0x492412 MOV	(%R15,%R13,8),%RDI

(1031) 0x492416 MOV	(%RBP),%RSI

(1031) 0x49241a CALL	4915e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m>

(1031) 0x49241f LEA	0x1(%R13),%RAX

(1031) 0x492423 CMP	%EAX,0x30(%RBX)

(1031) 0x492426 JLE	492491

(1031) 0x492428 MOV	0x328(%RBX),%RSI

(1031) 0x49242f MOV	0x310(%RBX),%RDI

(1031) 0x492436 MOV	0x340(%RBX),%RCX

(1031) 0x49243d LEA	(%RAX,%RAX,4),%RDX

(1031) 0x492441 MOV	0x2f8(%RBX),%R11

(1031) 0x492448 LEA	(%RAX,%RAX,2),%R8

(1031) 0x49244c VMOVSD	0x18(%RSP),%XMM2

(1031) 0x492452 VMOVSD	0x8(%RSP),%XMM1

(1031) 0x492458 VMOVSD	0x10(%RSP),%XMM0

(1031) 0x49245e ADD	$0x2,%R13

(1031) 0x492462 SAL	$0x3,%RDX

(1031) 0x492466 LEA	(%RDI,%R8,8),%R10

(1031) 0x49246a MOV	0x18(%RSI,%RDX,1),%R9

(1031) 0x49246f MOV	0x18(%RCX,%RDX,1),%RCX

(1031) 0x492474 MOVSXD	0x40(%RBX),%R8

(1031) 0x492478 MOV	(%R10),%RSI

(1031) 0x49247b MOV	(%R11,%RAX,8),%RDI

(1031) 0x49247f MOV	%R9,%RDX

(1031) 0x492482 CALL	4915e0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m>

(1031) 0x492487 CMP	%R13D,0x30(%RBX)

(1031) 0x49248b JG	4923c4

0x492491 MOV	%R12,%RDI

0x492494 CALL	545120 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x492499 MOV	0x30(%RBX),%R12D

0x49249d MOV	%R12D,0x18(%RSP)

0x4924a2 TEST	%R12D,%R12D

0x4924a5 JLE	49276e

0x4924ab MOVSXD	0x18(%RSP),%R13

0x4924b0 VMOVD	0x40(%RBX),%XMM4

0x4924b5 VMOVD	0x8(%RBX),%XMM3

0x4924ba XOR	%R9D,%R9D

0x4924bd VMOVDQA	%XMM4,%XMM7

0x4924c1 XOR	%R11D,%R11D

0x4924c4 XOR	%R8D,%R8D

0x4924c7 MOVQ	$0,0x10(%RSP)

0x4924d0 MOVL	$0,0x8(%RSP)

0x4924d8 LEA	(,%R13,8),%R14

0x4924e0 LEA	(%R13,%R13,2),%RBP

0x4924e5 LEA	(,%RBP,8),%R15

0x4924ed VMOVQ	%R14,%XMM1

0x4924f2 MOV	%R15,0x20(%RSP)

0x4924f7 NOPW	(%RAX,%RAX,1)

(1029) 0x492500 VPMINSD	%XMM3,%XMM7,%XMM0

(1029) 0x492505 VMOVD	%XMM0,%ESI

(1029) 0x492509 CMP	%ESI,0x8(%RSP)

(1029) 0x49250d JGE	49273f

(1029) 0x492513 MOV	0x340(%RBX),%RDI

(1029) 0x49251a MOV	0x328(%RBX),%RDX

(1029) 0x492521 MOV	0x8(%RSP),%EBP

(1029) 0x492525 MOV	0x28(%RSP),%R15

(1029) 0x49252a MOV	0x30(%RSP),%R14

(1029) 0x49252f MOV	0x310(%RBX),%RAX

(1029) 0x492536 MOV	0x18(%RDI,%R9,1),%R13

(1029) 0x49253b MOV	0x38(%RSP),%RDI

(1029) 0x492540 ADD	%R9,%RDX

(1029) 0x492543 SUB	%EBP,%ESI

(1029) 0x492545 MOV	0x18(%RDX),%R12

(1029) 0x492549 MOVSXD	0x8(%RDX),%RCX

(1029) 0x49254d MOV	0x18(%R15),%RBP

(1029) 0x492551 MOV	0x10(%RSP),%RDX

(1029) 0x492556 ADD	0x18(%R14),%RDX

(1029) 0x49255a MOV	(%RAX,%R11,1),%R10

(1029) 0x49255e XOR	%EAX,%EAX

(1029) 0x492560 SAL	$0x3,%RSI

(1029) 0x492564 MOV	0x18(%RDI),%R15

(1029) 0x492568 LEA	-0x8(%RSI),%RDI

(1029) 0x49256c LEA	(%R12,%RCX,8),%R14

(1029) 0x492570 ADD	%R8,%RBP

(1029) 0x492573 SHR	$0x3,%RDI

(1029) 0x492577 SAL	$0x4,%RCX

(1029) 0x49257b INC	%RDI

(1029) 0x49257e ADD	%R12,%RCX

(1029) 0x492581 ADD	%R8,%R15

(1029) 0x492584 AND	$0x3,%EDI

(1029) 0x492587 JE	492650

(1029) 0x49258d CMP	$0x1,%RDI

(1029) 0x492591 JE	49260c

(1029) 0x492593 CMP	$0x2,%RDI

(1029) 0x492597 JE	4925d0

(1029) 0x492599 VMOVSD	(%R10),%XMM2

(1029) 0x49259e VMOVSD	%XMM2,(%RBP)

(1029) 0x4925a3 VMOVSD	(%R12),%XMM6

(1029) 0x4925a9 VMOVHPD	(%R14),%XMM6,%XMM8

(1029) 0x4925ae VMOVSD	(%RCX),%XMM5

(1029) 0x4925b2 ADD	$0x18,%RDX

(1029) 0x4925b6 MOV	$0x8,%EAX

(1029) 0x4925bb VMOVUPD	%XMM8,-0x18(%RDX)

(1029) 0x4925c0 VMOVSD	%XMM5,-0x8(%RDX)

(1029) 0x4925c5 VMOVSD	(%R13),%XMM9

(1029) 0x4925cb VMOVSD	%XMM9,(%R15)

(1029) 0x4925d0 VMOVSD	(%R10,%RAX,1),%XMM10

(1029) 0x4925d6 VMOVSD	%XMM10,(%RBP,%RAX,1)

(1029) 0x4925dc VMOVSD	(%R12,%RAX,1),%XMM12

(1029) 0x4925e2 VMOVHPD	(%R14,%RAX,1),%XMM12,%XMM13

(1029) 0x4925e8 VMOVSD	(%RCX,%RAX,1),%XMM11

(1029) 0x4925ed ADD	$0x18,%RDX

(1029) 0x4925f1 VMOVUPD	%XMM13,-0x18(%RDX)

(1029) 0x4925f6 VMOVSD	%XMM11,-0x8(%RDX)

(1029) 0x4925fb VMOVSD	(%R13,%RAX,1),%XMM14

(1029) 0x492602 VMOVSD	%XMM14,(%R15,%RAX,1)

(1029) 0x492608 ADD	$0x8,%RAX

(1029) 0x49260c VMOVSD	(%R10,%RAX,1),%XMM15

(1029) 0x492612 VMOVSD	%XMM15,(%RBP,%RAX,1)

(1029) 0x492618 VMOVSD	(%R12,%RAX,1),%XMM2

(1029) 0x49261e VMOVHPD	(%R14,%RAX,1),%XMM2,%XMM5

(1029) 0x492624 VMOVSD	(%RCX,%RAX,1),%XMM0

(1029) 0x492629 VMOVUPD	%XMM5,(%RDX)

(1029) 0x49262d VMOVSD	%XMM0,0x10(%RDX)

(1029) 0x492632 VMOVSD	(%R13,%RAX,1),%XMM6

(1029) 0x492639 VMOVSD	%XMM6,(%R15,%RAX,1)

(1029) 0x49263f ADD	$0x8,%RAX

(1029) 0x492643 ADD	$0x18,%RDX

(1029) 0x492647 CMP	%RSI,%RAX

(1029) 0x49264a JE	49273f

  (1030) 0x492650 VMOVSD	(%R10,%RAX,1),%XMM8

  (1030) 0x492656 VMOVSD	%XMM8,(%RBP,%RAX,1)

  (1030) 0x49265c VMOVSD	(%R12,%RAX,1),%XMM10

  (1030) 0x492662 VMOVHPD	(%R14,%RAX,1),%XMM10,%XMM11

  (1030) 0x492668 VMOVSD	(%RCX,%RAX,1),%XMM9

  (1030) 0x49266d VMOVUPD	%XMM11,(%RDX)

  (1030) 0x492671 VMOVSD	%XMM9,0x10(%RDX)

  (1030) 0x492676 VMOVSD	(%R13,%RAX,1),%XMM12

  (1030) 0x49267d VMOVSD	%XMM12,(%R15,%RAX,1)

  (1030) 0x492683 VMOVSD	0x8(%R10,%RAX,1),%XMM13

  (1030) 0x49268a VMOVSD	%XMM13,0x8(%RAX,%RBP,1)

  (1030) 0x492690 VMOVSD	0x8(%R12,%RAX,1),%XMM15

  (1030) 0x492697 VMOVHPD	0x8(%R14,%RAX,1),%XMM15,%XMM0

  (1030) 0x49269e VMOVSD	0x8(%RCX,%RAX,1),%XMM14

  (1030) 0x4926a4 VMOVSD	%XMM14,0x28(%RDX)

  (1030) 0x4926a9 ADD	$0x60,%RDX

  (1030) 0x4926ad VMOVUPD	%XMM0,-0x48(%RDX)

  (1030) 0x4926b2 VMOVSD	0x8(%R13,%RAX,1),%XMM2

  (1030) 0x4926b9 VMOVSD	%XMM2,0x8(%RAX,%R15,1)

  (1030) 0x4926c0 VMOVSD	0x10(%R10,%RAX,1),%XMM5

  (1030) 0x4926c7 VMOVSD	%XMM5,0x10(%RAX,%RBP,1)

  (1030) 0x4926cd VMOVSD	0x10(%R12,%RAX,1),%XMM6

  (1030) 0x4926d4 VMOVHPD	0x10(%R14,%RAX,1),%XMM6,%XMM9

  (1030) 0x4926db VMOVSD	0x10(%RCX,%RAX,1),%XMM8

  (1030) 0x4926e1 VMOVUPD	%XMM9,-0x30(%RDX)

  (1030) 0x4926e6 VMOVSD	%XMM8,-0x20(%RDX)

  (1030) 0x4926eb VMOVSD	0x10(%R13,%RAX,1),%XMM10

  (1030) 0x4926f2 VMOVSD	%XMM10,0x10(%RAX,%R15,1)

  (1030) 0x4926f9 VMOVSD	0x18(%R10,%RAX,1),%XMM11

  (1030) 0x492700 VMOVSD	%XMM11,0x18(%RAX,%RBP,1)

  (1030) 0x492706 VMOVSD	0x18(%R12,%RAX,1),%XMM13

  (1030) 0x49270d VMOVHPD	0x18(%R14,%RAX,1),%XMM13,%XMM14

  (1030) 0x492714 VMOVSD	0x18(%RCX,%RAX,1),%XMM12

  (1030) 0x49271a VMOVUPD	%XMM14,-0x18(%RDX)

  (1030) 0x49271f VMOVSD	%XMM12,-0x8(%RDX)

  (1030) 0x492724 VMOVSD	0x18(%R13,%RAX,1),%XMM15

  (1030) 0x49272b ADD	$0x20,%RAX

  (1030) 0x49272f VMOVSD	%XMM15,-0x8(%RAX,%R15,1)

  (1030) 0x492736 CMP	%RSI,%RAX

  (1030) 0x492739 JNE	492650

(1029) 0x49273f MOV	0x20(%RSP),%R12

(1029) 0x492744 MOV	0x18(%RSP),%ESI

(1029) 0x492748 VMOVQ	%XMM1,%R10

(1029) 0x49274d ADD	$0x18,%R11

(1029) 0x492751 VPADDD	%XMM4,%XMM7,%XMM7

(1029) 0x492755 ADD	%R10,%R8

(1029) 0x492758 ADD	$0x28,%R9

(1029) 0x49275c ADD	%ESI,0x8(%RSP)

(1029) 0x492760 ADD	%R12,0x10(%RSP)

(1029) 0x492765 CMP	%R11,%R12

(1029) 0x492768 JNE	492500

0x49276e ADD	$0x48,%RSP

0x492772 POP	%RBX

0x492773 POP	%RBP

0x492774 POP	%R12

0x492776 POP	%R13

0x492778 POP	%R14

0x49277a POP	%R15

0x49277c RET

0x49277d VMOVAPD	%XMM13,%XMM15

0x492782 JMP	4923a2

0x492787 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►60.49+	miniqmcreference::DiracDetermi[...]		exec
○	qmcplusplus::WaveFunction::rat[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►17.95+	miniqmcreference::DiracDetermi[...]		exec
○	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.0		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►17.93+	miniqmcreference::DiracDetermi[...]		exec
○	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.0		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.88 to 5.50 cycles (2.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.88 to 1.14 cycles (10.40x speedup).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVB: 1 occurrences►
VCOMISD: 2 occurrences►
VMOVHPD: 1 occurrences►

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 160 bytes (20 double precision FP elements). The binary function is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	95
loop length	437
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.88 cycles
front end	11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	7.75	7.75	7.75	7.75	5.50	5.50	5.50	5.50	3.00	3.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	7.75	7.75	7.75	7.75	5.50	5.50	5.50	5.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Dispatch	7.75
Overall L1	11.88

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	46%
load	36%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	61%

INT+FP

all	28%
load	23%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	17%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	14%
load	13%
store	10%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 11.88 cycles. At this rate:

5% of peak load performance is reached (13.47 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.88 to 7.75 cycles (1.53x speedup).

ASM code

In the binary file, the address of the function is: 4922a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD %EDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 544ee0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x128(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP 0x124(%RBP),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 4922f1 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R15,%R15,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RCX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RCX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDDUP %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP 0x146815(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0x118(%RBX),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0xe8(%RBX),%XMM5,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VPERMILPD $0x3,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULPD 0xf0(%RBX),%XMM4,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VPERMILPD $0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VUNPCKHPD %XMM0,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VFMADD231PD 0xd8(%RBX),%XMM3,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD132PD 0x108(%RBX),%XMM8,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VCMPPD $0x1,%XMM9,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VFMADD132SD 0x100(%RBX),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VRNDSCALEPD $0x9,%XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VCMPPD $0xe,%XMM10,%XMM2,%K0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
KNOTB %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K2,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VCOMISD 0x1467a5(%RIP),%XMM7	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
KMOVB %ESI,%K3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VSUBPD %XMM11,%XMM2,%XMM12{%K3}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
JBE 492396 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xf6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISD %XMM7,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 49277d <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x4dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x30(%RBX),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVHPD %XMM12,0x8(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VMOVLPD %XMM12,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 492491 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD %XMM15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 545120 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %R12D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %R12D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 49276e <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x4ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x18(%RSP),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVD 0x40(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	8	0.50	scal (6.3%)
VMOVD 0x8(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	8	0.50	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDQA %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVQ $0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (,%R13,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%R13,2),%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (,%RBP,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %R14,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R15,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVAPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4923a2 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x102>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.88 to 5.50 cycles (2.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVB: 1 occurrences►
VCOMISD: 2 occurrences►
VMOVHPD: 1 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 160 bytes (20 double precision FP elements). The binary function is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	95
loop length	437
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.88 cycles
front end	11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	7.75	7.75	7.75	7.75	5.50	5.50	5.50	5.50	3.00	3.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	7.75	7.75	7.75	7.75	5.50	5.50	5.50	5.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Dispatch	7.75
Overall L1	11.88

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	46%
load	36%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	61%

INT+FP

all	28%
load	23%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	17%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	14%
load	13%
store	10%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 11.88 cycles. At this rate:

5% of peak load performance is reached (13.47 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4922a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD %EDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 544ee0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x128(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP 0x124(%RBP),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 4922f1 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R15,%R15,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RCX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RCX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDDUP %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVDDUP 0x146815(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0x118(%RBX),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0xe8(%RBX),%XMM5,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VPERMILPD $0x3,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULPD 0xf0(%RBX),%XMM4,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VPERMILPD $0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VUNPCKHPD %XMM0,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VFMADD231PD 0xd8(%RBX),%XMM3,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD132PD 0x108(%RBX),%XMM8,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VCMPPD $0x1,%XMM9,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VFMADD132SD 0x100(%RBX),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VRNDSCALEPD $0x9,%XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VCMPPD $0xe,%XMM10,%XMM2,%K0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
KNOTB %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K2,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VCOMISD 0x1467a5(%RIP),%XMM7	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
KMOVB %ESI,%K3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VSUBPD %XMM11,%XMM2,%XMM12{%K3}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
JBE 492396 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xf6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISD %XMM7,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 49277d <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x4dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x30(%RBX),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVHPD %XMM12,0x8(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VMOVLPD %XMM12,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 492491 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1f1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD %XMM15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 545120 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %R12D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %R12D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 49276e <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x4ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x18(%RSP),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVD 0x40(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	8	0.50	scal (6.3%)
VMOVD 0x8(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	8	0.50	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDQA %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVQ $0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (,%R13,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%R13,2),%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (,%RBP,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %R14,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R15,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVAPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4923a2 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x102>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator >...–	0.28	0.47
○Loop 1031 - - exec	0.00	0.01
▼Loop 1029 - - exec–	0.00	0.01
○Loop 1030 - - exec	0.28	0.46

Report Configuration

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Masked instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Cycles and memory resources usage

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ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

Masked instructions

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FMA

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CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code