OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: :0-0	Coverage (incl. loops): 25.82% \| (excl. loops): 0.01%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4872c0 PUSH	%RBP

0x4872c1 MOV	%RSP,%RBP

0x4872c4 PUSH	%R15

0x4872c6 PUSH	%R14

0x4872c8 PUSH	%R13

0x4872ca PUSH	%R12

0x4872cc PUSH	%RBX

0x4872cd MOV	%RSI,%R14

0x4872d0 MOV	%RDI,%RBX

0x4872d3 AND	$-0x40,%RSP

0x4872d7 MOV	%RCX,%R13

0x4872da MOVSXD	%EDX,%R15

0x4872dd SUB	$0x100,%RSP

0x4872e4 MOV	0x358(%RDI),%R12

0x4872eb MOV	%R12,%RDI

0x4872ee CALL	544ee0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x4872f3 LEA	0x128(%R14),%RCX

0x4872fa CMP	0x124(%R14),%R15D

0x487301 JE	48730f

0x487303 MOV	0x40(%R14),%RAX

0x487307 LEA	(%R15,%R15,2),%RDX

0x48730b LEA	(%RAX,%RDX,8),%RCX

0x48730f VMOVUPD	(%RCX),%XMM0

0x487313 VMOVSD	0x10(%RCX),%XMM2

0x487318 VMOVDDUP	0x151800(%RIP),%XMM9

0x487320 VMOVDDUP	%XMM2,%XMM1

0x487324 VXORPD	%XMM10,%XMM10,%XMM10

0x487329 VMULSD	0x118(%RBX),%XMM2,%XMM5

0x487331 VMOVSD	(%RCX),%XMM6

0x487335 VXORPD	%XMM13,%XMM13,%XMM13

0x48733a VFMADD231SD	0xe8(%RBX),%XMM6,%XMM5

0x487343 VPERMILPD	$0x3,%XMM0,%XMM4

0x487349 VMULPD	0xf0(%RBX),%XMM4,%XMM8

0x487351 VPERMILPD	$0,%XMM0,%XMM3

0x487357 VUNPCKHPD	%XMM0,%XMM0,%XMM7

0x48735b VFMADD231PD	0xd8(%RBX),%XMM3,%XMM8

0x487364 VFMADD132PD	0x108(%RBX),%XMM8,%XMM1

0x48736d VCMPPD	$0xe,%XMM9,%XMM1,%K1

0x487374 VFMADD132SD	0x100(%RBX),%XMM5,%XMM7

0x48737d VRNDSCALEPD	$0x9,%XMM1,%XMM11

0x487384 VCMPPD	$0x1,%XMM10,%XMM1,%K0{%K1}

0x48738b KNOTB	%K0,%K2

0x48738f KMOVB	%K2,%ESI

0x487393 AND	$0x3,%ESI

0x487396 VCOMISD	%XMM7,%XMM13

0x48739a KMOVB	%ESI,%K3

0x48739e VSUBPD	%XMM11,%XMM1,%XMM12{%K3}{z}

0x4873a4 JBE	4873b4

0x4873a6 VCOMISD	0x151772(%RIP),%XMM7

0x4873ae JA	487de2

0x4873b4 VRNDSCALESD	$0x9,%XMM7,%XMM7,%XMM14

0x4873bb VSUBSD	%XMM14,%XMM7,%XMM15

0x4873c0 MOVSXD	0x30(%RBX),%RDI

0x4873c4 TEST	%EDI,%EDI

0x4873c6 JLE	487ca9

0x4873cc MOVSXD	0x40(%RBX),%R8

0x4873d0 MOV	0x2f8(%RBX),%R11

0x4873d7 MOV	0x310(%RBX),%R10

0x4873de VMOVHPD	%XMM12,0x20(%RSP)

0x4873e4 VMOVLPD	%XMM12,0x28(%RSP)

0x4873ea MOV	%R12,0x10(%RSP)

0x4873ef VMOVSD	%XMM15,0x18(%RSP)

0x4873f5 MOV	%RBX,0x8(%RSP)

0x4873fa MOV	%R13,(%RSP)

0x4873fe LEA	(,%R8,8),%R9

0x487406 LEA	(%R11,%RDI,8),%R14

0x48740a LEA	-0x1(%R8),%R15

0x48740e MOV	%R8D,0x54(%RSP)

0x487413 MOV	%R8,0xa8(%RSP)

0x48741b MOV	%R9,0x38(%RSP)

0x487420 MOV	%R10,0x40(%RSP)

0x487425 MOV	%R11,0x48(%RSP)

0x48742a MOV	%R14,0x30(%RSP)

0x48742f MOV	%R15,0x70(%RSP)

(958) 0x487434 MOV	0x48(%RSP),%R12

(958) 0x487439 MOV	0x40(%RSP),%RBX

(958) 0x48743e VMOVSD	0x20(%RSP),%XMM0

(958) 0x487444 VMOVSD	0x18(%RSP),%XMM3

(958) 0x48744a VMOVSD	0x28(%RSP),%XMM4

(958) 0x487450 VXORPD	%XMM6,%XMM6,%XMM6

(958) 0x487454 MOV	(%R12),%R8

(958) 0x487458 MOV	(%RBX),%R15

(958) 0x48745b VSUBSD	0x28(%R8),%XMM4,%XMM2

(958) 0x487461 VSUBSD	0x50(%R8),%XMM0,%XMM1

(958) 0x487467 VMULSD	0x48(%R8),%XMM2,%XMM5

(958) 0x48746d VSUBSD	0x78(%R8),%XMM3,%XMM7

(958) 0x487473 VCOMISD	%XMM5,%XMM6

(958) 0x487477 JA	487d6d

(958) 0x48747d MOV	0x38(%R8),%EAX

(958) 0x487481 VCVTTSD2SI	%XMM5,%R13D

(958) 0x487485 DEC	%EAX

(958) 0x487487 CMP	%R13D,%EAX

(958) 0x48748a JL	487d96

(958) 0x487490 VRNDSCALESD	$0xb,%XMM5,%XMM5,%XMM8

(958) 0x487497 VSUBSD	%XMM8,%XMM5,%XMM11

(958) 0x48749c VMOVAPD	%XMM11,%XMM0

(958) 0x4874a0 VMOVSD	0x151608(%RIP),%XMM13

(958) 0x4874a8 VFNMADD132SD	%XMM13,%XMM13,%XMM0

(958) 0x4874ad VMULSD	0x151673(%RIP),%XMM11,%XMM12

(958) 0x4874b5 VMOVAPD	%XMM11,%XMM15

(958) 0x4874ba VADDSD	%XMM13,%XMM12,%XMM14

(958) 0x4874bf VFMADD213SD	0x151668(%RIP),%XMM13,%XMM15

(958) 0x4874c8 VXORPD	0x14fbf0(%RIP),%XMM12,%XMM3

(958) 0x4874d0 VMULSD	%XMM11,%XMM11,%XMM9

(958) 0x4874d5 VFMADD213SD	0x1515c2(%RIP),%XMM11,%XMM14

(958) 0x4874de VMOVSD	0x15155a(%RIP),%XMM10

(958) 0x4874e6 VFMADD132SD	%XMM11,%XMM10,%XMM14

(958) 0x4874eb VFMADD213SD	0x151554(%RIP),%XMM9,%XMM15

(958) 0x4874f4 MOVSXD	%R13D,%RDX

(958) 0x4874f7 MOV	%RDX,0xb8(%RSP)

(958) 0x4874ff VFMADD231SD	%XMM0,%XMM11,%XMM13

(958) 0x487504 VUNPCKLPD	%XMM15,%XMM14,%XMM5

(958) 0x487509 VMULSD	%XMM9,%XMM3,%XMM4

(958) 0x48750e VFMADD132SD	%XMM13,%XMM10,%XMM11

(958) 0x487513 VUNPCKLPD	%XMM4,%XMM11,%XMM2

(958) 0x487517 VINSERTF64X2	$0x1,%XMM2,%YMM5,%YMM11

(958) 0x48751e VMULSD	0x70(%R8),%XMM1,%XMM1

(958) 0x487524 VXORPD	%XMM6,%XMM6,%XMM6

(958) 0x487528 VCOMISD	%XMM1,%XMM6

(958) 0x48752c JA	487d5d

(958) 0x487532 MOV	0x60(%R8),%ECX

(958) 0x487536 VCVTTSD2SI	%XMM1,%EDI

(958) 0x48753a LEA	-0x1(%RCX),%ESI

(958) 0x48753d CMP	%EDI,%ESI

(958) 0x48753f JL	487d86

(958) 0x487545 VRNDSCALESD	$0xb,%XMM1,%XMM1,%XMM8

(958) 0x48754c VSUBSD	%XMM8,%XMM1,%XMM12

(958) 0x487551 VMOVAPD	%XMM12,%XMM9

(958) 0x487556 VMOVSD	0x151552(%RIP),%XMM15

(958) 0x48755e VFNMADD132SD	%XMM15,%XMM15,%XMM9

(958) 0x487563 VMOVSD	0x1514d5(%RIP),%XMM14

(958) 0x48756b VMOVAPD	%XMM12,%XMM3

(958) 0x48756f VMULSD	%XMM14,%XMM12,%XMM10

(958) 0x487574 VFMADD213SD	0x1515b3(%RIP),%XMM15,%XMM3

(958) 0x48757d VSUBSD	%XMM10,%XMM15,%XMM0

(958) 0x487582 VMULSD	%XMM12,%XMM12,%XMM13

(958) 0x487587 VFMADD213SD	0x151510(%RIP),%XMM12,%XMM0

(958) 0x487590 VFMADD132SD	%XMM12,%XMM14,%XMM0

(958) 0x487595 VFMADD213SD	0x1514aa(%RIP),%XMM13,%XMM3

(958) 0x48759e VMULSD	%XMM13,%XMM10,%XMM4

(958) 0x4875a3 MOVSXD	%EDI,%R9

(958) 0x4875a6 VFMADD231SD	%XMM9,%XMM12,%XMM15

(958) 0x4875ab VUNPCKLPD	%XMM3,%XMM0,%XMM5

(958) 0x4875af VFMADD132SD	%XMM15,%XMM14,%XMM12

(958) 0x4875b4 VUNPCKLPD	%XMM4,%XMM12,%XMM2

(958) 0x4875b8 VINSERTF64X2	$0x1,%XMM2,%YMM5,%YMM1

(958) 0x4875bf VMULSD	0x98(%R8),%XMM7,%XMM7

(958) 0x4875c8 VXORPD	%XMM6,%XMM6,%XMM6

(958) 0x4875cc VCOMISD	%XMM7,%XMM6

(958) 0x4875d0 JA	487d38

(958) 0x4875d6 MOV	0x88(%R8),%R10D

(958) 0x4875dd VCVTTSD2SI	%XMM7,%R14D

(958) 0x4875e1 LEA	-0x1(%R10),%R11D

(958) 0x4875e5 CMP	%R14D,%R11D

(958) 0x4875e8 JL	487dad

(958) 0x4875ee VRNDSCALESD	$0xb,%XMM7,%XMM7,%XMM8

(958) 0x4875f5 VSUBSD	%XMM8,%XMM7,%XMM13

(958) 0x4875fa VMOVAPD	%XMM13,%XMM0

(958) 0x4875fe VMOVSD	0x1514aa(%RIP),%XMM14

(958) 0x487606 VFNMADD132SD	%XMM14,%XMM14,%XMM0

(958) 0x48760b VMULSD	0x151515(%RIP),%XMM13,%XMM12

(958) 0x487613 VXORPD	0x14faa5(%RIP),%XMM12,%XMM3

(958) 0x48761b VMOVAPD	%XMM13,%XMM18

(958) 0x487621 VADDSD	%XMM14,%XMM12,%XMM17

(958) 0x487627 VFMADD213SD	0x1514ff(%RIP),%XMM14,%XMM18

(958) 0x487631 MOVSXD	%R14D,%R13

(958) 0x487634 VMULSD	%XMM13,%XMM13,%XMM15

(958) 0x487639 VFMADD213SD	0x15145d(%RIP),%XMM13,%XMM17

(958) 0x487643 VMOVSD	0x1513f5(%RIP),%XMM10

(958) 0x48764b VFMADD213SD	0x1513f3(%RIP),%XMM15,%XMM18

(958) 0x487655 VFMADD132SD	%XMM13,%XMM10,%XMM17

(958) 0x48765b VFMADD231SD	%XMM0,%XMM13,%XMM14

(958) 0x487660 VFMADD132SD	%XMM14,%XMM10,%XMM13

(958) 0x487665 VMULSD	%XMM15,%XMM3,%XMM14

(958) 0x48766a CMPQ	$0,0x38(%RSP)

(958) 0x487670 MOV	0x10(%R8),%R14

(958) 0x487674 MOV	0x18(%R8),%R12

(958) 0x487678 MOV	0x20(%R8),%RBX

(958) 0x48767c VMOVAPD	%YMM11,0xc0(%RSP)

(958) 0x487685 VMOVAPD	%YMM1,0xe0(%RSP)

(958) 0x48768e JE	487706

(958) 0x487690 MOV	0x38(%RSP),%RDX

(958) 0x487695 XOR	%ESI,%ESI

(958) 0x487697 MOV	%R15,%RDI

(958) 0x48769a VMOVSD	%XMM14,0x80(%RSP)

(958) 0x4876a3 VMOVSD	%XMM13,0x88(%RSP)

(958) 0x4876ac VMOVSD	%XMM18,0x90(%RSP)

(958) 0x4876b4 VMOVSD	%XMM17,0x98(%RSP)

(958) 0x4876bc MOV	%R9,0xa0(%RSP)

(958) 0x4876c4 MOV	%R8,0xb0(%RSP)

(958) 0x4876cc VZEROUPPER

(958) 0x4876cf CALL	404140 <memset@plt>

(958) 0x4876d4 MOV	0xb0(%RSP),%R8

(958) 0x4876dc MOV	0xa0(%RSP),%R9

(958) 0x4876e4 VMOVSD	0x98(%RSP),%XMM17

(958) 0x4876ec VMOVSD	0x90(%RSP),%XMM18

(958) 0x4876f4 VMOVSD	0x88(%RSP),%XMM13

(958) 0x4876fd VMOVSD	0x80(%RSP),%XMM14

(958) 0x487706 MOV	0xa8(%RSP),%RDI

(958) 0x48770e MOV	0x8(%R8),%RCX

(958) 0x487712 IMUL	%RBX,%R13

(958) 0x487716 TEST	%RDI,%RDI

(958) 0x487719 JE	487c79

(958) 0x48771f MOV	0xb8(%RSP),%RAX

(958) 0x487727 MOV	%R9,%RDX

(958) 0x48772a INC	%R9

(958) 0x48772d MOV	%R12,%R10

(958) 0x487730 IMUL	%R12,%RDX

(958) 0x487734 LEA	(,%RBX,8),%R8

(958) 0x48773c LEA	0xc0(%RSP),%RSI

(958) 0x487744 VMOVQ	%R14,%XMM2

(958) 0x487749 IMUL	%R12,%R9

(958) 0x48774d LEA	(%R12,%R12,1),%R12

(958) 0x487751 VBROADCASTSD	%XMM17,%ZMM6

(958) 0x487757 VBROADCASTSD	%XMM18,%ZMM5

(958) 0x48775d SHR	$0x3,%RDI

(958) 0x487761 MOV	%R12,0x80(%RSP)

(958) 0x487769 VBROADCASTSD	%XMM13,%ZMM4

(958) 0x48776f VMOVQ	%RCX,%XMM11

(958) 0x487774 VMOVQ	%R8,%XMM12

(958) 0x487779 IMUL	%R14,%RAX

(958) 0x48777d MOV	%R15,%R12

(958) 0x487780 MOV	%RSI,%R14

(958) 0x487783 MOV	%RBX,%R15

(958) 0x487786 SAL	$0x4,%R10

(958) 0x48778a ADD	%RAX,%RDX

(958) 0x48778d ADD	%RAX,%R9

(958) 0x487790 MOV	%R10,0x78(%RSP)

(958) 0x487795 SAL	$0x6,%RDI

(958) 0x487799 LEA	(%RDX,%R13,1),%R11

(958) 0x48779d ADD	%R9,%R13

(958) 0x4877a0 MOV	%RDI,0xb8(%RSP)

(958) 0x4877a8 MOV	%R13,%RBX

  (960) 0x4877ab MOV	0x54(%RSP),%R13D

  (960) 0x4877b0 VMOVQ	%XMM11,%R10

  (960) 0x4877b5 MOV	%R11,0xb0(%RSP)

  (960) 0x4877bd MOV	%R11,0x68(%RSP)

  (960) 0x4877c2 LEA	(%R10,%R11,8),%RDX

  (960) 0x4877c6 LEA	0xe0(%RSP),%R9

  (960) 0x4877ce LEA	(%R10,%RBX,8),%RAX

  (960) 0x4877d2 VBROADCASTSD	%XMM14,%ZMM3

  (960) 0x4877d8 VBROADCASTSD	%XMM17,%YMM21

  (960) 0x4877de VBROADCASTSD	%XMM18,%YMM20

  (960) 0x4877e4 VMOVQ	%XMM12,%R11

  (960) 0x4877e9 VBROADCASTSD	%XMM13,%YMM19

  (960) 0x4877ef VMOVSD	(%R14),%XMM16

  (960) 0x4877f5 MOV	%RBX,0xa0(%RSP)

  (960) 0x4877fd MOV	%R14,0x60(%RSP)

  (960) 0x487802 MOV	%RBX,0x58(%RSP)

  (960) 0x487807 AND	$0x7,%R13D

  (960) 0x48780b MOV	%R13D,0x88(%RSP)

    (959) 0x487813 CMPQ	$0x6,0x70(%RSP)

    (959) 0x487819 VMULSD	(%R9),%XMM16,%XMM15

    (959) 0x48781f JBE	487d26

    (959) 0x487825 LEA	(%RDX,%R11,1),%RSI

    (959) 0x487829 LEA	(%R11,%RAX,1),%R8

    (959) 0x48782d VMULSD	0x8(%R9),%XMM16,%XMM1

    (959) 0x487834 VBROADCASTSD	%XMM15,%ZMM9

    (959) 0x48783a LEA	(%RSI,%R11,1),%R13

    (959) 0x48783e LEA	(%R11,%R8,1),%RDI

    (959) 0x487842 VBROADCASTSD	%XMM1,%ZMM7

    (959) 0x487848 XOR	%ECX,%ECX

    (959) 0x48784a LEA	(%R13,%R11,1),%RBX

    (959) 0x48784f LEA	(%RDI,%R11,1),%R14

    (959) 0x487853 TESTB	$0x40,0xb8(%RSP)

    (959) 0x48785b JE	4878d0

    (959) 0x48785d VMULPD	(%R8),%ZMM5,%ZMM10

    (959) 0x487863 VMULPD	(%R14),%ZMM3,%ZMM23

    (959) 0x487869 CMPQ	$0x40,0xb8(%RSP)

    (959) 0x487872 MOV	$0x40,%ECX

    (959) 0x487877 VMULPD	(%RSI),%ZMM5,%ZMM22

    (959) 0x48787d VMULPD	(%RBX),%ZMM3,%ZMM8

    (959) 0x487883 VFMADD231PD	(%RAX),%ZMM6,%ZMM10

    (959) 0x487889 VFMADD231PD	(%RDI),%ZMM4,%ZMM23

    (959) 0x48788f VADDPD	%ZMM23,%ZMM10,%ZMM0

    (959) 0x487895 VFMADD231PD	(%RDX),%ZMM6,%ZMM22

    (959) 0x48789b VFMADD231PD	(%R13),%ZMM4,%ZMM8

    (959) 0x4878a2 VADDPD	%ZMM8,%ZMM22,%ZMM24

    (959) 0x4878a8 VFMADD213PD	(%R12),%ZMM9,%ZMM24

    (959) 0x4878af VFMADD132PD	%ZMM7,%ZMM24,%ZMM0

    (959) 0x4878b5 VMOVUPD	%ZMM0,(%R12)

    (959) 0x4878bc JE	48799d

    (959) 0x4878c2 NOPW	%CS:(%RAX,%RAX,1)

    (959) 0x4878cd NOPL	(%RAX)

      (961) 0x4878d0 VMULPD	(%R8,%RCX,1),%ZMM5,%ZMM8

      (961) 0x4878d7 VMULPD	(%R14,%RCX,1),%ZMM3,%ZMM27

      (961) 0x4878de VMULPD	(%RSI,%RCX,1),%ZMM5,%ZMM25

      (961) 0x4878e5 VMULPD	(%RBX,%RCX,1),%ZMM3,%ZMM1

      (961) 0x4878ec VFMADD231PD	(%RAX,%RCX,1),%ZMM6,%ZMM8

      (961) 0x4878f3 VFMADD231PD	(%RDI,%RCX,1),%ZMM4,%ZMM27

      (961) 0x4878fa VADDPD	%ZMM27,%ZMM8,%ZMM10

      (961) 0x487900 VMULPD	0x40(%R14,%RCX,1),%ZMM3,%ZMM29

      (961) 0x487908 VFMADD231PD	(%R13,%RCX,1),%ZMM4,%ZMM1

      (961) 0x487910 VFMADD231PD	(%RDX,%RCX,1),%ZMM6,%ZMM25

      (961) 0x487917 VADDPD	%ZMM1,%ZMM25,%ZMM26

      (961) 0x48791d VFMADD213PD	(%R12,%RCX,1),%ZMM9,%ZMM26

      (961) 0x487924 VFMADD132PD	%ZMM7,%ZMM26,%ZMM10

      (961) 0x48792a VMULPD	0x40(%RCX,%R8,1),%ZMM5,%ZMM8

      (961) 0x487932 VMULPD	0x40(%RSI,%RCX,1),%ZMM5,%ZMM0

      (961) 0x48793a VFMADD231PD	0x40(%RDI,%RCX,1),%ZMM4,%ZMM29

      (961) 0x487942 VMULPD	0x40(%RBX,%RCX,1),%ZMM3,%ZMM28

      (961) 0x48794a VFMADD231PD	0x40(%RAX,%RCX,1),%ZMM6,%ZMM8

      (961) 0x487952 VFMADD231PD	0x40(%RDX,%RCX,1),%ZMM6,%ZMM0

      (961) 0x48795a VFMADD231PD	0x40(%R13,%RCX,1),%ZMM4,%ZMM28

      (961) 0x487962 VADDPD	%ZMM28,%ZMM0,%ZMM1

      (961) 0x487968 VFMADD213PD	0x40(%R12,%RCX,1),%ZMM9,%ZMM1

      (961) 0x487970 VMOVUPD	%ZMM10,(%R12,%RCX,1)

      (961) 0x487977 VADDPD	%ZMM29,%ZMM8,%ZMM10

      (961) 0x48797d VFMADD132PD	%ZMM7,%ZMM1,%ZMM10

      (961) 0x487983 VMOVUPD	%ZMM10,0x40(%R12,%RCX,1)

      (961) 0x48798b SUB	$-0x80,%RCX

      (961) 0x48798f CMP	%RCX,0xb8(%RSP)

      (961) 0x487997 JNE	4878d0

    (959) 0x48799d MOV	0xa8(%RSP),%RCX

    (959) 0x4879a5 MOV	0x88(%RSP),%ESI

    (959) 0x4879ac AND	$-0x8,%RCX

    (959) 0x4879b0 TEST	%ESI,%ESI

    (959) 0x4879b2 JE	487c12

    (959) 0x4879b8 MOV	0xa8(%RSP),%RSI

    (959) 0x4879c0 SUB	%RCX,%RSI

    (959) 0x4879c3 LEA	-0x1(%RSI),%R13

    (959) 0x4879c7 CMP	$0x2,%R13

    (959) 0x4879cb JBE	487d2d

    (959) 0x4879d1 MOV	0xb0(%RSP),%RBX

    (959) 0x4879d9 LEA	(%R12,%RCX,8),%R14

    (959) 0x4879dd VBROADCASTSD	%XMM14,%YMM0

    (959) 0x4879e2 VBROADCASTSD	%XMM15,%YMM9

    (959) 0x4879e7 VMOVSD	0x8(%R9),%XMM8

    (959) 0x4879ed VMULSD	%XMM8,%XMM16,%XMM10

    (959) 0x4879f3 LEA	(%R15,%RBX,1),%R8

    (959) 0x4879f7 LEA	(%R15,%R8,1),%RDI

    (959) 0x4879fb ADD	%RCX,%R8

    (959) 0x4879fe LEA	(%RDI,%RCX,1),%R13

    (959) 0x487a02 ADD	%R15,%RDI

    (959) 0x487a05 VMULPD	(%R10,%R8,8),%YMM20,%YMM7

    (959) 0x487a0c VMOVQ	%R13,%XMM30

    (959) 0x487a12 MOV	0xa0(%RSP),%R13

    (959) 0x487a1a LEA	(%RDI,%RCX,1),%RBX

    (959) 0x487a1e MOV	%RBX,0x98(%RSP)

    (959) 0x487a26 MOV	0x98(%RSP),%R8

    (959) 0x487a2e LEA	(%RCX,%R13,1),%RDI

    (959) 0x487a32 LEA	(%R15,%R13,1),%R13

    (959) 0x487a36 LEA	(%RCX,%R13,1),%RBX

    (959) 0x487a3a ADD	%R15,%R13

    (959) 0x487a3d VMULPD	(%R10,%R8,8),%YMM0,%YMM1

    (959) 0x487a43 VMOVQ	%RBX,%XMM31

    (959) 0x487a49 LEA	(%RCX,%R13,1),%RBX

    (959) 0x487a4d ADD	%R15,%R13

    (959) 0x487a50 ADD	%RCX,%R13

    (959) 0x487a53 VMOVQ	%XMM31,%R8

    (959) 0x487a59 MOV	%R13,0x90(%RSP)

    (959) 0x487a61 MOV	0xb0(%RSP),%R13

    (959) 0x487a69 ADD	%RCX,%R13

    (959) 0x487a6c VFMADD231PD	(%R10,%R13,8),%YMM21,%YMM7

    (959) 0x487a73 VMOVQ	%XMM30,%R13

    (959) 0x487a79 VFMADD231PD	(%R10,%R13,8),%YMM19,%YMM1

    (959) 0x487a80 VADDPD	%YMM1,%YMM7,%YMM7

    (959) 0x487a84 VFMADD213PD	(%R14),%YMM9,%YMM7

    (959) 0x487a89 VBROADCASTSD	%XMM10,%YMM9

    (959) 0x487a8e VMULPD	(%R10,%R8,8),%YMM20,%YMM10

    (959) 0x487a95 VFMADD231PD	(%R10,%RDI,8),%YMM21,%YMM10

    (959) 0x487a9c MOV	0x90(%RSP),%RDI

    (959) 0x487aa4 VMULPD	(%R10,%RDI,8),%YMM0,%YMM0

    (959) 0x487aaa VFMADD231PD	(%R10,%RBX,8),%YMM19,%YMM0

    (959) 0x487ab1 VADDPD	%YMM0,%YMM10,%YMM1

    (959) 0x487ab5 VFMADD132PD	%YMM9,%YMM7,%YMM1

    (959) 0x487aba VMOVUPD	%YMM1,(%R14)

    (959) 0x487abf MOV	%RSI,%R14

    (959) 0x487ac2 AND	$-0x4,%R14

    (959) 0x487ac6 ADD	%R14,%RCX

    (959) 0x487ac9 AND	$0x3,%ESI

    (959) 0x487acc JE	487c12

    (959) 0x487ad2 LEA	(%R15,%RCX,1),%R13

    (959) 0x487ad6 LEA	(,%RCX,8),%RSI

    (959) 0x487ade VMULSD	%XMM8,%XMM16,%XMM8

    (959) 0x487ae4 LEA	(%R15,%R13,1),%R8

    (959) 0x487ae8 LEA	(%R12,%RSI,1),%RBX

    (959) 0x487aec LEA	(%R8,%R15,1),%RDI

    (959) 0x487af0 VMULSD	(%RDX,%R8,8),%XMM13,%XMM7

    (959) 0x487af6 VMULSD	(%RAX,%R8,8),%XMM13,%XMM0

    (959) 0x487afc VFMADD231SD	(%RDX,%R13,8),%XMM18,%XMM7

    (959) 0x487b03 VMULSD	(%RDX,%RDI,8),%XMM14,%XMM9

    (959) 0x487b08 VMULSD	(%RAX,%RDI,8),%XMM14,%XMM1

    (959) 0x487b0d VFMADD231SD	(%RDX,%RSI,1),%XMM17,%XMM9

    (959) 0x487b14 VFMADD231SD	(%RAX,%R13,8),%XMM18,%XMM0

    (959) 0x487b1b VADDSD	%XMM9,%XMM7,%XMM10

    (959) 0x487b20 VFMADD231SD	(%RAX,%RSI,1),%XMM17,%XMM1

    (959) 0x487b27 VFMADD213SD	(%RBX),%XMM15,%XMM10

    (959) 0x487b2c VADDSD	%XMM1,%XMM0,%XMM7

    (959) 0x487b30 VFMADD132SD	%XMM8,%XMM10,%XMM7

    (959) 0x487b35 LEA	0x1(%RCX),%RDI

    (959) 0x487b39 VMOVSD	%XMM7,(%RBX)

    (959) 0x487b3d MOV	0xa8(%RSP),%RBX

    (959) 0x487b45 CMP	%RBX,%RDI

    (959) 0x487b48 JAE	487c12

    (959) 0x487b4e ADD	%R15,%RDI

    (959) 0x487b51 LEA	0x8(%R12,%RSI,1),%R13

    (959) 0x487b56 ADD	$0x2,%RCX

    (959) 0x487b5a LEA	(%R15,%RDI,1),%R8

    (959) 0x487b5e LEA	(%R15,%R8,1),%R14

    (959) 0x487b62 VMULSD	(%RDX,%R8,8),%XMM13,%XMM9

    (959) 0x487b68 VMULSD	(%RAX,%R8,8),%XMM13,%XMM1

    (959) 0x487b6e VFMADD231SD	(%RDX,%RDI,8),%XMM18,%XMM9

    (959) 0x487b75 VMULSD	(%RDX,%R14,8),%XMM14,%XMM10

    (959) 0x487b7b VFMADD231SD	(%RAX,%RDI,8),%XMM18,%XMM1

    (959) 0x487b82 VFMADD231SD	0x8(%RDX,%RSI,1),%XMM17,%XMM10

    (959) 0x487b8a VMULSD	(%RAX,%R14,8),%XMM14,%XMM7

    (959) 0x487b90 VADDSD	%XMM10,%XMM9,%XMM0

    (959) 0x487b95 VFMADD231SD	0x8(%RAX,%RSI,1),%XMM17,%XMM7

    (959) 0x487b9d VFMADD213SD	(%R13),%XMM15,%XMM0

    (959) 0x487ba3 VADDSD	%XMM7,%XMM1,%XMM9

    (959) 0x487ba7 VFMADD132SD	%XMM8,%XMM0,%XMM9

    (959) 0x487bac VMOVSD	%XMM9,(%R13)

    (959) 0x487bb2 CMP	%RBX,%RCX

    (959) 0x487bb5 JAE	487c12

    (959) 0x487bb7 ADD	%R15,%RCX

    (959) 0x487bba LEA	0x10(%R12,%RSI,1),%RBX

    (959) 0x487bbf LEA	(%R15,%RCX,1),%RDI

    (959) 0x487bc3 LEA	(%RDI,%R15,1),%R13

    (959) 0x487bc7 VMULSD	(%RDX,%RDI,8),%XMM13,%XMM10

    (959) 0x487bcc VFMADD231SD	(%RDX,%RCX,8),%XMM18,%XMM10

    (959) 0x487bd3 VMULSD	(%RDX,%R13,8),%XMM14,%XMM0

    (959) 0x487bd9 VMULSD	(%RAX,%R13,8),%XMM14,%XMM7

    (959) 0x487bdf VFMADD231SD	0x10(%RDX,%RSI,1),%XMM17,%XMM0

    (959) 0x487be7 VFMADD231SD	0x10(%RAX,%RSI,1),%XMM17,%XMM7

    (959) 0x487bef VADDSD	%XMM10,%XMM0,%XMM1

    (959) 0x487bf4 VFMADD213SD	(%RBX),%XMM15,%XMM1

    (959) 0x487bf9 VMULSD	(%RAX,%RDI,8),%XMM13,%XMM15

    (959) 0x487bfe VFMADD231SD	(%RAX,%RCX,8),%XMM18,%XMM15

    (959) 0x487c05 VADDSD	%XMM7,%XMM15,%XMM9

    (959) 0x487c09 VFMADD231SD	%XMM9,%XMM8,%XMM1

    (959) 0x487c0e VMOVSD	%XMM1,(%RBX)

    (959) 0x487c12 MOV	0x78(%RSP),%RCX

    (959) 0x487c17 MOV	0x80(%RSP),%RSI

    (959) 0x487c1f ADD	$0x10,%R9

    (959) 0x487c23 LEA	0x100(%RSP),%R8

    (959) 0x487c2b ADD	%RSI,0xb0(%RSP)

    (959) 0x487c33 ADD	%RSI,0xa0(%RSP)

    (959) 0x487c3b ADD	%RCX,%RDX

    (959) 0x487c3e ADD	%RCX,%RAX

    (959) 0x487c41 CMP	%R9,%R8

    (959) 0x487c44 JNE	487813

  (960) 0x487c4a MOV	0x60(%RSP),%R14

  (960) 0x487c4f MOV	0x68(%RSP),%R11

  (960) 0x487c54 MOV	0x58(%RSP),%RBX

  (960) 0x487c59 VMOVQ	%XMM2,%R9

  (960) 0x487c5e LEA	0xe0(%RSP),%R10

  (960) 0x487c66 ADD	$0x8,%R14

  (960) 0x487c6a ADD	%R9,%R11

  (960) 0x487c6d ADD	%R9,%RBX

  (960) 0x487c70 CMP	%R14,%R10

  (960) 0x487c73 JNE	4877ab

(958) 0x487c79 ADDQ	$0x8,0x48(%RSP)

(958) 0x487c7f MOV	0x30(%RSP),%RDX

(958) 0x487c84 MOV	0x48(%RSP),%RAX

(958) 0x487c89 ADDQ	$0x18,0x40(%RSP)

(958) 0x487c8f CMP	%RDX,%RAX

(958) 0x487c92 JNE	487434

0x487c98 MOV	0x10(%RSP),%R12

0x487c9d MOV	0x8(%RSP),%RBX

0x487ca2 MOV	(%RSP),%R13

0x487ca6 VZEROUPPER

0x487ca9 MOV	%R12,%RDI

0x487cac XOR	%R15D,%R15D

0x487caf XOR	%R14D,%R14D

0x487cb2 CALL	545120 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x487cb7 MOV	0x30(%RBX),%ECX

0x487cba TEST	%ECX,%ECX

0x487cbc JLE	487d17

(957) 0x487cbe MOV	0x40(%RBX),%EAX

(957) 0x487cc1 MOV	0x8(%RBX),%ESI

(957) 0x487cc4 MOV	%ECX,%EDI

(957) 0x487cc6 IMUL	%R14D,%EDI

(957) 0x487cca INC	%R14D

(957) 0x487ccd IMUL	%R14D,%EAX

(957) 0x487cd1 CMP	%ESI,%EAX

(957) 0x487cd3 CMOVG	%ESI,%EAX

(957) 0x487cd6 SUB	%EDI,%EAX

(957) 0x487cd8 TEST	%EAX,%EAX

(957) 0x487cda JLE	487d0e

(957) 0x487cdc MOV	0x310(%RBX),%R8

(957) 0x487ce3 MOV	0x18(%R13),%R9

(957) 0x487ce7 CLTQ

(957) 0x487ce9 MOVSXD	%EDI,%R11

(957) 0x487cec LEA	(,%RAX,8),%RDX

(957) 0x487cf4 MOV	(%R8,%R15,1),%RSI

(957) 0x487cf8 LEA	(%R9,%R11,8),%RDI

(957) 0x487cfc CMP	$0x8,%RDX

(957) 0x487d00 JE	487dd5

(957) 0x487d06 CALL	4040d0 <memmove@plt>

(957) 0x487d0b MOV	0x30(%RBX),%ECX

(957) 0x487d0e ADD	$0x18,%R15

(957) 0x487d12 CMP	%ECX,%R14D

(957) 0x487d15 JL	487cbe

0x487d17 LEA	-0x28(%RBP),%RSP

0x487d1b POP	%RBX

0x487d1c POP	%R12

0x487d1e POP	%R13

0x487d20 POP	%R14

0x487d22 POP	%R15

0x487d24 POP	%RBP

0x487d25 RET

    (959) 0x487d26 XOR	%ECX,%ECX

    (959) 0x487d28 JMP	4879b8

    (959) 0x487d2d VMOVSD	0x8(%R9),%XMM8

    (959) 0x487d33 JMP	487ad2

(958) 0x487d38 VMOVSD	0x150d00(%RIP),%XMM13

(958) 0x487d40 XOR	%R13D,%R13D

(958) 0x487d43 VMOVAPD	%XMM13,%XMM17

(958) 0x487d49 VXORPD	%XMM14,%XMM14,%XMM14

(958) 0x487d4e VMOVSD	0x150cf0(%RIP),%XMM18

(958) 0x487d58 JMP	48766a

(958) 0x487d5d VMOVAPD	0x150cdb(%RIP),%YMM1

(958) 0x487d65 XOR	%R9D,%R9D

(958) 0x487d68 JMP	4875bf

(958) 0x487d6d VMOVAPD	0x150ccb(%RIP),%YMM11

(958) 0x487d75 MOVQ	$0,0xb8(%RSP)

(958) 0x487d81 JMP	48751e

(958) 0x487d86 VMOVAPD	0x150cd2(%RIP),%YMM1

(958) 0x487d8e MOVSXD	%ESI,%R9

(958) 0x487d91 JMP	4875bf

(958) 0x487d96 CLTQ

(958) 0x487d98 VMOVAPD	0x150cc0(%RIP),%YMM11

(958) 0x487da0 MOV	%RAX,0xb8(%RSP)

(958) 0x487da8 JMP	48751e

(958) 0x487dad MOVSXD	%R11D,%R13

(958) 0x487db0 VMOVSD	0x150cc0(%RIP),%XMM14

(958) 0x487db8 VMOVSD	0x150c88(%RIP),%XMM13

(958) 0x487dc0 VMOVSD	0x150c9e(%RIP),%XMM18

(958) 0x487dca VXORPD	%XMM17,%XMM17,%XMM17

(958) 0x487dd0 JMP	48766a

(957) 0x487dd5 VMOVSD	(%RSI),%XMM3

(957) 0x487dd9 VMOVSD	%XMM3,(%RDI)

(957) 0x487ddd JMP	487d0e

0x487de2 VMOVAPD	%XMM13,%XMM15

0x487de7 JMP	4873c0

0x487dec NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►49.33+	miniqmcreference::DiracDetermi[...]		exec
○	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►47.27+	miniqmcreference::DiracDetermi[...]		exec
○	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 5.25 cycles (2.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.63 to 1.28 cycles (9.85x speedup).

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVB: 1 occurrences►
VCOMISD: 2 occurrences►
VMOVHPD: 1 occurrences►

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 192 bytes (24 double precision FP elements). The binary function is storing 100 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	101
loop length	439
used x86 registers	16
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	9.25	9.25	9.25	9.25	5.50	5.50	5.50	5.50	3.00	3.00
cycles	4.17	4.17	4.17	4.17	4.17	4.17	9.25	9.25	9.25	9.25	5.50	5.50	5.50	5.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.63
Dispatch	9.25
Overall L1	12.63

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	46%
load	36%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	61%

INT+FP

all	29%
load	25%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	17%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	15%
load	15%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 12.63 cycles. At this rate:

5% of peak load performance is reached (15.21 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.63 to 9.25 cycles (1.36x speedup).

ASM code

In the binary file, the address of the function is: 4872c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVSXD %EDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 544ee0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x128(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP 0x124(%R14),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 48730f <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R15,%R15,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RCX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0x151800(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMULSD 0x118(%RBX),%XMM2,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SD 0xe8(%RBX),%XMM6,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VPERMILPD $0x3,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULPD 0xf0(%RBX),%XMM4,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VPERMILPD $0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VUNPCKHPD %XMM0,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VFMADD231PD 0xd8(%RBX),%XMM3,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD132PD 0x108(%RBX),%XMM8,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VCMPPD $0xe,%XMM9,%XMM1,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VFMADD132SD 0x100(%RBX),%XMM5,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VRNDSCALEPD $0x9,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VCMPPD $0x1,%XMM10,%XMM1,%K0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
KNOTB %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K2,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VCOMISD %XMM7,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
KMOVB %ESI,%K3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VSUBPD %XMM11,%XMM1,%XMM12{%K3}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
JBE 4873b4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xf4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCOMISD 0x151772(%RIP),%XMM7	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 487de2 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xb22>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 487ca9 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x9e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x40(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x2f8(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x310(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVHPD %XMM12,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VMOVLPD %XMM12,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%R8,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RDI,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%R8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R8,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 545120 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 487d17 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xa57>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVAPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4873c0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x100>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 5.25 cycles (2.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVB: 1 occurrences►
VCOMISD: 2 occurrences►
VMOVHPD: 1 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 192 bytes (24 double precision FP elements). The binary function is storing 100 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	101
loop length	439
used x86 registers	16
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	9.25	9.25	9.25	9.25	5.50	5.50	5.50	5.50	3.00	3.00
cycles	4.17	4.17	4.17	4.17	4.17	4.17	9.25	9.25	9.25	9.25	5.50	5.50	5.50	5.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.63
Dispatch	9.25
Overall L1	12.63

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	46%
load	36%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	61%

INT+FP

all	29%
load	25%
store	0%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	17%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	15%
load	15%
store	12%
mul	18%
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 12.63 cycles. At this rate:

5% of peak load performance is reached (15.21 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4872c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVSXD %EDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x358(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 544ee0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x128(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP 0x124(%R14),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 48730f <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x4f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R15,%R15,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RCX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0x151800(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMULSD 0x118(%RBX),%XMM2,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD231SD 0xe8(%RBX),%XMM6,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VPERMILPD $0x3,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMULPD 0xf0(%RBX),%XMM4,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VPERMILPD $0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VUNPCKHPD %XMM0,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VFMADD231PD 0xd8(%RBX),%XMM3,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD132PD 0x108(%RBX),%XMM8,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VCMPPD $0xe,%XMM9,%XMM1,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VFMADD132SD 0x100(%RBX),%XMM5,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VRNDSCALEPD $0x9,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VCMPPD $0x1,%XMM10,%XMM1,%K0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
KNOTB %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KMOVB %K2,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
AND $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VCOMISD %XMM7,%XMM13	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
KMOVB %ESI,%K3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VSUBPD %XMM11,%XMM1,%XMM12{%K3}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
JBE 4873b4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xf4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCOMISD 0x151772(%RIP),%XMM7	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 487de2 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xb22>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM14,%XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSXD 0x30(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST %EDI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 487ca9 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x9e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD 0x40(%RBX),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x2f8(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x310(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVHPD %XMM12,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VMOVLPD %XMM12,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%R8,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RDI,8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%R8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R8,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CALL 545120 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 487d17 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xa57>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVAPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4873c0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x100>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	25.82	42.65
▼Loop 958 - - exec–	0.00	0.01
▼Loop 960 - - exec–	0.00	0.01
▼Loop 959 - - exec–	0.00	0.01
○Loop 961 - - exec	25.80	42.24
○Loop 957 - - exec	0.00	0.01

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