OV - exec - Function miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x420e20 LEA	0x8(%RSP),%R10

0x420e25 AND	$-0x40,%RSP

0x420e29 MOV	$0x1,%EAX

0x420e2e PUSHQ	-0x8(%R10)

0x420e32 PUSH	%RBP

0x420e33 VPBROADCASTD	%EAX,%YMM2

0x420e39 MOV	%RSP,%RBP

0x420e3c PUSH	%R15

0x420e3e PUSH	%R14

0x420e40 PUSH	%R13

0x420e42 PUSH	%R12

0x420e44 PUSH	%R10

0x420e46 PUSH	%RBX

0x420e47 SUB	$0x280,%RSP

0x420e4e MOV	0x8(%RDX),%RCX

0x420e52 VMOVDQA	%YMM2,-0x270(%RBP)

0x420e5a MOV	%RSI,-0x288(%RBP)

0x420e61 CMP	%RCX,(%RDX)

0x420e64 JE	422095

0x420e6a XOR	%R13D,%R13D

0x420e6d MOV	%RDI,%RBX

0x420e70 MOV	%RDX,%R15

0x420e73 VZEROUPPER

0x420e76 NOPW	%CS:(%RAX,%RAX,1)

(252) 0x420e80 MOV	-0x288(%RBP),%RDI

(252) 0x420e87 MOV	0xf0(%RBX),%RSI

(252) 0x420e8e MOVSXD	0x2a0(%RDI),%RDX

(252) 0x420e95 VMOVSD	(%RSI,%RDX,8),%XMM1

(252) 0x420e9a MOV	0xa8(%RBX),%ESI

(252) 0x420ea0 VMOVSD	%XMM1,-0xb0(%RBP)

(252) 0x420ea8 CALL	4d55e0 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>

(252) 0x420ead LEA	(%R13,%R13,4),%R8

(252) 0x420eb2 VMOVSD	-0xb0(%RBP),%XMM5

(252) 0x420eba MOV	0x48(%RAX),%R9

(252) 0x420ebe LEA	(%R9,%R8,8),%R11

(252) 0x420ec2 MOVSXD	0x98(%RBX),%R9

(252) 0x420ec9 MOV	0x18(%R11),%R12

(252) 0x420ecd TEST	%R9D,%R9D

(252) 0x420ed0 JLE	421cb0

(252) 0x420ed6 MOV	$0x2,%R11D

(252) 0x420edc MOV	$0x1,%EDX

(252) 0x420ee1 MOV	0x1c8(%RBX),%R10

(252) 0x420ee8 MOV	%R15,-0x280(%RBP)

(252) 0x420eef VPBROADCASTD	%R11D,%ZMM7

(252) 0x420ef5 VPBROADCASTD	%EDX,%ZMM6

(252) 0x420efb XOR	%EDI,%EDI

(252) 0x420efd KXNORB	%K1,%K1,%K1

(252) 0x420f01 SAL	$0x2,%R9

(252) 0x420f05 MOVQ	$0,-0x210(%RBP)

(252) 0x420f10 MOV	%R13,-0x278(%RBP)

(252) 0x420f17 VMOVDQA32	%ZMM6,-0x1b0(%RBP)

(252) 0x420f21 VMOVQ	%XMM5,%R15

(252) 0x420f26 VMOVDQA32	%ZMM7,-0x1f0(%RBP)

(252) 0x420f30 MOV	%R12,%R11

(252) 0x420f33 NOPW	%CS:(%RAX,%RAX,1)

(252) 0x420f3e XCHG	%AX,%AX

  (254) 0x420f40 MOV	(%R10,%RDI,2),%R12

  (254) 0x420f44 TEST	%R12,%R12

  (254) 0x420f47 JE	421c3f

  (254) 0x420f4d MOV	0xa0(%RBX),%RSI

  (254) 0x420f54 MOV	0x268(%RSI),%RCX

  (254) 0x420f5b MOV	0x148(%RBX),%RSI

  (254) 0x420f62 MOV	0x18(%RCX),%RAX

  (254) 0x420f66 MOVSXD	(%RAX,%RDI,1),%R8

  (254) 0x420f6a MOV	0x4(%RAX,%RDI,1),%R14D

  (254) 0x420f6f MOV	%R8,%R13

  (254) 0x420f72 CMP	%R8D,%R14D

  (254) 0x420f75 JLE	421c3f

  (254) 0x420f7b LEA	(%R11,%R8,8),%RCX

  (254) 0x420f7f MOV	%R8D,%EAX

  (254) 0x420f82 MOV	%R14D,%R8D

  (254) 0x420f85 XOR	%EDX,%EDX

  (254) 0x420f87 SUB	%R13D,%R8D

  (254) 0x420f8a VMOVSD	0x8(%R12),%XMM9

  (254) 0x420f91 AND	$0x7,%R8D

  (254) 0x420f95 JE	4210bb

  (254) 0x420f9b CMP	$0x1,%R8D

  (254) 0x420f9f JE	421092

  (254) 0x420fa5 CMP	$0x2,%R8D

  (254) 0x420fa9 JE	421071

  (254) 0x420faf CMP	$0x3,%R8D

  (254) 0x420fb3 JE	421050

  (254) 0x420fb9 CMP	$0x4,%R8D

  (254) 0x420fbd JE	42102f

  (254) 0x420fbf CMP	$0x5,%R8D

  (254) 0x420fc3 JE	42100e

  (254) 0x420fc5 CMP	$0x6,%R8D

  (254) 0x420fc9 JE	420fed

  (254) 0x420fcb VMOVSD	(%RCX),%XMM10

  (254) 0x420fcf VCOMISD	%XMM10,%XMM9

  (254) 0x420fd4 JBE	420fe5

  (254) 0x420fd6 CMP	$-0x1,%R13D

  (254) 0x420fda JE	420fe5

  (254) 0x420fdc MOV	$0x1,%EDX

  (254) 0x420fe1 VMOVSD	%XMM10,(%RSI)

  (254) 0x420fe5 ADD	$0x8,%RCX

  (254) 0x420fe9 LEA	0x1(%R13),%EAX

  (254) 0x420fed VMOVSD	(%RCX),%XMM11

  (254) 0x420ff1 VCOMISD	%XMM11,%XMM9

  (254) 0x420ff6 JBE	421008

  (254) 0x420ff8 CMP	$-0x1,%EAX

  (254) 0x420ffb JE	421008

  (254) 0x420ffd MOVSXD	%EDX,%R13

  (254) 0x421000 INC	%EDX

  (254) 0x421002 VMOVSD	%XMM11,(%RSI,%R13,8)

  (254) 0x421008 ADD	$0x8,%RCX

  (254) 0x42100c INC	%EAX

  (254) 0x42100e VMOVSD	(%RCX),%XMM12

  (254) 0x421012 VCOMISD	%XMM12,%XMM9

  (254) 0x421017 JBE	421029

  (254) 0x421019 CMP	$-0x1,%EAX

  (254) 0x42101c JE	421029

  (254) 0x42101e MOVSXD	%EDX,%R8

  (254) 0x421021 INC	%EDX

  (254) 0x421023 VMOVSD	%XMM12,(%RSI,%R8,8)

  (254) 0x421029 ADD	$0x8,%RCX

  (254) 0x42102d INC	%EAX

  (254) 0x42102f VMOVSD	(%RCX),%XMM13

  (254) 0x421033 VCOMISD	%XMM13,%XMM9

  (254) 0x421038 JBE	42104a

  (254) 0x42103a CMP	$-0x1,%EAX

  (254) 0x42103d JE	42104a

  (254) 0x42103f MOVSXD	%EDX,%R13

  (254) 0x421042 INC	%EDX

  (254) 0x421044 VMOVSD	%XMM13,(%RSI,%R13,8)

  (254) 0x42104a ADD	$0x8,%RCX

  (254) 0x42104e INC	%EAX

  (254) 0x421050 VMOVSD	(%RCX),%XMM14

  (254) 0x421054 VCOMISD	%XMM14,%XMM9

  (254) 0x421059 JBE	42106b

  (254) 0x42105b CMP	$-0x1,%EAX

  (254) 0x42105e JE	42106b

  (254) 0x421060 MOVSXD	%EDX,%R8

  (254) 0x421063 INC	%EDX

  (254) 0x421065 VMOVSD	%XMM14,(%RSI,%R8,8)

  (254) 0x42106b ADD	$0x8,%RCX

  (254) 0x42106f INC	%EAX

  (254) 0x421071 VMOVSD	(%RCX),%XMM15

  (254) 0x421075 VCOMISD	%XMM15,%XMM9

  (254) 0x42107a JBE	42108c

  (254) 0x42107c CMP	$-0x1,%EAX

  (254) 0x42107f JE	42108c

  (254) 0x421081 MOVSXD	%EDX,%R13

  (254) 0x421084 INC	%EDX

  (254) 0x421086 VMOVSD	%XMM15,(%RSI,%R13,8)

  (254) 0x42108c ADD	$0x8,%RCX

  (254) 0x421090 INC	%EAX

  (254) 0x421092 VMOVSD	(%RCX),%XMM2

  (254) 0x421096 VCOMISD	%XMM2,%XMM9

  (254) 0x42109a JBE	4210ac

  (254) 0x42109c CMP	$-0x1,%EAX

  (254) 0x42109f JE	4210ac

  (254) 0x4210a1 MOVSXD	%EDX,%R8

  (254) 0x4210a4 INC	%EDX

  (254) 0x4210a6 VMOVSD	%XMM2,(%RSI,%R8,8)

  (254) 0x4210ac INC	%EAX

  (254) 0x4210ae ADD	$0x8,%RCX

  (254) 0x4210b2 CMP	%EAX,%R14D

  (254) 0x4210b5 JE	4211c6

    (255) 0x4210bb VMOVSD	(%RCX),%XMM1

    (255) 0x4210bf VCOMISD	%XMM1,%XMM9

    (255) 0x4210c3 JBE	4210d5

    (255) 0x4210c5 CMP	$-0x1,%EAX

    (255) 0x4210c8 JE	4210d5

    (255) 0x4210ca MOVSXD	%EDX,%R13

    (255) 0x4210cd INC	%EDX

    (255) 0x4210cf VMOVSD	%XMM1,(%RSI,%R13,8)

    (255) 0x4210d5 INC	%EAX

    (255) 0x4210d7 VMOVSD	0x8(%RCX),%XMM4

    (255) 0x4210dc LEA	0x8(%RCX),%R8

    (255) 0x4210e0 VCOMISD	%XMM4,%XMM9

    (255) 0x4210e4 JBE	4210f5

    (255) 0x4210e6 CMP	$-0x1,%EAX

    (255) 0x4210e9 JE	4210f5

    (255) 0x4210eb MOVSXD	%EDX,%RCX

    (255) 0x4210ee INC	%EDX

    (255) 0x4210f0 VMOVSD	%XMM4,(%RSI,%RCX,8)

    (255) 0x4210f5 VMOVSD	0x8(%R8),%XMM3

    (255) 0x4210fb LEA	0x1(%RAX),%R13D

    (255) 0x4210ff VCOMISD	%XMM3,%XMM9

    (255) 0x421103 JBE	421115

    (255) 0x421105 CMP	$-0x1,%R13D

    (255) 0x421109 JE	421115

    (255) 0x42110b MOVSXD	%EDX,%RCX

    (255) 0x42110e INC	%EDX

    (255) 0x421110 VMOVSD	%XMM3,(%RSI,%RCX,8)

    (255) 0x421115 VMOVSD	0x10(%R8),%XMM0

    (255) 0x42111b LEA	0x2(%RAX),%R13D

    (255) 0x42111f VCOMISD	%XMM0,%XMM9

    (255) 0x421123 JBE	421135

    (255) 0x421125 CMP	$-0x1,%R13D

    (255) 0x421129 JE	421135

    (255) 0x42112b MOVSXD	%EDX,%RCX

    (255) 0x42112e INC	%EDX

    (255) 0x421130 VMOVSD	%XMM0,(%RSI,%RCX,8)

    (255) 0x421135 VMOVSD	0x18(%R8),%XMM8

    (255) 0x42113b LEA	0x3(%RAX),%R13D

    (255) 0x42113f VCOMISD	%XMM8,%XMM9

    (255) 0x421144 JBE	421156

    (255) 0x421146 CMP	$-0x1,%R13D

    (255) 0x42114a JE	421156

    (255) 0x42114c MOVSXD	%EDX,%RCX

    (255) 0x42114f INC	%EDX

    (255) 0x421151 VMOVSD	%XMM8,(%RSI,%RCX,8)

    (255) 0x421156 VMOVSD	0x20(%R8),%XMM5

    (255) 0x42115c LEA	0x4(%RAX),%R13D

    (255) 0x421160 VCOMISD	%XMM5,%XMM9

    (255) 0x421164 JBE	421176

    (255) 0x421166 CMP	$-0x1,%R13D

    (255) 0x42116a JE	421176

    (255) 0x42116c MOVSXD	%EDX,%RCX

    (255) 0x42116f INC	%EDX

    (255) 0x421171 VMOVSD	%XMM5,(%RSI,%RCX,8)

    (255) 0x421176 VMOVSD	0x28(%R8),%XMM6

    (255) 0x42117c LEA	0x5(%RAX),%R13D

    (255) 0x421180 VCOMISD	%XMM6,%XMM9

    (255) 0x421184 JBE	421196

    (255) 0x421186 CMP	$-0x1,%R13D

    (255) 0x42118a JE	421196

    (255) 0x42118c MOVSXD	%EDX,%RCX

    (255) 0x42118f INC	%EDX

    (255) 0x421191 VMOVSD	%XMM6,(%RSI,%RCX,8)

    (255) 0x421196 VMOVSD	0x30(%R8),%XMM7

    (255) 0x42119c LEA	0x6(%RAX),%R13D

    (255) 0x4211a0 VCOMISD	%XMM7,%XMM9

    (255) 0x4211a4 JBE	4211b6

    (255) 0x4211a6 CMP	$-0x1,%R13D

    (255) 0x4211aa JE	4211b6

    (255) 0x4211ac MOVSXD	%EDX,%RCX

    (255) 0x4211af INC	%EDX

    (255) 0x4211b1 VMOVSD	%XMM7,(%RSI,%RCX,8)

    (255) 0x4211b6 ADD	$0x7,%EAX

    (255) 0x4211b9 LEA	0x38(%R8),%RCX

    (255) 0x4211bd CMP	%EAX,%R14D

    (255) 0x4211c0 JNE	4210bb

  (254) 0x4211c6 TEST	%EDX,%EDX

  (254) 0x4211c8 JE	421c3f

  (254) 0x4211ce VMOVSD	0x48(%R12),%XMM3

  (254) 0x4211d5 VMOVSD	0x50(%R12),%XMM6

  (254) 0x4211dc VMOVSD	0x58(%R12),%XMM5

  (254) 0x4211e3 VMOVSD	0x60(%R12),%XMM14

  (254) 0x4211ea VMOVSD	0x68(%R12),%XMM15

  (254) 0x4211f1 VMOVSD	0x70(%R12),%XMM13

  (254) 0x4211f8 VMOVSD	0x78(%R12),%XMM12

  (254) 0x4211ff VMOVSD	0x80(%R12),%XMM8

  (254) 0x421209 VMOVSD	0x88(%R12),%XMM11

  (254) 0x421213 MOV	0x218(%R12),%RAX

  (254) 0x42121b VMOVSD	0x238(%R12),%XMM4

  (254) 0x421225 VMOVSD	0x18(%R12),%XMM0

  (254) 0x42122c VMOVSD	0x20(%R12),%XMM7

  (254) 0x421233 VMOVSD	0x28(%R12),%XMM9

  (254) 0x42123a VMOVSD	0x30(%R12),%XMM10

  (254) 0x421241 VMOVSD	0x38(%R12),%XMM2

  (254) 0x421248 VMOVSD	0x40(%R12),%XMM1

  (254) 0x42124f VMOVSD	0x90(%R12),%XMM31

  (254) 0x421257 LEA	-0x1(%RDX),%R12D

  (254) 0x42125b VMOVSD	%XMM3,-0x48(%RBP)

  (254) 0x421260 VMOVSD	%XMM6,-0x50(%RBP)

  (254) 0x421265 VMOVSD	%XMM5,-0x58(%RBP)

  (254) 0x42126a VMOVSD	%XMM14,-0x60(%RBP)

  (254) 0x42126f VMOVSD	%XMM15,-0x68(%RBP)

  (254) 0x421274 VMOVSD	%XMM13,-0x70(%RBP)

  (254) 0x421279 VMOVSD	%XMM12,-0x1f8(%RBP)

  (254) 0x421281 VMOVSD	%XMM8,-0x200(%RBP)

  (254) 0x421289 VMOVSD	%XMM11,-0x208(%RBP)

  (254) 0x421291 CMP	$0xe,%R12D

  (254) 0x421295 JBE	422087

  (254) 0x42129b MOV	%EDX,%R13D

  (254) 0x42129e VBROADCASTSD	%XMM1,%ZMM29

  (254) 0x4212a4 VBROADCASTSD	%XMM3,%ZMM30

  (254) 0x4212aa VBROADCASTSD	%XMM2,%ZMM22

  (254) 0x4212b0 SHR	$0x4,%R13D

  (254) 0x4212b4 VMOVSD	%XMM31,-0x250(%RBP)

  (254) 0x4212bb VMOVSD	%XMM4,-0x218(%RBP)

  (254) 0x4212c3 VMOVSD	%XMM0,-0x220(%RBP)

  (254) 0x4212cb VBROADCASTSD	%XMM6,%ZMM28

  (254) 0x4212d1 VBROADCASTSD	%XMM14,%ZMM21

  (254) 0x4212d7 VXORPD	%XMM14,%XMM14,%XMM14

  (254) 0x4212dc VMOVAPD	%ZMM29,-0x130(%RBP)

  (254) 0x4212e6 SAL	$0x7,%R13

  (254) 0x4212ea VMOVSD	%XMM7,-0x228(%RBP)

  (254) 0x4212f2 VMOVSD	%XMM9,-0x230(%RBP)

  (254) 0x4212fa VMOVSD	%XMM10,-0x238(%RBP)

  (254) 0x421302 VBROADCASTSD	%XMM15,%ZMM20

  (254) 0x421308 VBROADCASTSD	%XMM4,%ZMM27

  (254) 0x42130e VBROADCASTSD	%XMM31,%ZMM15

  (254) 0x421314 VBROADCASTSD	%XMM0,%ZMM26

  (254) 0x42131a VMOVAPD	%ZMM30,%ZMM31

  (254) 0x421320 VBROADCASTSD	%XMM7,%ZMM25

  (254) 0x421326 VBROADCASTSD	%XMM9,%ZMM24

  (254) 0x42132c VBROADCASTSD	%XMM10,%ZMM23

  (254) 0x421332 VBROADCASTSD	%XMM5,%ZMM29

  (254) 0x421338 VBROADCASTSD	%XMM13,%ZMM19

  (254) 0x42133e VBROADCASTSD	%XMM12,%ZMM18

  (254) 0x421344 VBROADCASTSD	%XMM8,%ZMM17

  (254) 0x42134a VBROADCASTSD	%XMM11,%ZMM16

  (254) 0x421350 MOV	%RSI,%R14

  (254) 0x421353 ADD	%RSI,%R13

  (254) 0x421356 VMOVAPD	%ZMM22,%ZMM30

  (254) 0x42135c VMOVAPD	%ZMM28,-0x170(%RBP)

  (254) 0x421366 VMOVSD	%XMM2,-0x240(%RBP)

  (254) 0x42136e VMOVSD	%XMM1,-0x248(%RBP)

  (254) 0x421376 VMOVAPD	%ZMM14,-0xb0(%RBP)

    (257) 0x421380 VMULPD	(%R14),%ZMM27,%ZMM7

    (257) 0x421386 VMULPD	0x40(%R14),%ZMM27,%ZMM9

    (257) 0x42138d KMOVB	%K1,%K3

    (257) 0x421391 VMOVAPD	%ZMM24,%ZMM8

    (257) 0x421397 SUB	$-0x80,%R14

    (257) 0x42139b KMOVB	%K1,%K4

    (257) 0x42139f KMOVB	%K1,%K2

    (257) 0x4213a3 KMOVB	%K1,%K5

    (257) 0x4213a7 KMOVB	%K1,%K6

    (257) 0x4213ab KMOVB	%K1,%K7

    (257) 0x4213af VRNDSCALEPD	$0xb,%ZMM7,%ZMM10

    (257) 0x4213b6 VCVTTPD2DQ	%ZMM7,%YMM6

    (257) 0x4213bc VCVTTPD2DQ	%ZMM9,%YMM4

    (257) 0x4213c2 VINSERTI32X8	$0x1,%YMM4,%ZMM6,%ZMM3

    (257) 0x4213c9 VGATHERDPD	(%RAX,%YMM6,8),%ZMM28{%K2}

    (257) 0x4213d0 VSHUFI32X4	$-0x12,%ZMM3,%ZMM3,%ZMM5

    (257) 0x4213d7 KMOVB	%K1,%K2

    (257) 0x4213db VGATHERDPD	(%RAX,%YMM5,8),%ZMM22{%K3}

    (257) 0x4213e2 KMOVB	%K1,%K3

    (257) 0x4213e6 VRNDSCALEPD	$0xb,%ZMM9,%ZMM0

    (257) 0x4213ed VSUBPD	%ZMM10,%ZMM7,%ZMM1

    (257) 0x4213f3 VMOVAPD	%ZMM24,%ZMM7

    (257) 0x4213f9 VFMADD132PD	%ZMM1,%ZMM23,%ZMM8

    (257) 0x4213ff VSUBPD	%ZMM0,%ZMM9,%ZMM2

    (257) 0x421405 VMULPD	%ZMM1,%ZMM1,%ZMM0

    (257) 0x42140b VPADDD	-0x1b0(%RBP),%ZMM3,%ZMM5

    (257) 0x421415 VMULPD	%ZMM2,%ZMM2,%ZMM4

    (257) 0x42141b VFMADD132PD	%ZMM2,%ZMM23,%ZMM7

    (257) 0x421421 VMULPD	%ZMM1,%ZMM0,%ZMM10

    (257) 0x421427 VMULPD	%ZMM0,%ZMM25,%ZMM13

    (257) 0x42142d VMULPD	%ZMM2,%ZMM4,%ZMM9

    (257) 0x421433 VMULPD	%ZMM4,%ZMM25,%ZMM12

    (257) 0x421439 VFMADD231PD	%ZMM10,%ZMM26,%ZMM13

    (257) 0x42143f VFMADD231PD	%ZMM9,%ZMM26,%ZMM12

    (257) 0x421445 VADDPD	%ZMM13,%ZMM8,%ZMM11

    (257) 0x42144b VMOVAPD	-0x130(%RBP),%ZMM8

    (257) 0x421455 VGATHERDPD	(%RAX,%YMM5,8),%ZMM13{%K4}

    (257) 0x42145c VMOVAPD	%ZMM13,-0xf0(%RBP)

    (257) 0x421466 VMOVAPD	-0x170(%RBP),%ZMM13

    (257) 0x421470 VADDPD	%ZMM7,%ZMM12,%ZMM7

    (257) 0x421476 VSHUFI32X4	$-0x12,%ZMM5,%ZMM5,%ZMM12

    (257) 0x42147d VGATHERDPD	(%RAX,%YMM12,8),%ZMM6{%K5}

    (257) 0x421484 VMULPD	%ZMM8,%ZMM0,%ZMM12

    (257) 0x42148a VMULPD	%ZMM8,%ZMM4,%ZMM8

    (257) 0x421490 VMOVAPD	%ZMM13,%ZMM5

    (257) 0x421496 VFMADD231PD	%ZMM2,%ZMM31,%ZMM13

    (257) 0x42149c VFMADD231PD	%ZMM1,%ZMM31,%ZMM5

    (257) 0x4214a2 VFMADD231PD	%ZMM10,%ZMM30,%ZMM12

    (257) 0x4214a8 VFMADD231PD	%ZMM9,%ZMM30,%ZMM8

    (257) 0x4214ae VADDPD	%ZMM12,%ZMM5,%ZMM12

    (257) 0x4214b4 VADDPD	%ZMM13,%ZMM8,%ZMM8

    (257) 0x4214ba VMULPD	-0xf0(%RBP),%ZMM12,%ZMM13

    (257) 0x4214c4 VMULPD	%ZMM8,%ZMM6,%ZMM6

    (257) 0x4214ca VFMADD231PD	%ZMM22,%ZMM7,%ZMM6

    (257) 0x4214d0 VPADDD	-0x1f0(%RBP),%ZMM3,%ZMM7

    (257) 0x4214da VMULPD	%ZMM21,%ZMM0,%ZMM22

    (257) 0x4214e0 VPADDD	0x1b6b56(%RIP),%ZMM3,%ZMM3

    (257) 0x4214ea VMULPD	%ZMM17,%ZMM0,%ZMM0

    (257) 0x4214f0 VFMADD231PD	%ZMM29,%ZMM10,%ZMM22

    (257) 0x4214f6 VFMADD231PD	%ZMM28,%ZMM11,%ZMM13

    (257) 0x4214fc VMOVAPD	%ZMM1,%ZMM11

    (257) 0x421502 VMOVAPD	%ZMM2,%ZMM28

    (257) 0x421508 VFMADD231PD	%ZMM18,%ZMM10,%ZMM0

    (257) 0x42150e VFMADD132PD	%ZMM16,%ZMM15,%ZMM1

    (257) 0x421514 VFMADD132PD	%ZMM20,%ZMM19,%ZMM11

    (257) 0x42151a VFMADD132PD	%ZMM16,%ZMM15,%ZMM2

    (257) 0x421520 VGATHERDPD	(%RAX,%YMM7,8),%ZMM5{%K6}

    (257) 0x421527 VFMADD132PD	%ZMM20,%ZMM19,%ZMM28

    (257) 0x42152d VSHUFI32X4	$-0x12,%ZMM7,%ZMM7,%ZMM8

    (257) 0x421534 VMULPD	%ZMM21,%ZMM4,%ZMM7

    (257) 0x42153a VMULPD	%ZMM17,%ZMM4,%ZMM4

    (257) 0x421540 VGATHERDPD	(%RAX,%YMM8,8),%ZMM12{%K7}

    (257) 0x421547 VADDPD	%ZMM1,%ZMM0,%ZMM1

    (257) 0x42154d VADDPD	%ZMM22,%ZMM11,%ZMM8

    (257) 0x421553 VGATHERDPD	(%RAX,%YMM3,8),%ZMM22{%K2}

    (257) 0x42155a VSHUFI32X4	$-0x12,%ZMM3,%ZMM3,%ZMM11

    (257) 0x421561 VFMADD231PD	%ZMM18,%ZMM9,%ZMM4

    (257) 0x421567 VMULPD	%ZMM22,%ZMM1,%ZMM10

    (257) 0x42156d VFMADD231PD	%ZMM29,%ZMM9,%ZMM7

    (257) 0x421573 VFMADD132PD	%ZMM8,%ZMM10,%ZMM5

    (257) 0x421579 VADDPD	%ZMM2,%ZMM4,%ZMM2

    (257) 0x42157f VADDPD	%ZMM28,%ZMM7,%ZMM7

    (257) 0x421585 VGATHERDPD	(%RAX,%YMM11,8),%ZMM28{%K3}

    (257) 0x42158c VMULPD	%ZMM2,%ZMM28,%ZMM22

    (257) 0x421592 VADDPD	%ZMM5,%ZMM13,%ZMM9

    (257) 0x421598 VADDPD	-0xb0(%RBP),%ZMM9,%ZMM13

    (257) 0x4215a2 VFMADD231PD	%ZMM7,%ZMM12,%ZMM22

    (257) 0x4215a8 VADDPD	%ZMM22,%ZMM6,%ZMM6

    (257) 0x4215ae VMOVAPD	%ZMM13,-0xb0(%RBP)

    (257) 0x4215b8 VADDPD	%ZMM6,%ZMM14,%ZMM14

    (257) 0x4215be CMP	%R14,%R13

    (257) 0x4215c1 JNE	421380

  (254) 0x4215c7 VADDPD	%ZMM14,%ZMM13,%ZMM15

  (254) 0x4215cd MOV	%EDX,%ECX

  (254) 0x4215cf VMOVSD	-0x218(%RBP),%XMM4

  (254) 0x4215d7 VMOVSD	-0x220(%RBP),%XMM0

  (254) 0x4215df AND	$-0x10,%ECX

  (254) 0x4215e2 VMOVSD	-0x228(%RBP),%XMM7

  (254) 0x4215ea VMOVSD	-0x230(%RBP),%XMM9

  (254) 0x4215f2 VMOVSD	-0x238(%RBP),%XMM10

  (254) 0x4215fa VEXTRACTF64X4	$0x1,%ZMM15,%YMM5

  (254) 0x421601 MOV	%ECX,%R8D

  (254) 0x421604 VMOVSD	-0x240(%RBP),%XMM2

  (254) 0x42160c VMOVSD	-0x248(%RBP),%XMM1

  (254) 0x421614 VADDPD	%YMM15,%YMM5,%YMM12

  (254) 0x421619 VMOVSD	-0x250(%RBP),%XMM31

  (254) 0x421620 VEXTRACTF64X2	$0x1,%YMM12,%XMM8

  (254) 0x421627 VADDPD	%XMM12,%XMM8,%XMM11

  (254) 0x42162c VUNPCKHPD	%XMM11,%XMM11,%XMM3

  (254) 0x421631 VADDPD	%XMM11,%XMM3,%XMM3

  (254) 0x421636 CMP	%EDX,%ECX

  (254) 0x421638 JE	421c2f

  (254) 0x42163e MOV	%EDX,%R12D

  (254) 0x421641 SUB	%R8D,%R12D

  (254) 0x421644 LEA	-0x1(%R12),%R14D

  (254) 0x421649 CMP	$0x6,%R14D

  (254) 0x42164d JBE	4218f0

  (254) 0x421653 LEA	(%RSI,%R8,8),%R8

  (254) 0x421657 VBROADCASTSD	%XMM4,%YMM6

  (254) 0x42165c VBROADCASTSD	-0x68(%RBP),%YMM14

  (254) 0x421662 KMOVB	%K1,%K4

  (254) 0x421666 VMULPD	(%R8),%YMM6,%YMM5

  (254) 0x42166b VMULPD	0x20(%R8),%YMM6,%YMM6

  (254) 0x421671 VBROADCASTSD	%XMM7,%YMM30

  (254) 0x421677 VBROADCASTSD	%XMM0,%YMM19

  (254) 0x42167d VBROADCASTSD	%XMM10,%YMM26

  (254) 0x421683 VBROADCASTSD	%XMM9,%YMM12

  (254) 0x421688 VBROADCASTSD	-0x50(%RBP),%YMM24

  (254) 0x42168f VBROADCASTSD	-0x48(%RBP),%YMM13

  (254) 0x421695 VBROADCASTSD	%XMM1,%YMM16

  (254) 0x42169b VBROADCASTSD	%XMM2,%YMM25

  (254) 0x4216a1 VBROADCASTSD	-0x60(%RBP),%YMM15

  (254) 0x4216a7 VBROADCASTSD	-0x58(%RBP),%YMM23

  (254) 0x4216ae VBROADCASTSD	-0x70(%RBP),%YMM22

  (254) 0x4216b5 MOV	%R12D,%R13D

  (254) 0x4216b8 KMOVB	%K1,%K5

  (254) 0x4216bc AND	$-0x8,%R13D

  (254) 0x4216c0 VMOVAPD	%YMM14,-0xb0(%RBP)

  (254) 0x4216c8 KMOVB	%K1,%K7

  (254) 0x4216cc KMOVB	%K1,%K6

  (254) 0x4216d0 VBROADCASTSD	-0x200(%RBP),%YMM14

  (254) 0x4216d9 KMOVB	%K1,%K2

  (254) 0x4216dd ADD	%R13D,%ECX

  (254) 0x4216e0 AND	$0x7,%R12D

  (254) 0x4216e4 KMOVB	%K1,%K3

  (254) 0x4216e8 VRNDSCALEPD	$0xb,%YMM5,%YMM29

  (254) 0x4216ef VCVTTPD2DQ	%YMM5,%XMM27

  (254) 0x4216f5 VCVTTPD2DQ	%YMM6,%XMM8

  (254) 0x4216f9 VINSERTI32X4	$0x1,%XMM8,%YMM27,%YMM11

  (254) 0x421700 VGATHERDPD	(%RAX,%XMM27,8),%YMM28{%K4}

  (254) 0x421707 KMOVB	%K1,%K4

  (254) 0x42170b VRNDSCALEPD	$0xb,%YMM6,%YMM21

  (254) 0x421712 VSUBPD	%YMM29,%YMM5,%YMM8

  (254) 0x421718 VPERM2I128	$0x11,%YMM11,%YMM11,%YMM5

  (254) 0x42171e VGATHERDPD	(%RAX,%XMM5,8),%YMM29{%K5}

  (254) 0x421725 KMOVB	%K1,%K5

  (254) 0x421729 VMULPD	%YMM8,%YMM8,%YMM17

  (254) 0x42172f VSUBPD	%YMM21,%YMM6,%YMM6

  (254) 0x421735 VMULPD	%YMM17,%YMM8,%YMM18

  (254) 0x42173b VMULPD	%YMM30,%YMM17,%YMM27

  (254) 0x421741 VMULPD	%YMM6,%YMM6,%YMM20

  (254) 0x421747 VFMADD231PD	%YMM19,%YMM18,%YMM27

  (254) 0x42174d VMULPD	%YMM20,%YMM6,%YMM21

  (254) 0x421753 VMULPD	%YMM30,%YMM20,%YMM30

  (254) 0x421759 VFMADD132PD	%YMM21,%YMM30,%YMM19

  (254) 0x42175f VMOVAPD	%YMM8,%YMM30

  (254) 0x421765 VFMADD132PD	%YMM12,%YMM26,%YMM30

  (254) 0x42176b VFMADD132PD	%YMM6,%YMM26,%YMM12

  (254) 0x421771 VADDPD	%YMM19,%YMM12,%YMM12

  (254) 0x421777 VADDPD	%YMM27,%YMM30,%YMM26

  (254) 0x42177d VMULPD	%YMM15,%YMM17,%YMM27

  (254) 0x421783 VMULPD	%YMM15,%YMM20,%YMM15

  (254) 0x421789 VMULPD	%YMM29,%YMM12,%YMM12

  (254) 0x42178f VFMADD231PD	%YMM23,%YMM18,%YMM27

  (254) 0x421795 VFMADD231PD	%YMM23,%YMM21,%YMM15

  (254) 0x42179b VMOVAPD	%YMM8,%YMM23

  (254) 0x4217a1 VFMADD231PD	%YMM26,%YMM28,%YMM12

  (254) 0x4217a7 VMULPD	%YMM16,%YMM17,%YMM26

  (254) 0x4217ad VPADDD	-0x270(%RBP),%YMM11,%YMM28

  (254) 0x4217b7 VMULPD	%YMM16,%YMM20,%YMM16

  (254) 0x4217bd VMULPD	%YMM14,%YMM17,%YMM17

  (254) 0x4217c3 VMULPD	%YMM14,%YMM20,%YMM14

  (254) 0x4217c9 VFMADD231PD	%YMM25,%YMM18,%YMM26

  (254) 0x4217cf VFMADD231PD	%YMM25,%YMM21,%YMM16

  (254) 0x4217d5 VMOVAPD	%YMM8,%YMM25

  (254) 0x4217db VFMADD132PD	%YMM13,%YMM24,%YMM25

  (254) 0x4217e1 VFMADD132PD	%YMM6,%YMM24,%YMM13

  (254) 0x4217e7 VMOVDQA32	%YMM28,%YMM5

  (254) 0x4217ed VGATHERDPD	(%RAX,%XMM28,8),%YMM19{%K6}

  (254) 0x4217f4 VPERM2I128	$0x11,%YMM5,%YMM5,%YMM5

  (254) 0x4217fa VGATHERDPD	(%RAX,%XMM5,8),%YMM30{%K7}

  (254) 0x421801 VADDPD	%YMM16,%YMM13,%YMM13

  (254) 0x421807 VADDPD	%YMM26,%YMM25,%YMM24

  (254) 0x42180d VMULPD	%YMM30,%YMM13,%YMM5

  (254) 0x421813 VPADDD	0x1b67e5(%RIP),%YMM11,%YMM13

  (254) 0x42181b VPADDD	0x1b681d(%RIP),%YMM11,%YMM11

  (254) 0x421823 VFMADD132PD	%YMM24,%YMM5,%YMM19

  (254) 0x421829 VPERM2I128	$0x11,%YMM13,%YMM13,%YMM5

  (254) 0x42182f VADDPD	%YMM19,%YMM12,%YMM28

  (254) 0x421835 VGATHERDPD	(%RAX,%XMM13,8),%YMM12{%K2}

  (254) 0x42183c VGATHERDPD	(%RAX,%XMM5,8),%YMM13{%K3}

  (254) 0x421843 VMOVAPD	-0xb0(%RBP),%YMM5

  (254) 0x42184b VFMADD132PD	%YMM5,%YMM22,%YMM23

  (254) 0x421851 VFMADD132PD	%YMM6,%YMM22,%YMM5

  (254) 0x421857 VADDPD	%YMM15,%YMM5,%YMM15

  (254) 0x42185c VADDPD	%YMM27,%YMM23,%YMM22

  (254) 0x421862 VMULPD	%YMM13,%YMM15,%YMM5

  (254) 0x421867 VPERM2I128	$0x11,%YMM11,%YMM11,%YMM15

  (254) 0x42186d VGATHERDPD	(%RAX,%XMM15,8),%YMM13{%K5}

  (254) 0x421874 VBROADCASTSD	%XMM31,%YMM15

  (254) 0x42187a VFMADD231PD	%YMM22,%YMM12,%YMM5

  (254) 0x421880 VGATHERDPD	(%RAX,%XMM11,8),%YMM12{%K4}

  (254) 0x421887 VBROADCASTSD	-0x1f8(%RBP),%YMM11

  (254) 0x421890 VFMADD231PD	%YMM11,%YMM21,%YMM14

  (254) 0x421896 VFMADD132PD	%YMM11,%YMM17,%YMM18

  (254) 0x42189c VBROADCASTSD	-0x208(%RBP),%YMM11

  (254) 0x4218a5 VFMADD132PD	%YMM11,%YMM15,%YMM8

  (254) 0x4218aa VFMADD231PD	%YMM11,%YMM6,%YMM15

  (254) 0x4218af VADDPD	%YMM14,%YMM15,%YMM6

  (254) 0x4218b4 VADDPD	%YMM18,%YMM8,%YMM8

  (254) 0x4218ba VMULPD	%YMM13,%YMM6,%YMM13

  (254) 0x4218bf VFMADD132PD	%YMM8,%YMM13,%YMM12

  (254) 0x4218c4 VADDPD	%YMM12,%YMM5,%YMM5

  (254) 0x4218c9 VADDPD	%YMM28,%YMM5,%YMM12

  (254) 0x4218cf VEXTRACTF64X2	$0x1,%YMM12,%XMM14

  (254) 0x4218d6 VADDPD	%XMM12,%XMM14,%XMM11

  (254) 0x4218db VUNPCKHPD	%XMM11,%XMM11,%XMM15

  (254) 0x4218e0 VADDPD	%XMM11,%XMM15,%XMM8

  (254) 0x4218e5 VADDSD	%XMM8,%XMM3,%XMM3

  (254) 0x4218ea JE	421c2f

  (254) 0x4218f0 MOVSXD	%ECX,%RCX

  (254) 0x4218f3 VMOVAPD	%XMM9,%XMM15

  (254) 0x4218f8 VMULSD	(%RSI,%RCX,8),%XMM4,%XMM6

  (254) 0x4218fd VRNDSCALESD	$0xb,%XMM6,%XMM6,%XMM13

  (254) 0x421904 VSUBSD	%XMM13,%XMM6,%XMM5

  (254) 0x421909 VMULSD	%XMM5,%XMM5,%XMM14

  (254) 0x42190d VFMADD132SD	%XMM5,%XMM10,%XMM15

  (254) 0x421912 VMULSD	%XMM14,%XMM5,%XMM12

  (254) 0x421917 VMULSD	%XMM14,%XMM7,%XMM11

  (254) 0x42191c VMULSD	%XMM14,%XMM1,%XMM8

  (254) 0x421921 VFMADD231SD	%XMM12,%XMM0,%XMM11

  (254) 0x421926 VFMADD231SD	%XMM12,%XMM2,%XMM8

  (254) 0x42192b MOV	%RCX,%R12

  (254) 0x42192e VCVTTSD2SI	%XMM6,%R14D

  (254) 0x421932 NOT	%R12

  (254) 0x421935 MOVSXD	%R14D,%R8

  (254) 0x421938 LEA	0x1(%RCX),%R14

  (254) 0x42193c VMOVSD	-0x48(%RBP),%XMM13

  (254) 0x421941 ADD	%EDX,%R12D

  (254) 0x421944 VFMADD213SD	-0x50(%RBP),%XMM5,%XMM13

  (254) 0x42194a AND	$0x1,%R12D

  (254) 0x42194e VADDSD	%XMM11,%XMM15,%XMM6

  (254) 0x421953 VADDSD	%XMM13,%XMM8,%XMM11

  (254) 0x421958 VMULSD	-0x60(%RBP),%XMM14,%XMM8

  (254) 0x42195d VMULSD	0x8(%RAX,%R8,8),%XMM11,%XMM15

  (254) 0x421964 VFMADD231SD	-0x58(%RBP),%XMM12,%XMM8

  (254) 0x42196a VFMADD132SD	(%RAX,%R8,8),%XMM15,%XMM6

  (254) 0x421970 VMOVSD	-0x68(%RBP),%XMM13

  (254) 0x421975 VMULSD	-0x200(%RBP),%XMM14,%XMM14

  (254) 0x42197d VFMADD213SD	-0x70(%RBP),%XMM5,%XMM13

  (254) 0x421983 VFMADD132SD	-0x1f8(%RBP),%XMM14,%XMM12

  (254) 0x42198c VADDSD	%XMM8,%XMM13,%XMM11

  (254) 0x421991 VFMADD132SD	-0x208(%RBP),%XMM31,%XMM5

  (254) 0x421998 VADDSD	%XMM12,%XMM5,%XMM5

  (254) 0x42199d VMULSD	0x18(%RAX,%R8,8),%XMM5,%XMM12

  (254) 0x4219a4 VFMADD231SD	0x10(%RAX,%R8,8),%XMM11,%XMM12

  (254) 0x4219ab VADDSD	%XMM12,%XMM6,%XMM6

  (254) 0x4219b0 VADDSD	%XMM6,%XMM3,%XMM3

  (254) 0x4219b4 CMP	%R14D,%EDX

  (254) 0x4219b7 JLE	421c2f

  (254) 0x4219bd TEST	%R12D,%R12D

  (254) 0x4219c0 JE	421a83

  (254) 0x4219c6 VMOVAPD	%XMM9,%XMM11

  (254) 0x4219cb VMULSD	(%RSI,%R14,8),%XMM4,%XMM15

  (254) 0x4219d1 VRNDSCALESD	$0xb,%XMM15,%XMM15,%XMM8

  (254) 0x4219d8 VCVTTSD2SI	%XMM15,%R13D

  (254) 0x4219dd VSUBSD	%XMM8,%XMM15,%XMM14

  (254) 0x4219e2 VMULSD	%XMM14,%XMM14,%XMM5

  (254) 0x4219e7 VFMADD132SD	%XMM14,%XMM10,%XMM11

  (254) 0x4219ec VMULSD	%XMM5,%XMM14,%XMM12

  (254) 0x4219f0 VMULSD	%XMM5,%XMM7,%XMM13

  (254) 0x4219f4 VMULSD	%XMM5,%XMM1,%XMM15

  (254) 0x4219f8 VFMADD231SD	%XMM12,%XMM0,%XMM13

  (254) 0x4219fd VFMADD231SD	%XMM12,%XMM2,%XMM15

  (254) 0x421a02 MOVSXD	%R13D,%R12

  (254) 0x421a05 LEA	0x2(%RCX),%R14

  (254) 0x421a09 VMOVSD	-0x48(%RBP),%XMM8

  (254) 0x421a0e VFMADD213SD	-0x50(%RBP),%XMM14,%XMM8

  (254) 0x421a14 VADDSD	%XMM13,%XMM11,%XMM6

  (254) 0x421a19 VADDSD	%XMM8,%XMM15,%XMM13

  (254) 0x421a1e VMULSD	-0x60(%RBP),%XMM5,%XMM15

  (254) 0x421a23 VMULSD	0x8(%RAX,%R12,8),%XMM13,%XMM11

  (254) 0x421a2a VFMADD231SD	-0x58(%RBP),%XMM12,%XMM15

  (254) 0x421a30 VFMADD132SD	(%RAX,%R12,8),%XMM11,%XMM6

  (254) 0x421a36 VMOVSD	-0x68(%RBP),%XMM8

  (254) 0x421a3b VMULSD	-0x200(%RBP),%XMM5,%XMM5

  (254) 0x421a43 VFMADD213SD	-0x70(%RBP),%XMM14,%XMM8

  (254) 0x421a49 VFMADD132SD	-0x1f8(%RBP),%XMM5,%XMM12

  (254) 0x421a52 VADDSD	%XMM15,%XMM8,%XMM13

  (254) 0x421a57 VFMADD132SD	-0x208(%RBP),%XMM31,%XMM14

  (254) 0x421a5e VADDSD	%XMM12,%XMM14,%XMM14

  (254) 0x421a63 VMULSD	0x18(%RAX,%R12,8),%XMM14,%XMM12

  (254) 0x421a6a VFMADD231SD	0x10(%RAX,%R12,8),%XMM13,%XMM12

  (254) 0x421a71 VADDSD	%XMM12,%XMM6,%XMM6

  (254) 0x421a76 VADDSD	%XMM6,%XMM3,%XMM3

  (254) 0x421a7a CMP	%R14D,%EDX

  (254) 0x421a7d JLE	421c2f

  (254) 0x421a83 VMOVSD	-0x48(%RBP),%XMM12

  (254) 0x421a88 VMOVSD	-0x50(%RBP),%XMM13

  (254) 0x421a8d VMOVSD	-0x58(%RBP),%XMM14

  (254) 0x421a92 VMOVSD	-0x60(%RBP),%XMM15

  (254) 0x421a97 VMOVSD	-0x68(%RBP),%XMM30

  (254) 0x421a9e VMOVSD	-0x70(%RBP),%XMM26

  (254) 0x421aa5 VMOVSD	-0x1f8(%RBP),%XMM18

  (254) 0x421aac VMOVSD	-0x200(%RBP),%XMM16

  (254) 0x421ab3 VMOVSD	-0x208(%RBP),%XMM20

    (256) 0x421aba VMOVAPD	%XMM9,%XMM6

    (256) 0x421abe VMULSD	(%RSI,%R14,8),%XMM4,%XMM11

    (256) 0x421ac4 VRNDSCALESD	$0xb,%XMM11,%XMM11,%XMM8

    (256) 0x421acb VCVTTSD2SI	%XMM11,%ECX

    (256) 0x421ad0 VSUBSD	%XMM8,%XMM11,%XMM5

    (256) 0x421ad5 VMULSD	%XMM5,%XMM5,%XMM8

    (256) 0x421ad9 VFMADD132SD	%XMM5,%XMM10,%XMM6

    (256) 0x421ade VMULSD	%XMM8,%XMM5,%XMM21

    (256) 0x421ae4 VMULSD	%XMM8,%XMM7,%XMM11

    (256) 0x421ae9 VFMADD231SD	%XMM21,%XMM0,%XMM11

    (256) 0x421aef VMOVAPD	%XMM12,%XMM25

    (256) 0x421af5 MOVSXD	%ECX,%R8

    (256) 0x421af8 VFMADD132SD	%XMM5,%XMM13,%XMM25

    (256) 0x421afe VMULSD	%XMM8,%XMM15,%XMM24

    (256) 0x421b04 VFMADD231SD	%XMM21,%XMM14,%XMM24

    (256) 0x421b0a VMOVAPD	%XMM12,%XMM29

    (256) 0x421b10 VADDSD	%XMM11,%XMM6,%XMM6

    (256) 0x421b15 VMULSD	%XMM8,%XMM1,%XMM11

    (256) 0x421b1a VFMADD231SD	%XMM21,%XMM2,%XMM11

    (256) 0x421b20 VMULSD	%XMM8,%XMM16,%XMM8

    (256) 0x421b26 VFMADD132SD	%XMM18,%XMM8,%XMM21

    (256) 0x421b2c VADDSD	%XMM25,%XMM11,%XMM11

    (256) 0x421b32 VMULSD	0x8(%RAX,%R8,8),%XMM11,%XMM11

    (256) 0x421b39 VFMADD132SD	(%RAX,%R8,8),%XMM11,%XMM6

    (256) 0x421b3f VMOVAPD	%XMM30,%XMM11

    (256) 0x421b45 VFMADD132SD	%XMM5,%XMM26,%XMM11

    (256) 0x421b4b VFMADD132SD	%XMM20,%XMM31,%XMM5

    (256) 0x421b51 VADDSD	%XMM24,%XMM11,%XMM11

    (256) 0x421b57 VADDSD	%XMM21,%XMM5,%XMM5

    (256) 0x421b5d VMULSD	0x18(%RAX,%R8,8),%XMM5,%XMM8

    (256) 0x421b64 VFMADD231SD	0x10(%RAX,%R8,8),%XMM11,%XMM8

    (256) 0x421b6b VADDSD	%XMM8,%XMM6,%XMM6

    (256) 0x421b70 VADDSD	%XMM6,%XMM3,%XMM6

    (256) 0x421b74 VMULSD	0x8(%RSI,%R14,8),%XMM4,%XMM3

    (256) 0x421b7b VRNDSCALESD	$0xb,%XMM3,%XMM3,%XMM11

    (256) 0x421b82 VCVTTSD2SI	%XMM3,%R13D

    (256) 0x421b86 VSUBSD	%XMM11,%XMM3,%XMM5

    (256) 0x421b8b VMOVAPD	%XMM9,%XMM3

    (256) 0x421b8f VMULSD	%XMM5,%XMM5,%XMM8

    (256) 0x421b93 VFMADD132SD	%XMM5,%XMM10,%XMM3

    (256) 0x421b98 VMULSD	%XMM8,%XMM5,%XMM28

    (256) 0x421b9e VMULSD	%XMM8,%XMM7,%XMM11

    (256) 0x421ba3 VFMADD231SD	%XMM28,%XMM0,%XMM11

    (256) 0x421ba9 VFMADD132SD	%XMM5,%XMM13,%XMM29

    (256) 0x421baf MOVSXD	%R13D,%R12

    (256) 0x421bb2 VMULSD	%XMM8,%XMM15,%XMM19

    (256) 0x421bb8 VFMADD231SD	%XMM28,%XMM14,%XMM19

    (256) 0x421bbe ADD	$0x2,%R14

    (256) 0x421bc2 VADDSD	%XMM11,%XMM3,%XMM3

    (256) 0x421bc7 VMULSD	%XMM8,%XMM1,%XMM11

    (256) 0x421bcc VFMADD231SD	%XMM28,%XMM2,%XMM11

    (256) 0x421bd2 VMULSD	%XMM8,%XMM16,%XMM8

    (256) 0x421bd8 VFMADD132SD	%XMM18,%XMM8,%XMM28

    (256) 0x421bde VADDSD	%XMM29,%XMM11,%XMM11

    (256) 0x421be4 VMULSD	0x8(%RAX,%R12,8),%XMM11,%XMM11

    (256) 0x421beb VFMADD132SD	(%RAX,%R12,8),%XMM11,%XMM3

    (256) 0x421bf1 VMOVAPD	%XMM30,%XMM11

    (256) 0x421bf7 VFMADD132SD	%XMM5,%XMM26,%XMM11

    (256) 0x421bfd VFMADD132SD	%XMM20,%XMM31,%XMM5

    (256) 0x421c03 VADDSD	%XMM19,%XMM11,%XMM11

    (256) 0x421c09 VADDSD	%XMM28,%XMM5,%XMM5

    (256) 0x421c0f VMULSD	0x18(%RAX,%R12,8),%XMM5,%XMM8

    (256) 0x421c16 VFMADD231SD	0x10(%RAX,%R12,8),%XMM11,%XMM8

    (256) 0x421c1d VADDSD	%XMM8,%XMM3,%XMM3

    (256) 0x421c22 VADDSD	%XMM3,%XMM6,%XMM3

    (256) 0x421c26 CMP	%R14D,%EDX

    (256) 0x421c29 JG	421aba

  (254) 0x421c2f VADDSD	-0x210(%RBP),%XMM3,%XMM7

  (254) 0x421c37 VMOVSD	%XMM7,-0x210(%RBP)

  (254) 0x421c3f ADD	$0x4,%RDI

  (254) 0x421c43 CMP	%R9,%RDI

  (254) 0x421c46 JNE	420f40

(252) 0x421c4c VMOVQ	%R15,%XMM0

(252) 0x421c51 MOV	-0x278(%RBP),%R13

(252) 0x421c58 MOV	-0x280(%RBP),%R15

(252) 0x421c5f VSUBSD	-0x210(%RBP),%XMM0,%XMM5

(252) 0x421c67 VZEROUPPER

(252) 0x421c6a VMOVAPD	%XMM5,%XMM0

(252) 0x421c6e CALL	4040b0 <exp@plt>

(252) 0x421c73 MOV	(%R15),%RSI

(252) 0x421c76 MOV	0x8(%R15),%RDX

(252) 0x421c7a SUB	%RSI,%RDX

(252) 0x421c7d VMOVSD	%XMM0,(%RSI,%R13,8)

(252) 0x421c83 INC	%R13

(252) 0x421c86 SAR	$0x3,%RDX

(252) 0x421c8a CMP	%RDX,%R13

(252) 0x421c8d JB	420e80

0x421c93 ADD	$0x280,%RSP

0x421c9a POP	%RBX

0x421c9b POP	%RAX

0x421c9c POP	%R12

0x421c9e POP	%R13

0x421ca0 POP	%R14

0x421ca2 POP	%R15

0x421ca4 POP	%RBP

0x421ca5 LEA	-0x8(%RAX),%RSP

0x421ca9 RET

0x421caa NOPW	(%RAX,%RAX,1)

(252) 0x421cb0 MOV	0x90(%RBX),%R10D

(252) 0x421cb7 TEST	%R10D,%R10D

(252) 0x421cba JLE	421c6a

(252) 0x421cbc MOV	0xa0(%RBX),%RAX

(252) 0x421cc3 MOVSXD	%R10D,%RSI

(252) 0x421cc6 MOV	0x1c8(%RBX),%R14

(252) 0x421ccd MOV	%R12,%RDX

(252) 0x421cd0 VXORPD	%XMM8,%XMM8,%XMM8

(252) 0x421cd5 MOV	0x18(%RAX),%RAX

(252) 0x421cd9 LEA	(%RAX,%RSI,4),%R10

(252) 0x421cdd AND	$0x1,%ESI

(252) 0x421ce0 JE	421e1d

(252) 0x421ce6 MOVSXD	(%RAX),%RDX

(252) 0x421ce9 MOV	(%R14,%RDX,8),%RDI

(252) 0x421ced TEST	%RDI,%RDI

(252) 0x421cf0 JE	421e0b

(252) 0x421cf6 VMOVSD	(%R12),%XMM0

(252) 0x421cfc VCOMISD	0x8(%RDI),%XMM0

(252) 0x421d01 JAE	421e0b

(252) 0x421d07 VMULSD	0x238(%RDI),%XMM0,%XMM0

(252) 0x421d0f MOV	%RDI,-0xb0(%RBP)

(252) 0x421d16 LEA	-0x38(%RBP),%RDI

(252) 0x421d1a VMOVSD	%XMM5,-0x1b0(%RBP)

(252) 0x421d22 VMOVSD	%XMM8,-0x170(%RBP)

(252) 0x421d2a MOV	%R10,-0x130(%RBP)

(252) 0x421d31 MOV	%RAX,-0xf0(%RBP)

(252) 0x421d38 CALL	404310 <modf@plt>

(252) 0x421d3d MOV	-0xb0(%RBP),%RCX

(252) 0x421d44 MOV	-0x130(%RBP),%R10

(252) 0x421d4b MOV	-0xf0(%RBP),%RAX

(252) 0x421d52 VCVTTSD2SI	-0x38(%RBP),%R9D

(252) 0x421d57 MOVSXD	%R9D,%R11

(252) 0x421d5a VMULSD	%XMM0,%XMM0,%XMM4

(252) 0x421d5e VMOVSD	-0x170(%RBP),%XMM7

(252) 0x421d66 VMULSD	%XMM0,%XMM4,%XMM6

(252) 0x421d6a MOV	0x218(%RCX),%R8

(252) 0x421d71 VMULSD	0x20(%RCX),%XMM4,%XMM3

(252) 0x421d76 VMOVSD	0x28(%RCX),%XMM5

(252) 0x421d7b VFMADD231SD	0x18(%RCX),%XMM6,%XMM3

(252) 0x421d81 VFMADD213SD	0x30(%RCX),%XMM0,%XMM5

(252) 0x421d87 VMULSD	0x40(%RCX),%XMM4,%XMM9

(252) 0x421d8c VADDSD	%XMM5,%XMM3,%XMM8

(252) 0x421d90 VFMADD231SD	0x38(%RCX),%XMM6,%XMM9

(252) 0x421d96 VMOVSD	0x48(%RCX),%XMM10

(252) 0x421d9b VMULSD	0x60(%RCX),%XMM4,%XMM12

(252) 0x421da0 VFMADD213SD	0x50(%RCX),%XMM0,%XMM10

(252) 0x421da6 VFMADD231SD	0x58(%RCX),%XMM6,%XMM12

(252) 0x421dac VADDSD	%XMM10,%XMM9,%XMM11

(252) 0x421db1 VMOVSD	0x68(%RCX),%XMM13

(252) 0x421db6 VMULSD	0x80(%RCX),%XMM4,%XMM2

(252) 0x421dbe VFMADD213SD	0x70(%RCX),%XMM0,%XMM13

(252) 0x421dc4 VFMADD132SD	0x78(%RCX),%XMM2,%XMM6

(252) 0x421dca VADDSD	%XMM13,%XMM12,%XMM14

(252) 0x421dcf VMOVSD	0x90(%RCX),%XMM1

(252) 0x421dd7 VMOVSD	-0x1b0(%RBP),%XMM5

(252) 0x421ddf VFMADD132SD	(%R8,%R11,8),%XMM7,%XMM8

(252) 0x421de5 VMULSD	0x10(%R8,%R11,8),%XMM14,%XMM15

(252) 0x421dec VFMADD132SD	0x88(%RCX),%XMM1,%XMM0

(252) 0x421df5 VFMADD132SD	0x8(%R8,%R11,8),%XMM15,%XMM11

(252) 0x421dfc VADDSD	%XMM6,%XMM0,%XMM0

(252) 0x421e00 VFMADD132SD	0x18(%R8,%R11,8),%XMM8,%XMM0

(252) 0x421e07 VADDSD	%XMM0,%XMM11,%XMM8

(252) 0x421e0b ADD	$0x4,%RAX

(252) 0x421e0f LEA	0x8(%R12),%RDX

(252) 0x421e14 CMP	%RAX,%R10

(252) 0x421e17 JE	42207d

(252) 0x421e1d MOV	%R13,-0x170(%RBP)

(252) 0x421e24 MOV	%RBX,-0x1f0(%RBP)

(252) 0x421e2b MOV	%R15,-0x48(%RBP)

(252) 0x421e2f MOV	%R10,%R12

(252) 0x421e32 MOV	%RDX,%R13

(252) 0x421e35 MOV	%RAX,%RBX

(252) 0x421e38 MOV	%R14,%R15

(252) 0x421e3b VMOVSD	%XMM5,-0x1b0(%RBP)

  (253) 0x421e43 MOVSXD	(%RBX),%R14

  (253) 0x421e46 MOV	(%R15,%R14,8),%R14

  (253) 0x421e4a TEST	%R14,%R14

  (253) 0x421e4d JE	421f38

  (253) 0x421e53 VMOVSD	(%R13),%XMM4

  (253) 0x421e59 VCOMISD	0x8(%R14),%XMM4

  (253) 0x421e5f JAE	421f38

  (253) 0x421e65 LEA	-0x38(%RBP),%RDI

  (253) 0x421e69 VMOVSD	%XMM8,-0xb0(%RBP)

  (253) 0x421e71 VMULSD	0x238(%R14),%XMM4,%XMM0

  (253) 0x421e7a CALL	404310 <modf@plt>

  (253) 0x421e7f MOV	0x218(%R14),%RDI

  (253) 0x421e86 VCVTTSD2SI	-0x38(%RBP),%ESI

  (253) 0x421e8b MOVSXD	%ESI,%RCX

  (253) 0x421e8e VMULSD	%XMM0,%XMM0,%XMM3

  (253) 0x421e92 VMOVSD	0x28(%R14),%XMM8

  (253) 0x421e98 VMULSD	%XMM0,%XMM3,%XMM5

  (253) 0x421e9c VFMADD213SD	0x30(%R14),%XMM0,%XMM8

  (253) 0x421ea2 VMULSD	0x20(%R14),%XMM3,%XMM6

  (253) 0x421ea8 VMOVSD	-0xb0(%RBP),%XMM9

  (253) 0x421eb0 VFMADD231SD	0x18(%R14),%XMM5,%XMM6

  (253) 0x421eb6 VMULSD	0x40(%R14),%XMM3,%XMM10

  (253) 0x421ebc VADDSD	%XMM8,%XMM6,%XMM7

  (253) 0x421ec1 VFMADD231SD	0x38(%R14),%XMM5,%XMM10

  (253) 0x421ec7 VMOVSD	0x48(%R14),%XMM11

  (253) 0x421ecd VMULSD	0x60(%R14),%XMM3,%XMM13

  (253) 0x421ed3 VFMADD213SD	0x50(%R14),%XMM0,%XMM11

  (253) 0x421ed9 VFMADD231SD	0x58(%R14),%XMM5,%XMM13

  (253) 0x421edf VADDSD	%XMM11,%XMM10,%XMM12

  (253) 0x421ee4 VMOVSD	0x68(%R14),%XMM14

  (253) 0x421eea VFMADD132SD	(%RDI,%RCX,8),%XMM9,%XMM7

  (253) 0x421ef0 VFMADD213SD	0x70(%R14),%XMM0,%XMM14

  (253) 0x421ef6 VMULSD	0x80(%R14),%XMM3,%XMM1

  (253) 0x421eff VADDSD	%XMM14,%XMM13,%XMM15

  (253) 0x421f04 VFMADD132SD	0x78(%R14),%XMM1,%XMM5

  (253) 0x421f0a VMULSD	0x10(%RDI,%RCX,8),%XMM15,%XMM2

  (253) 0x421f10 VMOVSD	0x90(%R14),%XMM4

  (253) 0x421f19 VFMADD132SD	0x8(%RDI,%RCX,8),%XMM2,%XMM12

  (253) 0x421f20 VFMADD132SD	0x88(%R14),%XMM4,%XMM0

  (253) 0x421f29 VADDSD	%XMM5,%XMM0,%XMM0

  (253) 0x421f2d VFMADD132SD	0x18(%RDI,%RCX,8),%XMM7,%XMM0

  (253) 0x421f34 VADDSD	%XMM0,%XMM12,%XMM8

  (253) 0x421f38 LEA	0x4(%RBX),%R8

  (253) 0x421f3c MOVSXD	0x4(%RBX),%RBX

  (253) 0x421f40 LEA	0x8(%R13),%R9

  (253) 0x421f44 MOV	(%R15,%RBX,8),%R14

  (253) 0x421f48 TEST	%R14,%R14

  (253) 0x421f4b JE	422052

  (253) 0x421f51 VMOVSD	0x8(%R13),%XMM3

  (253) 0x421f57 VCOMISD	0x8(%R14),%XMM3

  (253) 0x421f5d JAE	422052

  (253) 0x421f63 LEA	-0x38(%RBP),%RDI

  (253) 0x421f67 VMOVSD	%XMM8,-0x130(%RBP)

  (253) 0x421f6f MOV	%R9,-0xf0(%RBP)

  (253) 0x421f76 MOV	%R8,-0xb0(%RBP)

  (253) 0x421f7d VMULSD	0x238(%R14),%XMM3,%XMM0

  (253) 0x421f86 CALL	404310 <modf@plt>

  (253) 0x421f8b MOV	0x218(%R14),%R13

  (253) 0x421f92 MOV	-0xf0(%RBP),%R9

  (253) 0x421f99 MOV	-0xb0(%RBP),%R8

  (253) 0x421fa0 VCVTTSD2SI	-0x38(%RBP),%EAX

  (253) 0x421fa5 CLTQ

  (253) 0x421fa7 VMULSD	%XMM0,%XMM0,%XMM8

  (253) 0x421fab VMOVSD	0x28(%R14),%XMM7

  (253) 0x421fb1 VMULSD	%XMM0,%XMM8,%XMM5

  (253) 0x421fb5 VMULSD	0x20(%R14),%XMM8,%XMM6

  (253) 0x421fbb VFMADD213SD	0x30(%R14),%XMM0,%XMM7

  (253) 0x421fc1 VFMADD231SD	0x18(%R14),%XMM5,%XMM6

  (253) 0x421fc7 VMULSD	0x40(%R14),%XMM8,%XMM11

  (253) 0x421fcd VMULSD	0x60(%R14),%XMM8,%XMM14

  (253) 0x421fd3 VFMADD231SD	0x38(%R14),%XMM5,%XMM11

  (253) 0x421fd9 VFMADD231SD	0x58(%R14),%XMM5,%XMM14

  (253) 0x421fdf VMULSD	0x80(%R14),%XMM8,%XMM4

  (253) 0x421fe8 VADDSD	%XMM7,%XMM6,%XMM9

  (253) 0x421fec VMOVSD	-0x130(%RBP),%XMM10

  (253) 0x421ff4 VMOVSD	0x48(%R14),%XMM12

  (253) 0x421ffa VFMADD132SD	(%R13,%RAX,8),%XMM10,%XMM9

  (253) 0x422001 VFMADD213SD	0x50(%R14),%XMM0,%XMM12

  (253) 0x422007 VMOVSD	0x68(%R14),%XMM15

  (253) 0x42200d VADDSD	%XMM12,%XMM11,%XMM13

  (253) 0x422012 VFMADD213SD	0x70(%R14),%XMM0,%XMM15

  (253) 0x422018 VFMADD132SD	0x78(%R14),%XMM4,%XMM5

  (253) 0x42201e VADDSD	%XMM15,%XMM14,%XMM2

  (253) 0x422023 VMOVSD	0x90(%R14),%XMM3

  (253) 0x42202c VMULSD	0x10(%R13,%RAX,8),%XMM2,%XMM1

  (253) 0x422033 VFMADD132SD	0x88(%R14),%XMM3,%XMM0

  (253) 0x42203c VFMADD132SD	0x8(%R13,%RAX,8),%XMM1,%XMM13

  (253) 0x422043 VADDSD	%XMM5,%XMM0,%XMM0

  (253) 0x422047 VFMADD132SD	0x18(%R13,%RAX,8),%XMM9,%XMM0

  (253) 0x42204e VADDSD	%XMM0,%XMM13,%XMM8

  (253) 0x422052 LEA	0x4(%R8),%RBX

  (253) 0x422056 LEA	0x8(%R9),%R13

  (253) 0x42205a CMP	%RBX,%R12

  (253) 0x42205d JNE	421e43

(252) 0x422063 MOV	-0x170(%RBP),%R13

(252) 0x42206a MOV	-0x1f0(%RBP),%RBX

(252) 0x422071 MOV	-0x48(%RBP),%R15

(252) 0x422075 VMOVSD	-0x1b0(%RBP),%XMM5

(252) 0x42207d VSUBSD	%XMM8,%XMM5,%XMM5

(252) 0x422082 JMP	421c6a

  (254) 0x422087 XOR	%R8D,%R8D

  (254) 0x42208a XOR	%ECX,%ECX

  (254) 0x42208c VXORPD	%XMM3,%XMM3,%XMM3

  (254) 0x422090 JMP	42163e

0x422095 VZEROUPPER

0x422098 JMP	421c93

0x42209d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.09+	qmcplusplus::WaveFunction::eva[...]		exec
○	main._omp_fn.1		exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.63 to 1.25 cycles (3.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
VPBROADCASTD: 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	38
nb uops	37
loop length	136
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50
cycles	1.67	1.67	1.67	1.67	1.67	1.67	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Dispatch	1.67
Overall L1	4.63

Vectorization ratios

all	30%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

all	17%
load	12%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.63 cycles. At this rate:

2% of peak load performance is reached (5.19 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.63 to 1.67 cycles (2.77x speedup).

ASM code

In the binary file, the address of the function is: 420e20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.71	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VPBROADCASTD %EAX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1	scal (6.3%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x280,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %YMM2,-0x270(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %RSI,-0x288(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %RCX,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 422095 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1275>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x280,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x8(%RAX),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 421c93 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xe73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.63 to 1.25 cycles (3.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
VPBROADCASTD: 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	38
nb uops	37
loop length	136
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50
cycles	1.67	1.67	1.67	1.67	1.67	1.67	1.25	1.25	1.25	1.25	0.00	0.50	0.50	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Dispatch	1.67
Overall L1	4.63

Vectorization ratios

all	30%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

all	17%
load	12%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.63 cycles. At this rate:

2% of peak load performance is reached (5.19 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 420e20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.71	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VPBROADCASTD %EAX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1	scal (6.3%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x280,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %YMM2,-0x270(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %RSI,-0x288(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %RCX,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 422095 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x1275>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x280,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x8(%RAX),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 421c93 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xe73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	0.03	0.04
▼Loop 252 - - exec–	0.01	0.01
▼Loop 254 - - exec–	0.00	0.01
○Loop 255 - - exec	0.01	0.02
○Loop 256 - - exec	0.00	0.01
○Loop 257 - - exec	0.00	0.00
○Loop 253 - - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code