OV - exec - Loop 828

	Loop Id: 828	Module: exec	Source: :0-0	Coverage: 0.13%

0x446d50 VPBROADCASTQ	%R14,%ZMM6

0x446d56 VPADDQ	%ZMM4,%ZMM6,%ZMM6

0x446d5c VPMULLQ	%ZMM6,%ZMM0,%ZMM6

0x446d62 VPADDQ	%ZMM5,%ZMM6,%ZMM6

0x446d68 VXORPD	%XMM7,%XMM7,%XMM7

0x446d6c KXNORW	%K0,%K0,%K1

0x446d70 VGATHERQPD	(%RCX,%ZMM6,8),%ZMM7{%K1}    [2]

0x446d77 VMOVUPD	%ZMM7,(%R10,%R14,8)    [1]

0x446d7e ADD	$0x8,%R14

0x446d82 CMP	%RDI,%R14

0x446d85 JBE	446d50

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►49.25+	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►47.47+	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.62+	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.51+	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	qmcplusplus::DiracMatrix::invert_transpose(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&, double&, double&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	7.13
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	6.67
Front-end cycles	7.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	4.75
P11 cycles	4.75
P12 cycles	4.75
P13 cycles	4.75
P14 cycles	5.50
P15 cycles	5.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	58.00
Nb loads	1.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.66
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	66.67
Vector-efficiency ratio all	76.79
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	45.83

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	qmcplusplus::DiracMatrix::invert_transpose(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&, double&, double&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	7.13
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	6.67
Front-end cycles	7.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	4.75
P11 cycles	4.75
P12 cycles	4.75
P13 cycles	4.75
P14 cycles	5.50
P15 cycles	5.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	58.00
Nb loads	1.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.66
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	66.67
Vector-efficiency ratio all	76.79
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	45.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::DiracMatrix::invert_transpose(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&, double&, double&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 76% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.25 to 6.67 cycles (1.09x speedup).

Details

85% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 1 occurrences►
VPBROADCASTQ: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 1 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	11
nb uops	58
loop length	55
used x86 registers	4
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	5
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.25	2.25	2.25	2.25	4.75	4.75	4.75	4.75	5.50	5.50
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.25	2.25	2.25	2.25	4.75	4.75	4.75	4.75	5.50	5.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.25
Dispatch	5.50
Data deps.	1.00
Overall L1	7.25

Vectorization ratios

INT

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

Vector efficiency ratios

INT

all	78%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	75%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

INT+FP

all	76%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

3% of peak load performance is reached (8.83 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.25 to 5.50 cycles (1.32x speedup).

ASM code

In the binary file, the address of the loop is: 446d50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R14,%ZMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ %ZMM4,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPMULLQ %ZMM6,%ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM5,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%RCX,%ZMM6,8),%ZMM7{%K1}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVUPD %ZMM7,(%R10,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 446d50 <_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_+0x160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::DiracMatrix::invert_transpose(qmcplusplus::Matrix > const&, qmcplusplus::Matrix >&, double&, double&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Details

85% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 1 occurrences►
VPBROADCASTQ: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 1 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	11
nb uops	58
loop length	55
used x86 registers	4
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	5
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.25 cycles
front end	7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.25	2.25	2.25	2.25	4.75	4.75	4.75	4.75	5.50	5.50
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.25	2.25	2.25	2.25	4.75	4.75	4.75	4.75	5.50	5.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.25
Dispatch	5.50
Data deps.	1.00
Overall L1	7.25

Vectorization ratios

INT

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

Vector efficiency ratios

INT

all	78%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	75%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

INT+FP

all	76%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

3% of peak load performance is reached (8.83 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 446d50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R14,%ZMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ %ZMM4,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPMULLQ %ZMM6,%ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM5,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERQPD (%RCX,%ZMM6,8),%ZMM7{%K1}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVUPD %ZMM7,(%R10,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 446d50 <_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_+0x160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code