OV - exec - Loop 753

	Loop Id: 753	Module: exec	Source: :0-0	Coverage: 10.03%

0x43f1a0 VMOVUPD	(%R11,%R15,8),%ZMM21    [4]

0x43f1a7 VMOVUPD	(%R8,%R15,8),%ZMM22    [1]

0x43f1ae VMOVUPD	(%R9,%R15,8),%ZMM23    [2]

0x43f1b5 VMOVUPD	(%R14,%R15,8),%ZMM24    [3]

0x43f1bc VMULPD	%ZMM0,%ZMM21,%ZMM25

0x43f1c2 VFMADD231PD	%ZMM1,%ZMM22,%ZMM25

0x43f1c8 VFMADD231PD	%ZMM2,%ZMM23,%ZMM25

0x43f1ce VFMADD231PD	%ZMM24,%ZMM3,%ZMM25

0x43f1d4 VMULPD	%ZMM4,%ZMM21,%ZMM26

0x43f1da VMULPD	%ZMM5,%ZMM22,%ZMM27

0x43f1e0 VFMADD231PD	%ZMM7,%ZMM24,%ZMM27

0x43f1e6 VFMADD231PD	%ZMM6,%ZMM23,%ZMM26

0x43f1ec VFMADD231PD	%ZMM27,%ZMM8,%ZMM26

0x43f1f2 VMULPD	%ZMM9,%ZMM21,%ZMM21

0x43f1f8 VFMADD231PD	%ZMM22,%ZMM10,%ZMM21

0x43f1fe VFMADD231PD	%ZMM23,%ZMM11,%ZMM21

0x43f204 VFMADD231PD	%ZMM24,%ZMM8,%ZMM21

0x43f20a LEA	(%R13,%R15,8),%RDX

0x43f20f VMOVUPD	(%R13,%R15,8),%ZMM22    [6]

0x43f217 VFMADD231PD	%ZMM25,%ZMM20,%ZMM22

0x43f21d VMOVUPD	%ZMM22,(%R13,%R15,8)    [6]

0x43f225 VMOVUPD	(%RSI,%RDX,1),%ZMM22    [10]

0x43f22c VFMADD231PD	%ZMM25,%ZMM19,%ZMM22

0x43f232 VMOVUPD	%ZMM22,(%RSI,%RDX,1)    [10]

0x43f239 LEA	(%RDX,%RSI,1),%RDX

0x43f23d VMOVUPD	(%RSI,%RDX,1),%ZMM22    [10]

0x43f244 VFMADD231PD	%ZMM17,%ZMM26,%ZMM22

0x43f24a VMOVUPD	%ZMM22,(%RSI,%RDX,1)    [10]

0x43f251 LEA	(%RDX,%RSI,1),%RDX

0x43f255 VMOVUPD	(%RSI,%RDX,1),%ZMM22    [10]

0x43f25c VFMADD231PD	%ZMM25,%ZMM18,%ZMM22

0x43f262 VMOVUPD	%ZMM22,(%RSI,%RDX,1)    [10]

0x43f269 LEA	(%RDX,%RSI,1),%RDX

0x43f26d VMOVUPD	(%RSI,%RDX,1),%ZMM22    [10]

0x43f274 VFMADD231PD	%ZMM16,%ZMM26,%ZMM22

0x43f27a VMOVUPD	%ZMM22,(%RSI,%RDX,1)    [10]

0x43f281 LEA	(%RDX,%RSI,1),%RDX

0x43f285 VFMADD213PD	(%RSI,%RDX,1),%ZMM15,%ZMM21    [10]

0x43f28c VMOVUPD	%ZMM21,(%RSI,%RDX,1)    [10]

0x43f293 VMOVUPD	(%RBP,%R15,8),%ZMM21    [5]

0x43f29b VFMADD231PD	%ZMM17,%ZMM25,%ZMM21

0x43f2a1 VMOVUPD	%ZMM21,(%RBP,%R15,8)    [5]

0x43f2a9 VMOVUPD	(%RAX,%R15,8),%ZMM21    [7]

0x43f2b0 VFMADD231PD	%ZMM16,%ZMM25,%ZMM21

0x43f2b6 VMOVUPD	%ZMM21,(%RAX,%R15,8)    [7]

0x43f2bd VFMADD213PD	(%RCX,%R15,8),%ZMM15,%ZMM26    [8]

0x43f2c4 VMOVUPD	%ZMM26,(%RCX,%R15,8)    [8]

0x43f2cb VFMADD213PD	(%RBX,%R15,8),%ZMM15,%ZMM25    [9]

0x43f2d2 VMOVUPD	%ZMM25,(%RBX,%R15,8)    [9]

0x43f2d9 ADD	$0x8,%R15

0x43f2dd CMP	%RDI,%R15

0x43f2e0 JL	43f1a0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►80.30+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►7.28+	qmcplusplus::SPOSet::evaluate_[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►6.96+	qmcplusplus::SPOSet::evaluate_[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.52+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.31+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	P10, P11,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	6.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	11.50
P11 cycles	11.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00
P15 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	14.00
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	29.22
Nb FLOP add-sub	0.00
Nb FLOP mul	32.00
Nb FLOP fma	152.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	133.57
Bytes prefetched	0.00
Bytes loaded	896.00
Bytes stored	640.00
Stride 0	0.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	P10, P11,
Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	6.38
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	11.50
P11 cycles	11.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00
P15 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	14.00
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	29.22
Nb FLOP add-sub	0.00
Nb FLOP mul	32.00
Nb FLOP fma	152.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	133.57
Bytes prefetched	0.00
Bytes loaded	896.00
Bytes stored	640.00
Stride 0	0.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 6.38 cycles (1.80x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 152 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 21 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 21 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

23 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 336 FP arithmetical operations:

152: addition or subtraction (all inside FMA instructions)
184: multiply (152 inside FMA instructions)

The binary loop is loading 896 bytes (112 double precision FP elements). The binary loop is storing 640 bytes (80 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	52
nb uops	51
loop length	326
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	25
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	6.00	6.00	6.00	6.00	11.50	11.50	0.00	0.00	5.00	5.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	6.00	6.00	6.00	6.00	11.50	11.50	0.00	0.00	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Dispatch	11.50
Data deps.	1.00
Overall L1	11.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

30% of peak load performance is reached (77.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (55.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43f1a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11,%R15,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R8,%R15,8),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R9,%R15,8),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R14,%R15,8),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM21,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM22,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM23,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM24,%ZMM3,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM21,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM22,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM24,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM8,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM10,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM11,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM24,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LEA (%R13,%R15,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R13,%R15,8),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM20,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%R13,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM26,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM16,%ZMM26,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RSI,%RDX,1),%ZMM15,%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM21,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RBP,%R15,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM21,(%RBP,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RAX,%R15,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM16,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM21,(%RAX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD213PD (%RCX,%R15,8),%ZMM15,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM26,(%RCX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD213PD (%RBX,%R15,8),%ZMM15,%ZMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM25,(%RBX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 43f1a0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xef0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator > >&, qmcplusplus::Vector >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 152 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 21 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 21 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

23 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 336 FP arithmetical operations:

152: addition or subtraction (all inside FMA instructions)
184: multiply (152 inside FMA instructions)

The binary loop is loading 896 bytes (112 double precision FP elements). The binary loop is storing 640 bytes (80 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	52
nb uops	51
loop length	326
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	25
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	6.00	6.00	6.00	6.00	11.50	11.50	0.00	0.00	5.00	5.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	6.00	6.00	6.00	6.00	11.50	11.50	0.00	0.00	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Dispatch	11.50
Data deps.	1.00
Overall L1	11.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

30% of peak load performance is reached (77.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (55.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 43f1a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11,%R15,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R8,%R15,8),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R9,%R15,8),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R14,%R15,8),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM21,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM22,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM23,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM24,%ZMM3,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM4,%ZMM21,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM22,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM24,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM8,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM10,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM11,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM24,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LEA (%R13,%R15,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R13,%R15,8),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM20,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%R13,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM26,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RSI,%RDX,1),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM16,%ZMM26,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM22,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RDX,%RSI,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RSI,%RDX,1),%ZMM15,%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM21,(%RSI,%RDX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RBP,%R15,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM21,(%RBP,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RAX,%R15,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM16,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM21,(%RAX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD213PD (%RCX,%R15,8),%ZMM15,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM26,(%RCX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD213PD (%RBX,%R15,8),%ZMM15,%ZMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM25,(%RBX,%R15,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 43f1a0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xef0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code