OV - exec - Loop 325

	Loop Id: 325	Module: exec	Source: :0-0	Coverage: 0.04%

0x4216e0 VMULPD	(%RDX,%R14,8),%ZMM20,%ZMM22    [2]

0x4216e7 VCVTTPD2DQ	%ZMM22,%YMM23

0x4216ed VRNDSCALEPD	$0xb,%ZMM22,%ZMM24

0x4216f4 VSUBPD	%ZMM24,%ZMM22,%ZMM22

0x4216fa VXORPD	%XMM24,%XMM24,%XMM24

0x421700 KXNORW	%K0,%K0,%K1

0x421704 VGATHERDPD	(%R11,%YMM23,8),%ZMM24{%K1}    [1]

0x42170b VXORPD	%XMM25,%XMM25,%XMM25

0x421711 KXNORW	%K0,%K0,%K1

0x421715 VGATHERDPD	0x8(%R11,%YMM23,8),%ZMM25{%K1}    [1]

0x42171d VXORPD	%XMM26,%XMM26,%XMM26

0x421723 KXNORW	%K0,%K0,%K1

0x421727 VGATHERDPD	0x10(%R11,%YMM23,8),%ZMM26{%K1}    [1]

0x42172f VXORPD	%XMM27,%XMM27,%XMM27

0x421735 KXNORW	%K0,%K0,%K1

0x421739 VGATHERDPD	0x18(%R11,%YMM23,8),%ZMM27{%K1}    [1]

0x421741 VMOVAPD	%ZMM22,%ZMM23

0x421747 VFMADD213PD	%ZMM2,%ZMM4,%ZMM23

0x42174d VFMADD213PD	%ZMM6,%ZMM22,%ZMM23

0x421753 VFMADD213PD	%ZMM5,%ZMM22,%ZMM23

0x421759 VFMADD213PD	%ZMM21,%ZMM24,%ZMM23

0x42175f VMOVAPD	%ZMM22,%ZMM21

0x421765 VFMADD213PD	%ZMM12,%ZMM13,%ZMM21

0x42176b VFMADD213PD	%ZMM15,%ZMM22,%ZMM21

0x421771 VFMADD213PD	%ZMM14,%ZMM22,%ZMM21

0x421777 VFMADD213PD	%ZMM23,%ZMM25,%ZMM21

0x42177d VMOVAPD	%ZMM22,%ZMM23

0x421783 VFMADD213PD	%ZMM3,%ZMM7,%ZMM23

0x421789 VFMADD213PD	%ZMM10,%ZMM22,%ZMM23

0x42178f VFMADD213PD	%ZMM9,%ZMM22,%ZMM23

0x421795 VFMADD213PD	%ZMM21,%ZMM26,%ZMM23

0x42179b VMOVAPD	%ZMM22,%ZMM21

0x4217a1 VFMADD213PD	%ZMM8,%ZMM16,%ZMM21

0x4217a7 VFMADD213PD	%ZMM18,%ZMM22,%ZMM21

0x4217ad VFMADD213PD	%ZMM17,%ZMM22,%ZMM21

0x4217b3 VFMADD213PD	%ZMM23,%ZMM27,%ZMM21

0x4217b9 ADD	$0x8,%R14

0x4217bd CMP	%R9,%R14

0x4217c0 JB	4216e0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►94.82+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.74+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.38
CQA cycles if no scalar integer	26.88
CQA cycles if FP arith vectorized	27.38
CQA cycles if fully vectorized	27.38
Front-end cycles	27.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	8.25
P7 cycles	8.25
P8 cycles	8.25
P9 cycles	8.25
P10 cycles	19.25
P11 cycles	19.25
P12 cycles	19.25
P13 cycles	19.25
P14 cycles	20.00
P15 cycles	20.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	219.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.94
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	128.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.69
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	90.63
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	78.57

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.38
CQA cycles if no scalar integer	26.88
CQA cycles if FP arith vectorized	27.38
CQA cycles if fully vectorized	27.38
Front-end cycles	27.38
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	8.25
P7 cycles	8.25
P8 cycles	8.25
P9 cycles	8.25
P10 cycles	19.25
P11 cycles	19.25
P12 cycles	19.25
P13 cycles	19.25
P14 cycles	20.00
P15 cycles	20.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	219.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.94
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	128.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.69
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	90.63
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	78.57

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 90% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 128 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences►
VGATHERDPD: 4 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

19 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 272 FP arithmetical operations:

136: addition or subtraction (128 inside FMA instructions)
136: multiply (128 inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.85 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	219
loop length	230
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	27.38 cycles
front end	27.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	8.25	8.25	8.25	8.25	19.25	19.25	19.25	19.25	20.00	20.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	8.25	8.25	8.25	8.25	19.25	19.25	19.25	19.25	20.00	20.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	27.38
Dispatch	20.00
Data deps.	16.00
Overall L1	27.38

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.38 cycles. At this rate:

4% of peak load performance is reached (11.69 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.38 to 20.00 cycles (1.37x speedup).

ASM code

In the binary file, the address of the loop is: 4216e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD (%RDX,%R14,8),%ZMM20,%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM22,%YMM23	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM22,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM24,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%R11,%YMM23,8),%ZMM24{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD 0x8(%R11,%YMM23,8),%ZMM25{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD 0x10(%R11,%YMM23,8),%ZMM26{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD 0x18(%R11,%YMM23,8),%ZMM27{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM2,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM6,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM5,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM21,%ZMM24,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM12,%ZMM13,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM15,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM14,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM23,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM3,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM10,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM21,%ZMM26,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM8,%ZMM16,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM18,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM17,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM23,%ZMM27,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4216e0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x3a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 90% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 128 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences►
VGATHERDPD: 4 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

19 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 272 FP arithmetical operations:

136: addition or subtraction (128 inside FMA instructions)
136: multiply (128 inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.85 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	219
loop length	230
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	27.38 cycles
front end	27.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	8.25	8.25	8.25	8.25	19.25	19.25	19.25	19.25	20.00	20.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	8.25	8.25	8.25	8.25	19.25	19.25	19.25	19.25	20.00	20.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	27.38
Dispatch	20.00
Data deps.	16.00
Overall L1	27.38

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.38 cycles. At this rate:

4% of peak load performance is reached (11.69 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4216e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD (%RDX,%R14,8),%ZMM20,%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM22,%YMM23	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM22,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM24,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%R11,%YMM23,8),%ZMM24{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD 0x8(%R11,%YMM23,8),%ZMM25{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD 0x10(%R11,%YMM23,8),%ZMM26{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD 0x18(%R11,%YMM23,8),%ZMM27{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM2,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM6,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM5,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM21,%ZMM24,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM12,%ZMM13,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM15,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM14,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM23,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM3,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM10,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM22,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM21,%ZMM26,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM8,%ZMM16,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM18,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM17,%ZMM22,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM23,%ZMM27,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4216e0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x3a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code