OV - exec - Loop 280

	Loop Id: 280	Module: exec	Source: :0-0	Coverage: 0.19%

0x41d160 VMOVUPD	(%R12,%R13,8),%ZMM4    [2]

0x41d167 LEA	(%R15,%R13,1),%EBP

0x41d16b VPBROADCASTD	%EBP,%YMM5

0x41d171 VPADDD	%YMM3,%YMM5,%YMM5

0x41d175 VPCMPNEQD	%YMM1,%YMM5,%K1

0x41d17c VCMPPD	$0x1,%ZMM2,%ZMM4,%K1{%K1}

0x41d183 VPBROADCASTD	%R13D,%YMM5

0x41d189 VPADDD	%YMM3,%YMM5,%YMM5

0x41d18d MOVSXD	%EBX,%RBX

0x41d190 VPCOMPRESSD	%YMM5,(%RAX,%RBX,4){%K1}    [3]

0x41d197 VCOMPRESSPD	%ZMM4,(%R10,%RBX,8){%K1}    [1]

0x41d19e KMOVB	%K1,%EBP

0x41d1a2 POPCNT	%EBP,%EBP

0x41d1a6 ADD	%EBP,%EBX

0x41d1a8 ADD	$0x8,%R13

0x41d1ac CMP	%R14,%R13

0x41d1af JB	41d160

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►62.61+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::acc[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►26.56+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►4.77+	miniqmcreference::TwoBodyJastr[...]	exec
○	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.82+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::acc[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.22+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::acc[...]	exec
○	main.extracted.109	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.27
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.88
CQA cycles if no scalar integer	23.38
CQA cycles if FP arith vectorized	23.88
CQA cycles if fully vectorized	17.12
Front-end cycles	23.88
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	3.25
P11 cycles	3.25
P12 cycles	3.50
P13 cycles	3.00
P14 cycles	10.50
P15 cycles	10.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	191.00
Nb loads	1.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.70
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	70.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	51.88
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.75

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.27
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.88
CQA cycles if no scalar integer	23.38
CQA cycles if FP arith vectorized	23.88
CQA cycles if fully vectorized	17.12
Front-end cycles	23.88
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	3.25
P11 cycles	3.25
P12 cycles	3.50
P13 cycles	3.00
P14 cycles	10.50
P15 cycles	10.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	191.00
Nb loads	1.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.70
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	70.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	51.88
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 51% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 23.88 to 17.12 cycles (1.39x speedup).

Details

70% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMPRESSPD: 1 occurrences►
VPBROADCASTD: 2 occurrences►
VPCOMPRESSD: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

General properties

nb instructions	17
nb uops	191
loop length	81
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	2
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	23.88 cycles
front end	23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.50	3.00	10.50	10.50
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.50	3.00	10.50	10.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	23.88
Dispatch	10.50
Data deps.	2.00
Overall L1	23.88

Vectorization ratios

INT

all	57%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	70%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	51%
load	100%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.88 cycles. At this rate:

1% of peak load performance is reached (2.68 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.02 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.88 to 10.50 cycles (2.27x speedup).

ASM code

In the binary file, the address of the loop is: 41d160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R12,%R13,8),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
LEA (%R15,%R13,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPBROADCASTD %EBP,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPNEQD %YMM1,%YMM5,%K1																				vect (50.0%)
VCMPPD $0x1,%ZMM2,%ZMM4,%K1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VPBROADCASTD %R13D,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
MOVSXD %EBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPCOMPRESSD %YMM5,(%RAX,%RBX,4){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	38-54	54	vect (50.0%)
VCOMPRESSPD %ZMM4,(%R10,%RBX,8){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	8	54	vect (100.0%)
KMOVB %K1,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
POPCNT %EBP,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBP,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 41d160 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x70>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Details

70% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMPRESSPD: 1 occurrences►
VPBROADCASTD: 2 occurrences►
VPCOMPRESSD: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	17
nb uops	191
loop length	81
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	2
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	23.88 cycles
front end	23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.50	3.00	10.50	10.50
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.50	3.00	10.50	10.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	23.88
Dispatch	10.50
Data deps.	2.00
Overall L1	23.88

Vectorization ratios

INT

all	57%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	70%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	51%
load	100%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.88 cycles. At this rate:

1% of peak load performance is reached (2.68 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.02 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41d160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R12,%R13,8),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
LEA (%R15,%R13,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPBROADCASTD %EBP,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPNEQD %YMM1,%YMM5,%K1																				vect (50.0%)
VCMPPD $0x1,%ZMM2,%ZMM4,%K1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
VPBROADCASTD %R13D,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
MOVSXD %EBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPCOMPRESSD %YMM5,(%RAX,%RBX,4){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	38-54	54	vect (50.0%)
VCOMPRESSPD %ZMM4,(%R10,%RBX,8){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	8	54	vect (100.0%)
KMOVB %K1,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
POPCNT %EBP,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBP,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 41d160 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x70>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

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Vectorization

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Execution units bottlenecks

Masked instructions

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Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code