OV - exec - Loop 278

	Loop Id: 278	Module: exec	Source: :0-0	Coverage: 0.02%

0x41d4d0 VMOVUPD	(%R10,%RDI,8),%ZMM20    [3]

0x41d4d7 VMULPD	%ZMM20,%ZMM16,%ZMM21

0x41d4dd VRNDSCALEPD	$0xb,%ZMM21,%ZMM10

0x41d4e4 VSUBPD	%ZMM10,%ZMM21,%ZMM10

0x41d4ea VCVTTPD2DQ	%ZMM21,%YMM21

0x41d4f0 KXNORW	%K0,%K0,%K1

0x41d4f4 VXORPD	%XMM23,%XMM23,%XMM23

0x41d4fa KXNORW	%K0,%K0,%K2

0x41d4fe VGATHERDPD	(%R8,%YMM21,8),%ZMM23{%K1}    [1]

0x41d505 VXORPD	%XMM22,%XMM22,%XMM22

0x41d50b VGATHERDPD	0x8(%R8,%YMM21,8),%ZMM22{%K2}    [1]

0x41d513 VMOVAPD	%ZMM10,%ZMM24

0x41d519 VMOVAPD	%ZMM10,%ZMM25

0x41d51f VMOVUPD	0x600(%RSP),%ZMM0    [5]

0x41d527 VFMADD132PD	0x680(%RSP),%ZMM0,%ZMM24    [5]

0x41d52f VFMADD213PD	0x280(%RSP),%ZMM10,%ZMM24    [5]

0x41d537 VMOVAPD	%ZMM10,%ZMM26

0x41d53d VMULPD	%ZMM23,%ZMM24,%ZMM24

0x41d543 VMOVUPD	0x540(%RSP),%ZMM0    [5]

0x41d54b VFMADD213PD	0x5c0(%RSP),%ZMM0,%ZMM26    [5]

0x41d553 VFMADD213PD	0x580(%RSP),%ZMM10,%ZMM26    [5]

0x41d55b VFMADD213PD	%ZMM24,%ZMM22,%ZMM26

0x41d561 VMOVAPD	%ZMM10,%ZMM24

0x41d567 VMOVUPD	0x180(%RSP),%ZMM0    [5]

0x41d56f VFMADD132PD	0x240(%RSP),%ZMM0,%ZMM24    [5]

0x41d577 VMULPD	%ZMM23,%ZMM24,%ZMM24

0x41d57d VMOVUPD	0x1c0(%RSP),%ZMM0    [5]

0x41d585 VFMADD213PD	0x140(%RSP),%ZMM0,%ZMM25    [5]

0x41d58d VFMADD213PD	%ZMM24,%ZMM22,%ZMM25

0x41d593 VMOVAPD	%ZMM10,%ZMM24

0x41d599 VFMADD213PD	%ZMM11,%ZMM27,%ZMM24

0x41d59f VFMADD213PD	%ZMM13,%ZMM10,%ZMM24

0x41d5a5 VFMADD213PD	%ZMM31,%ZMM10,%ZMM24

0x41d5ab VMULPD	%ZMM23,%ZMM24,%ZMM23

0x41d5b1 VMOVAPD	%ZMM10,%ZMM24

0x41d5b7 VFMADD213PD	%ZMM3,%ZMM30,%ZMM24

0x41d5bd VFMADD213PD	%ZMM17,%ZMM10,%ZMM24

0x41d5c3 VFMADD213PD	%ZMM4,%ZMM10,%ZMM24

0x41d5c9 VFMADD213PD	%ZMM23,%ZMM22,%ZMM24

0x41d5cf VMOVAPD	%ZMM10,%ZMM22

0x41d5d5 KXNORW	%K0,%K0,%K1

0x41d5d9 VXORPD	%XMM23,%XMM23,%XMM23

0x41d5df VGATHERDPD	0x10(%R8,%YMM21,8),%ZMM23{%K1}    [1]

0x41d5e7 VFMADD132PD	0x2c0(%RSP),%ZMM5,%ZMM22    [5]

0x41d5ef VFMADD213PD	%ZMM12,%ZMM10,%ZMM22

0x41d5f5 VFMADD213PD	%ZMM26,%ZMM23,%ZMM22

0x41d5fb VMOVAPD	%ZMM10,%ZMM26

0x41d601 VMOVUPD	0x6c0(%RSP),%ZMM0    [5]

0x41d609 VFMADD132PD	0x200(%RSP),%ZMM0,%ZMM26    [5]

0x41d611 VFMADD213PD	%ZMM25,%ZMM23,%ZMM26

0x41d617 VMOVAPD	%ZMM10,%ZMM25

0x41d61d VFMADD213PD	%ZMM2,%ZMM29,%ZMM25

0x41d623 VFMADD213PD	%ZMM9,%ZMM10,%ZMM25

0x41d629 VFMADD213PD	%ZMM15,%ZMM10,%ZMM25

0x41d62f VFMADD213PD	%ZMM24,%ZMM23,%ZMM25

0x41d635 KXNORW	%K0,%K0,%K1

0x41d639 VXORPD	%XMM23,%XMM23,%XMM23

0x41d63f VGATHERDPD	0x18(%R8,%YMM21,8),%ZMM23{%K1}    [1]

0x41d647 VMOVAPD	%ZMM10,%ZMM21

0x41d64d VFMADD213PD	%ZMM1,%ZMM14,%ZMM21

0x41d653 VFMADD213PD	%ZMM8,%ZMM10,%ZMM21

0x41d659 VFMADD213PD	%ZMM22,%ZMM23,%ZMM21

0x41d65f VMOVAPD	%ZMM10,%ZMM22

0x41d665 VFMADD213PD	%ZMM18,%ZMM28,%ZMM22

0x41d66b VFMADD213PD	%ZMM19,%ZMM10,%ZMM22

0x41d671 VFMADD213PD	%ZMM6,%ZMM10,%ZMM22

0x41d677 VFMADD213PD	%ZMM25,%ZMM23,%ZMM22

0x41d67d VMOVUPD	0x500(%RSP),%ZMM0    [5]

0x41d685 VFMADD213PD	0x640(%RSP),%ZMM0,%ZMM10    [5]

0x41d68d VFMADD213PD	%ZMM26,%ZMM23,%ZMM10

0x41d693 VMULPD	%ZMM16,%ZMM21,%ZMM21

0x41d699 VDIVPD	%ZMM20,%ZMM21,%ZMM20

0x41d69f VPMOVSXDQ	(%RAX,%RDI,4),%ZMM21    [6]

0x41d6a6 VMULPD	0x700(%RSP),%ZMM10,%ZMM10    [5]

0x41d6ae VPADDQ	%ZMM21,%ZMM7,%ZMM21

0x41d6b4 KXNORW	%K0,%K0,%K1

0x41d6b8 VSCATTERQPD	%ZMM10,(%RDX,%ZMM21,8){%K1}    [7]

0x41d6bf KXNORW	%K0,%K0,%K1

0x41d6c3 VSCATTERQPD	%ZMM20,(%RSI,%ZMM21,8){%K1}    [4]

0x41d6ca KXNORW	%K0,%K0,%K1

0x41d6ce VSCATTERQPD	%ZMM22,(%R9,%ZMM21,8){%K1}    [2]

0x41d6d5 ADD	$0x8,%RDI

0x41d6d9 CMP	%RCX,%RDI

0x41d6dc JB	41d4d0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►51.73+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►38.10+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::acc[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►4.46+	miniqmcreference::TwoBodyJastr[...]	exec
○	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.38+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::acc[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.38+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.13+	miniqmcreference::TwoBodyJastr[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.63
CQA cycles if no scalar integer	49.75
CQA cycles if FP arith vectorized	50.63
CQA cycles if fully vectorized	50.32
Front-end cycles	50.63
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	18.50
P7 cycles	18.50
P8 cycles	18.50
P9 cycles	18.50
P10 cycles	32.25
P11 cycles	32.25
P12 cycles	32.25
P13 cycles	32.25
P14 cycles	47.00
P15 cycles	47.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	405.00
Nb loads	22.00
Nb stores	3.00
Nb stack references	16.00
FLOP/cycle	11.69
Nb FLOP add-sub	8.00
Nb FLOP mul	48.00
Nb FLOP fma	264.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.97
Bytes prefetched	0.00
Bytes loaded	1376.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	95.27
Vector-efficiency ratio load	97.73
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	85.71

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.63
CQA cycles if no scalar integer	49.75
CQA cycles if FP arith vectorized	50.63
CQA cycles if fully vectorized	50.32
Front-end cycles	50.63
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	18.50
P7 cycles	18.50
P8 cycles	18.50
P9 cycles	18.50
P10 cycles	32.25
P11 cycles	32.25
P12 cycles	32.25
P13 cycles	32.25
P14 cycles	47.00
P15 cycles	47.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	84.00
Nb uops	405.00
Nb loads	22.00
Nb stores	3.00
Nb stack references	16.00
FLOP/cycle	11.69
Nb FLOP add-sub	8.00
Nb FLOP mul	48.00
Nb FLOP fma	264.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.97
Bytes prefetched	0.00
Bytes loaded	1376.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	95.27
Vector-efficiency ratio load	97.73
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	85.71

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 95% register length (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 50.63 to 50.32 cycles (1.01x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 264 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences►
VGATHERDPD: 4 occurrences►
VSCATTERQPD: 3 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 7 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 7 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►
VSCATTERQPD: 3 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 592 FP arithmetical operations:

272: addition or subtraction (264 inside FMA instructions)
312: multiply (264 inside FMA instructions)
8: divide

The binary loop is loading 1376 bytes (172 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	84
nb uops	405
loop length	530
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	32
nb stack references	16
ADD-SUB / MUL ratio	0.17

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	50.63 cycles
front end	50.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	18.50	18.50	18.50	18.50	32.25	32.25	32.25	32.25	47.00	47.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	18.50	18.50	18.50	18.50	32.25	32.25	32.25	32.25	47.00	47.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	50.63
Dispatch	47.00
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	50.63

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	75%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	95%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	85%

INT+FP

all	95%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	85%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.63 cycles. At this rate:

10% of peak load performance is reached (27.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 50.63 to 47.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 41d4d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R10,%RDI,8),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM20,%ZMM16,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM21,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM21,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%R8,%YMM21,8),%ZMM23{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM22,%XMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x8(%R8,%YMM21,8),%ZMM22{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x600(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x680(%RSP),%ZMM0,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x280(%RSP),%ZMM10,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x540(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD 0x5c0(%RSP),%ZMM0,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x580(%RSP),%ZMM10,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM24,%ZMM22,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x180(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x240(%RSP),%ZMM0,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x1c0(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD 0x140(%RSP),%ZMM0,%ZMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM24,%ZMM22,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM11,%ZMM27,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM13,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM31,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM3,%ZMM30,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM17,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM4,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM23,%ZMM22,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x10(%R8,%YMM21,8),%ZMM23{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VFMADD132PD 0x2c0(%RSP),%ZMM5,%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM12,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM26,%ZMM23,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x6c0(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x200(%RSP),%ZMM0,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM25,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM2,%ZMM29,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM15,%ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM24,%ZMM23,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x18(%R8,%YMM21,8),%ZMM23{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM10,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM1,%ZMM14,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM8,%ZMM10,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM22,%ZMM23,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM18,%ZMM28,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM19,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM6,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM25,%ZMM23,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD 0x500(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD 0x640(%RSP),%ZMM0,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM26,%ZMM23,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM20,%ZMM21,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VPMOVSXDQ (%RAX,%RDI,4),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x700(%RSP),%ZMM10,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM21,%ZMM7,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM10,(%RDX,%ZMM21,8){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM20,(%RSI,%ZMM21,8){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM22,(%R9,%ZMM21,8){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
ADD $0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 41d4d0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x3e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 264 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences►
VGATHERDPD: 4 occurrences►
VSCATTERQPD: 3 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 7 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 7 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 4 occurrences►
VSCATTERQPD: 3 occurrences►

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 592 FP arithmetical operations:

272: addition or subtraction (264 inside FMA instructions)
312: multiply (264 inside FMA instructions)
8: divide

The binary loop is loading 1376 bytes (172 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.38 FP operations per loaded or stored byte.

General properties

nb instructions	84
nb uops	405
loop length	530
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	32
nb stack references	16
ADD-SUB / MUL ratio	0.17

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	50.63 cycles
front end	50.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	18.50	18.50	18.50	18.50	32.25	32.25	32.25	32.25	47.00	47.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	18.50	18.50	18.50	18.50	32.25	32.25	32.25	32.25	47.00	47.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	50.63
Dispatch	47.00
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	50.63

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	75%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	95%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	85%

INT+FP

all	95%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	85%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.63 cycles. At this rate:

10% of peak load performance is reached (27.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41d4d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R10,%RDI,8),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM20,%ZMM16,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM21,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM10,%ZMM21,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VCVTTPD2DQ %ZMM21,%YMM21	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	0.67	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VGATHERDPD (%R8,%YMM21,8),%ZMM23{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VXORPD %XMM22,%XMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x8(%R8,%YMM21,8),%ZMM22{%K2}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x600(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x680(%RSP),%ZMM0,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x280(%RSP),%ZMM10,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x540(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD 0x5c0(%RSP),%ZMM0,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x580(%RSP),%ZMM10,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM24,%ZMM22,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x180(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x240(%RSP),%ZMM0,%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x1c0(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD 0x140(%RSP),%ZMM0,%ZMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM24,%ZMM22,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM11,%ZMM27,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM13,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM31,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM23,%ZMM24,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM3,%ZMM30,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM17,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM4,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM23,%ZMM22,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x10(%R8,%YMM21,8),%ZMM23{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VFMADD132PD 0x2c0(%RSP),%ZMM5,%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM12,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM26,%ZMM23,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVUPD 0x6c0(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD132PD 0x200(%RSP),%ZMM0,%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM25,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM2,%ZMM29,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM9,%ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM15,%ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM24,%ZMM23,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPD 0x18(%R8,%YMM21,8),%ZMM23{%K1}	46	0	0	0	0	0	0	2	2	2	2	2.50	3.50	4	3	5	5	0-16	8	vect (100.0%)
VMOVAPD %ZMM10,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM1,%ZMM14,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM8,%ZMM10,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM22,%ZMM23,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD213PD %ZMM18,%ZMM28,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM19,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM6,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM25,%ZMM23,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD 0x500(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD213PD 0x640(%RSP),%ZMM0,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PD %ZMM26,%ZMM23,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VDIVPD %ZMM20,%ZMM21,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VPMOVSXDQ (%RAX,%RDI,4),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMULPD 0x700(%RSP),%ZMM10,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM21,%ZMM7,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM10,(%RDX,%ZMM21,8){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM20,(%RSI,%ZMM21,8){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSCATTERQPD %ZMM22,(%R9,%ZMM21,8){%K1}	48	0	0	0	0	0	0	2	2	2	2	0	3	3.50	1.50	9	9	1-40	12.14	vect (100.0%)
ADD $0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 41d4d0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x3e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code