OV - exec - Loop 1860

	Loop Id: 1860	Module: exec	Source: :0-0	Coverage: 0.02%

0x4c4200 LEA	0x1(%R10),%RAX

0x4c4204 ADD	$0x200,%EBX

0x4c420a ADD	$0x200,%R11D

0x4c4211 CMP	%RBP,%R10

0x4c4214 MOV	%RAX,%R10

0x4c4217 JE	4c4100

0x4c421d CMP	%R15D,%EBX

0x4c4220 MOV	%R15D,%R13D

0x4c4223 CMOVL	%EBX,%R13D

0x4c4227 MOV	%R11D,%R11D

0x4c422a MOV	%R10D,%R9D

0x4c422d SAL	$0x9,%R9D

0x4c4231 LEA	0x200(%R9),%EAX

0x4c4238 CMP	%R15D,%EAX

0x4c423b CMOVGE	%R15D,%EAX

0x4c423f CMP	%EAX,%R9D

0x4c4242 JGE	4c4200

0x4c4244 MOV	0x28(%RSP),%RAX

0x4c4249 MOV	0x8(%RSP),%R9

0x4c424e VMOVSD	(%RAX,%R9,8),%XMM20

0x4c4255 MOV	0x18(%RSP),%R9

0x4c425a VMOVSD	(%RAX,%R9,8),%XMM21

0x4c4261 MOV	0x30(%RSP),%R9

0x4c4266 VMOVSD	(%RAX,%R9,8),%XMM22

0x4c426d MOV	%R11,%R9

  (1861) 0x4c4270 VMOVSD	(%R14,%R9,8),%XMM23

  (1861) 0x4c4277 VSUBSD	%XMM20,%XMM23,%XMM23

  (1861) 0x4c427d VMOVSD	(%RSI,%R9,8),%XMM24

  (1861) 0x4c4284 VSUBSD	%XMM21,%XMM24,%XMM24

  (1861) 0x4c428a VMOVSD	(%R8,%R9,8),%XMM25

  (1861) 0x4c4291 VSUBSD	%XMM22,%XMM25,%XMM25

  (1861) 0x4c4297 VMULSD	%XMM23,%XMM2,%XMM26

  (1861) 0x4c429d VFMADD231SD	%XMM24,%XMM3,%XMM26

  (1861) 0x4c42a3 VFMADD231SD	%XMM25,%XMM4,%XMM26

  (1861) 0x4c42a9 VMULSD	%XMM23,%XMM5,%XMM27

  (1861) 0x4c42af VFMADD231SD	%XMM24,%XMM6,%XMM27

  (1861) 0x4c42b5 VFMADD231SD	%XMM25,%XMM7,%XMM27

  (1861) 0x4c42bb VMULSD	%XMM23,%XMM8,%XMM23

  (1861) 0x4c42c1 VFMADD231SD	%XMM24,%XMM9,%XMM23

  (1861) 0x4c42c7 VFMADD231SD	%XMM25,%XMM10,%XMM23

  (1861) 0x4c42cd VMOVDQA64	%XMM1,%XMM24

  (1861) 0x4c42d3 VPTERNLOGQ	$-0x8,%XMM0,%XMM26,%XMM24

  (1861) 0x4c42da VADDSD	%XMM24,%XMM26,%XMM24

  (1861) 0x4c42e0 VRNDSCALESD	$0xb,%XMM24,%XMM24,%XMM24

  (1861) 0x4c42e7 VSUBSD	%XMM24,%XMM26,%XMM24

  (1861) 0x4c42ed VMOVDQA64	%XMM1,%XMM25

  (1861) 0x4c42f3 VPTERNLOGQ	$-0x8,%XMM0,%XMM27,%XMM25

  (1861) 0x4c42fa VADDSD	%XMM25,%XMM27,%XMM25

  (1861) 0x4c4300 VRNDSCALESD	$0xb,%XMM25,%XMM25,%XMM25

  (1861) 0x4c4307 VSUBSD	%XMM25,%XMM27,%XMM25

  (1861) 0x4c430d VMOVDQA64	%XMM1,%XMM26

  (1861) 0x4c4313 VPTERNLOGQ	$-0x8,%XMM0,%XMM23,%XMM26

  (1861) 0x4c431a VADDSD	%XMM26,%XMM23,%XMM26

  (1861) 0x4c4320 VRNDSCALESD	$0xb,%XMM26,%XMM26,%XMM26

  (1861) 0x4c4327 VSUBSD	%XMM26,%XMM23,%XMM23

  (1861) 0x4c432d VMULSD	%XMM24,%XMM11,%XMM26

  (1861) 0x4c4333 VFMADD231SD	%XMM25,%XMM12,%XMM26

  (1861) 0x4c4339 VFMADD231SD	%XMM13,%XMM23,%XMM26

  (1861) 0x4c433f VMOVSD	%XMM26,(%RDX,%R9,8)

  (1861) 0x4c4346 VMULSD	%XMM24,%XMM14,%XMM27

  (1861) 0x4c434c VFMADD231SD	%XMM25,%XMM15,%XMM27

  (1861) 0x4c4352 VFMADD231SD	%XMM23,%XMM16,%XMM27

  (1861) 0x4c4358 VMOVSD	%XMM27,(%RDI,%R9,8)

  (1861) 0x4c435f VMULSD	%XMM24,%XMM17,%XMM24

  (1861) 0x4c4365 VFMADD231SD	%XMM25,%XMM18,%XMM24

  (1861) 0x4c436b VFMADD231SD	%XMM23,%XMM19,%XMM24

  (1861) 0x4c4371 VMOVSD	%XMM24,(%RCX,%R9,8)

  (1861) 0x4c4378 VMULSD	%XMM26,%XMM26,%XMM23

  (1861) 0x4c437e VFMADD231SD	%XMM27,%XMM27,%XMM23

  (1861) 0x4c4384 VFMADD231SD	%XMM24,%XMM24,%XMM23

  (1861) 0x4c438a VSQRTSD	%XMM23,%XMM23,%XMM23

  (1861) 0x4c4390 VMOVSD	%XMM23,(%R12,%R9,8)

  (1861) 0x4c4397 INC	%R9

  (1861) 0x4c439a CMP	%R9,%R13

  (1861) 0x4c439d JNE	4c4270

0x4c43a3 JMP	4c4200

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►95.79+	qmcplusplus::ParticleSet::upda[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.76+	qmcplusplus::ParticleSet::upda[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.92
CQA cycles if no scalar integer	1.85
CQA cycles if FP arith vectorized	2.92
CQA cycles if fully vectorized	0.20
Front-end cycles	2.88
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	0.88
P7 cycles	0.88
P8 cycles	0.88
P9 cycles	0.88
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.50
Nb uops	23.00
Nb loads	3.50
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.78
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Metric	Value
CQA speedup if no scalar integer	2.55
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	micro-operation queue,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.38
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.25
Front-end cycles	3.50
P0 cycles	2.67
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	28.00
Nb loads	7.00
Nb stores	0.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.52
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.33
CQA cycles if no scalar integer	2.33
CQA cycles if FP arith vectorized	2.33
CQA cycles if fully vectorized	0.16
Front-end cycles	2.25
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	18.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.03
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.29

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines
Module	exec

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.92 to 0.20 cycles (14.27x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVGE: 0 occurrences
CMOVL: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes.

General properties

nb instructions	21.50
nb uops	23
loop length	92.50
used x86 registers	8.50
used mmx registers	0
used xmm registers	1.50
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.50	2.50	2.50	2.50	2.50	2.50	0.88	0.88	0.88	0.88	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	0.88	0.88	0.88	0.88	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.88
Dispatch	2.50
Data deps.	1.00
Overall L1	2.92

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.92 cycles. At this rate:

3% of peak load performance is reached (8.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.38 cycles (2.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.25 cycles (13.87x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVGE: 1 occurrences►
CMOVL: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	26
nb uops	28
loop length	117
used x86 registers	9
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	2.67
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

6% of peak load performance is reached (16.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.67 cycles (1.31x speedup).

ASM code

In the binary file, the address of the loop is: 4c421d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
LEA 0x1(%R10),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD $0x200,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x200,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %RBP,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4c4100 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x270>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMOVL %EBX,%R13D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x9,%R9D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA 0x200(%R9),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVGE %R15D,%EAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
CMP %EAX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 4c4200 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD (%RAX,%R9,8),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD (%RAX,%R9,8),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD (%RAX,%R9,8),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4c4200 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVGE: 1 occurrences►
CMOVL: 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	17
nb uops	18
loop length	68
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	2.33
Data deps.	1.00
Overall L1	2.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.33 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4c421d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
LEA 0x1(%R10),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
ADD $0x200,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
ADD $0x200,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
CMP %RBP,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0.17	N/A
JE 4c4100 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x270>	1	0	0	0	0.33	0.33	0.33	1	0.50-1	N/A
CMP %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMOVL %EBX,%R13D	2	0.33	0.33	0.33	0.33	0.33	0.33	1	0.33	scal (6.3%)
MOV %R11D,%R11D	1	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10D,%R9D	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x9,%R9D	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
LEA 0x200(%R9),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
CMOVGE %R15D,%EAX	2	0.33	0.33	0.33	0.33	0.33	0.33	1	0.33	N/A
CMP %EAX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
JGE 4c4200 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x370>	1	0	0	0	0.33	0.33	0.33	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code