OV - exec - Loop 1190

	Loop Id: 1190	Module: exec	Source: :0-0	Coverage: 0.72%

0x46fd80 LEA	(%R9,%R15,1),%R12D

0x46fd84 MOVSXD	%R12D,%R12

0x46fd87 VMOVUPD	(%RBX,%R12,8),%ZMM17    [6]

0x46fd8e VMOVUPD	0x40(%RBX,%R12,8),%ZMM18    [6]

0x46fd96 VSUBPD	%ZMM5,%ZMM17,%ZMM17

0x46fd9c VSUBPD	%ZMM5,%ZMM18,%ZMM18

0x46fda2 VMOVUPD	(%R11,%R12,8),%ZMM19    [3]

0x46fda9 VMOVUPD	0x40(%R11,%R12,8),%ZMM20    [3]

0x46fdb1 VSUBPD	%ZMM4,%ZMM20,%ZMM20

0x46fdb7 VSUBPD	%ZMM4,%ZMM19,%ZMM19

0x46fdbd VMOVUPD	(%R10,%R12,8),%ZMM21    [2]

0x46fdc4 VMOVUPD	0x40(%R10,%R12,8),%ZMM22    [2]

0x46fdcc VMULPD	%ZMM18,%ZMM8,%ZMM23

0x46fdd2 VSUBPD	%ZMM3,%ZMM21,%ZMM21

0x46fdd8 VMULPD	%ZMM17,%ZMM8,%ZMM24

0x46fdde VFMADD231PD	%ZMM19,%ZMM7,%ZMM24

0x46fde4 VFMADD231PD	%ZMM20,%ZMM7,%ZMM23

0x46fdea VSUBPD	%ZMM3,%ZMM22,%ZMM22

0x46fdf0 VFMADD231PD	%ZMM22,%ZMM6,%ZMM23

0x46fdf6 VMULPD	%ZMM17,%ZMM12,%ZMM25

0x46fdfc VMULPD	%ZMM18,%ZMM12,%ZMM26

0x46fe02 VFMADD231PD	%ZMM21,%ZMM6,%ZMM24

0x46fe08 VFMADD231PD	%ZMM20,%ZMM11,%ZMM26

0x46fe0e VFMADD231PD	%ZMM19,%ZMM11,%ZMM25

0x46fe14 VMULPD	%ZMM18,%ZMM14,%ZMM18

0x46fe1a VFMADD231PD	%ZMM21,%ZMM10,%ZMM25

0x46fe20 VMULPD	%ZMM17,%ZMM14,%ZMM17

0x46fe26 VFMADD231PD	%ZMM19,%ZMM13,%ZMM17

0x46fe2c VFMADD231PD	%ZMM20,%ZMM13,%ZMM18

0x46fe32 VFMADD231PD	%ZMM22,%ZMM10,%ZMM26

0x46fe38 VFMADD231PD	%ZMM22,%ZMM9,%ZMM18

0x46fe3e VFMADD231PD	%ZMM21,%ZMM9,%ZMM17

0x46fe44 VMOVDQA64	%ZMM16,%ZMM19

0x46fe4a VPTERNLOGQ	$-0x8,%ZMM15,%ZMM24,%ZMM19

0x46fe51 VADDPD	%ZMM19,%ZMM24,%ZMM19

0x46fe57 VMOVDQA64	%ZMM16,%ZMM20

0x46fe5d VPTERNLOGQ	$-0x8,%ZMM15,%ZMM23,%ZMM20

0x46fe64 VRNDSCALEPD	$0xb,%ZMM19,%ZMM19

0x46fe6b VADDPD	%ZMM20,%ZMM23,%ZMM20

0x46fe71 VRNDSCALEPD	$0xb,%ZMM20,%ZMM20

0x46fe78 VMOVDQA64	%ZMM16,%ZMM21

0x46fe7e VSUBPD	%ZMM20,%ZMM23,%ZMM20

0x46fe84 VPTERNLOGQ	$-0x8,%ZMM15,%ZMM26,%ZMM21

0x46fe8b VADDPD	%ZMM21,%ZMM26,%ZMM21

0x46fe91 VRNDSCALEPD	$0xb,%ZMM21,%ZMM21

0x46fe98 VSUBPD	%ZMM19,%ZMM24,%ZMM19

0x46fe9e VMOVDQA64	%ZMM16,%ZMM22

0x46fea4 VPTERNLOGQ	$-0x8,%ZMM15,%ZMM25,%ZMM22

0x46feab VADDPD	%ZMM22,%ZMM25,%ZMM22

0x46feb1 VRNDSCALEPD	$0xb,%ZMM22,%ZMM22

0x46feb8 VMOVDQA64	%ZMM16,%ZMM23

0x46febe VPTERNLOGQ	$-0x8,%ZMM15,%ZMM17,%ZMM23

0x46fec5 VADDPD	%ZMM23,%ZMM17,%ZMM23

0x46fecb VSUBPD	%ZMM22,%ZMM25,%ZMM22

0x46fed1 VRNDSCALEPD	$0xb,%ZMM23,%ZMM23

0x46fed8 VMOVDQA64	%ZMM16,%ZMM24

0x46fede VPTERNLOGQ	$-0x8,%ZMM15,%ZMM18,%ZMM24

0x46fee5 VSUBPD	%ZMM21,%ZMM26,%ZMM21

0x46feeb VADDPD	%ZMM24,%ZMM18,%ZMM24

0x46fef1 VRNDSCALEPD	$0xb,%ZMM24,%ZMM24

0x46fef8 VMULPD	%ZMM19,%ZMM2,%ZMM25

0x46fefe VSUBPD	%ZMM24,%ZMM18,%ZMM18

0x46ff04 VMULPD	%ZMM20,%ZMM2,%ZMM24

0x46ff0a VFMADD231PD	%ZMM21,%ZMM1,%ZMM24

0x46ff10 VFMADD231PD	%ZMM22,%ZMM1,%ZMM25

0x46ff16 VSUBPD	%ZMM23,%ZMM17,%ZMM17

0x46ff1c VFMADD231PD	%ZMM0,%ZMM17,%ZMM25

0x46ff22 VFMADD231PD	%ZMM0,%ZMM18,%ZMM24

0x46ff28 VMOVUPD	%ZMM24,0x40(%RSI,%R12,8)    [4]

0x46ff30 VMOVUPD	%ZMM25,(%RSI,%R12,8)    [4]

0x46ff37 VBROADCASTSD	0x18(%RDI),%ZMM23    [1]

0x46ff3e VMULPD	%ZMM20,%ZMM23,%ZMM26

0x46ff44 VMULPD	%ZMM19,%ZMM23,%ZMM23

0x46ff4a VBROADCASTSD	0x20(%RDI),%ZMM27    [1]

0x46ff51 VFMADD231PD	%ZMM22,%ZMM27,%ZMM23

0x46ff57 VFMADD231PD	%ZMM27,%ZMM21,%ZMM26

0x46ff5d VBROADCASTSD	0x28(%RDI),%ZMM27    [1]

0x46ff64 VFMADD231PD	%ZMM18,%ZMM27,%ZMM26

0x46ff6a VFMADD231PD	%ZMM27,%ZMM17,%ZMM23

0x46ff70 VMOVUPD	%ZMM23,(%RDX,%R12,8)    [8]

0x46ff77 VMOVUPD	%ZMM26,0x40(%RDX,%R12,8)    [8]

0x46ff7f VBROADCASTSD	0x30(%RDI),%ZMM27    [1]

0x46ff86 VMULPD	%ZMM20,%ZMM27,%ZMM20

0x46ff8c VBROADCASTSD	0x38(%RDI),%ZMM28    [1]

0x46ff93 VMULPD	%ZMM19,%ZMM27,%ZMM19

0x46ff99 VFMADD231PD	%ZMM22,%ZMM28,%ZMM19

0x46ff9f VBROADCASTSD	0x40(%RDI),%ZMM22    [1]

0x46ffa6 VFMADD231PD	%ZMM21,%ZMM28,%ZMM20

0x46ffac VFMADD231PD	%ZMM18,%ZMM22,%ZMM20

0x46ffb2 VMULPD	%ZMM24,%ZMM24,%ZMM18

0x46ffb8 VMULPD	%ZMM25,%ZMM25,%ZMM21

0x46ffbe VFMADD231PD	%ZMM17,%ZMM22,%ZMM19

0x46ffc4 VFMADD231PD	%ZMM23,%ZMM23,%ZMM21

0x46ffca VFMADD231PD	%ZMM26,%ZMM26,%ZMM18

0x46ffd0 VFMADD231PD	%ZMM20,%ZMM20,%ZMM18

0x46ffd6 VFMADD231PD	%ZMM19,%ZMM19,%ZMM21

0x46ffdc VSQRTPD	%ZMM21,%ZMM17

0x46ffe2 VMOVUPD	%ZMM19,(%RAX,%R12,8)    [5]

0x46ffe9 VSQRTPD	%ZMM18,%ZMM18

0x46ffef VMOVUPD	%ZMM20,0x40(%RAX,%R12,8)    [5]

0x46fff7 VMOVUPD	%ZMM18,0x40(%RCX,%R12,8)    [7]

0x46ffff VMOVUPD	%ZMM17,(%RCX,%R12,8)    [7]

0x470006 ADD	$0x10,%R15D

0x47000a CMP	%R14D,%R15D

0x47000d JBE	46fd80

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►36.12+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►30.05+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►19.55+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::upda[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►7.67+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.71+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.14+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	13.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	22.00
P11 cycles	22.00
P12 cycles	15.00
P13 cycles	15.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	17.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	104.00
Nb loads	12.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	32.73
Nb FLOP add-sub	144.00
Nb FLOP mul	112.00
Nb FLOP fma	224.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.91
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	94.00
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	94.75
Vector-efficiency ratio load	56.25
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	78.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	13.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	22.00
P11 cycles	22.00
P12 cycles	15.00
P13 cycles	15.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	17.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	104.00
Nb loads	12.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	32.73
Nb FLOP add-sub	144.00
Nb FLOP mul	112.00
Nb FLOP fma	224.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.91
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	94.00
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	94.75
Vector-efficiency ratio load	56.25
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	78.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 94% of vector register length is used (average across all SSE/AVX instructions).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 14 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 14 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

68 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary loop is loading 432 bytes (54 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.76 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	104
loop length	659
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	29
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	22.00	22.00	15.00	15.00	4.00	4.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	22.00	22.00	15.00	15.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	17.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.00
Dispatch	22.00
DIV/SQRT	17.00
Data deps.	1.00
Overall L1	22.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	93%
load	50%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

INT+FP

all	94%
load	50%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	75%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	94%
load	56%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	56%

INT+FP

all	94%
load	56%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	78%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

7% of peak load performance is reached (19.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46fd80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA (%R9,%R15,1),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSXD %R12D,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RBX,%R12,8),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RBX,%R12,8),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R11,%R12,8),%ZMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R11,%R12,8),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM20,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM19,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R10,%R12,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%R12,8),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM8,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM6,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM12,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM12,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM11,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM11,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM14,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM14,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM13,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM13,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM9,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM9,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM19,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM19,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM20,%ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM20,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VSUBPD %ZMM20,%ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM26,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM21,%ZMM26,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM19,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM22,%ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM17,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM23,%ZMM17,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM22,%ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM23,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VSUBPD %ZMM21,%ZMM26,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM2,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM24,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM20,%ZMM2,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM1,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM23,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM24,0x40(%RSI,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM25,(%RSI,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x18(%RDI),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM20,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM23,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x20(%RDI),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM22,%ZMM27,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM21,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x28(%RDI),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM18,%ZMM27,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM17,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM23,(%RDX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM26,0x40(%RDX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x30(%RDI),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM20,%ZMM27,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x38(%RDI),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM19,%ZMM27,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM28,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x40(%RDI),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM21,%ZMM28,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM22,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM24,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM22,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM23,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM26,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM20,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM19,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM21,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVUPD %ZMM19,(%RAX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VSQRTPD %ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVUPD %ZMM20,0x40(%RAX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM18,0x40(%RCX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM17,(%RCX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x10,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 46fd80 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x110>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer > >(qmcplusplus::TinyVector const&, qmcplusplus::VectorSoAContainer > const&, double*, qmcplusplus::VectorSoAContainer >&, int, int, int) const
Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 94% of vector register length is used (average across all SSE/AVX instructions).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 14 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 14 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

68 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary loop is loading 432 bytes (54 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.76 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	104
loop length	659
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	29
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	22.00	22.00	15.00	15.00	4.00	4.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	22.00	22.00	15.00	15.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	17.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.00
Dispatch	22.00
DIV/SQRT	17.00
Data deps.	1.00
Overall L1	22.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	93%
load	50%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

INT+FP

all	94%
load	50%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	75%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	94%
load	56%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	56%

INT+FP

all	94%
load	56%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	78%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

7% of peak load performance is reached (19.64 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46fd80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA (%R9,%R15,1),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSXD %R12D,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%RBX,%R12,8),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RBX,%R12,8),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R11,%R12,8),%ZMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R11,%R12,8),%ZMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM20,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM19,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R10,%R12,8),%ZMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%R12,8),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM8,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM6,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM12,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM12,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM11,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM11,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM14,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM10,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM14,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM13,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM13,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM9,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM9,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM19,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM19,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM20,%ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM20,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VSUBPD %ZMM20,%ZMM23,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM26,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM21,%ZMM26,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM21,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM19,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM22,%ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM22,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM17,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM23,%ZMM17,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM22,%ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM23,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM16,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM15,%ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VSUBPD %ZMM21,%ZMM26,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM24,%ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM2,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM24,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM20,%ZMM2,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM1,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM23,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM24,0x40(%RSI,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM25,(%RSI,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x18(%RDI),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM20,%ZMM23,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM23,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x20(%RDI),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM22,%ZMM27,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM21,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x28(%RDI),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM18,%ZMM27,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM17,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM23,(%RDX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM26,0x40(%RDX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x30(%RDI),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM20,%ZMM27,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x38(%RDI),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM19,%ZMM27,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM22,%ZMM28,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x40(%RDI),%ZMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM21,%ZMM28,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM22,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM24,%ZMM24,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM25,%ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM17,%ZMM22,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM23,%ZMM23,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM26,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM20,%ZMM20,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM19,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM21,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVUPD %ZMM19,(%RAX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VSQRTPD %ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVUPD %ZMM20,0x40(%RAX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM18,0x40(%RCX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM17,(%RCX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x10,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 46fd80 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x110>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code