OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.72% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x46fc70 PUSH	%RBP

0x46fc71 PUSH	%R15

0x46fc73 PUSH	%R14

0x46fc75 PUSH	%R12

0x46fc77 PUSH	%RBX

0x46fc78 MOV	0x30(%RSP),%EBP

0x46fc7c SUB	%R9D,%EBP

0x46fc7f JLE	470343

0x46fc85 VMOVSD	(%RSI),%XMM5

0x46fc89 VMOVSD	0x8(%RSI),%XMM4

0x46fc8e VMOVSD	0x10(%RSI),%XMM3

0x46fc93 MOV	0x8(%RDX),%R10

0x46fc97 MOV	0x18(%RDX),%RBX

0x46fc9b LEA	(%RBX,%R10,8),%R11

0x46fc9f SAL	$0x4,%R10

0x46fca3 ADD	%RBX,%R10

0x46fca6 MOV	0x8(%R8),%RAX

0x46fcaa MOV	0x18(%R8),%RSI

0x46fcae LEA	(%RSI,%RAX,8),%RDX

0x46fcb2 SAL	$0x4,%RAX

0x46fcb6 ADD	%RSI,%RAX

0x46fcb9 VMOVSD	0x48(%RDI),%XMM8

0x46fcbe VMOVSD	0x50(%RDI),%XMM7

0x46fcc3 VMOVSD	0x58(%RDI),%XMM6

0x46fcc8 VMOVSD	0x60(%RDI),%XMM12

0x46fccd VMOVSD	0x68(%RDI),%XMM11

0x46fcd2 VMOVSD	0x70(%RDI),%XMM10

0x46fcd7 VMOVSD	0x78(%RDI),%XMM14

0x46fcdc VMOVSD	0x80(%RDI),%XMM13

0x46fce4 VMOVSD	0x88(%RDI),%XMM9

0x46fcec VMOVSD	(%RDI),%XMM2

0x46fcf0 VMOVSD	0x8(%RDI),%XMM1

0x46fcf5 VMOVSD	0x10(%RDI),%XMM0

0x46fcfa MOV	%EBP,%R8D

0x46fcfd AND	$-0x10,%R8D

0x46fd01 JE	470024

0x46fd07 LEA	-0x1(%R8),%R14D

0x46fd0b VBROADCASTSD	%XMM5,%ZMM5

0x46fd11 VBROADCASTSD	%XMM4,%ZMM4

0x46fd17 VBROADCASTSD	%XMM3,%ZMM3

0x46fd1d VBROADCASTSD	%XMM8,%ZMM8

0x46fd23 VBROADCASTSD	%XMM7,%ZMM7

0x46fd29 VBROADCASTSD	%XMM6,%ZMM6

0x46fd2f VBROADCASTSD	%XMM12,%ZMM12

0x46fd35 VBROADCASTSD	%XMM11,%ZMM11

0x46fd3b VBROADCASTSD	%XMM10,%ZMM10

0x46fd41 VBROADCASTSD	%XMM14,%ZMM14

0x46fd47 VBROADCASTSD	%XMM13,%ZMM13

0x46fd4d VBROADCASTSD	%XMM9,%ZMM9

0x46fd53 VBROADCASTSD	%XMM2,%ZMM2

0x46fd59 VBROADCASTSD	%XMM1,%ZMM1

0x46fd5f VBROADCASTSD	%XMM0,%ZMM0

0x46fd65 XOR	%R15D,%R15D

0x46fd68 VPBROADCASTQ	0x822ce(%RIP),%ZMM15

0x46fd72 VPBROADCASTQ	0x87704(%RIP),%ZMM16

0x46fd7c NOPL	(%RAX)

(1190) 0x46fd80 LEA	(%R9,%R15,1),%R12D

(1190) 0x46fd84 MOVSXD	%R12D,%R12

(1190) 0x46fd87 VMOVUPD	(%RBX,%R12,8),%ZMM17

(1190) 0x46fd8e VMOVUPD	0x40(%RBX,%R12,8),%ZMM18

(1190) 0x46fd96 VSUBPD	%ZMM5,%ZMM17,%ZMM17

(1190) 0x46fd9c VSUBPD	%ZMM5,%ZMM18,%ZMM18

(1190) 0x46fda2 VMOVUPD	(%R11,%R12,8),%ZMM19

(1190) 0x46fda9 VMOVUPD	0x40(%R11,%R12,8),%ZMM20

(1190) 0x46fdb1 VSUBPD	%ZMM4,%ZMM20,%ZMM20

(1190) 0x46fdb7 VSUBPD	%ZMM4,%ZMM19,%ZMM19

(1190) 0x46fdbd VMOVUPD	(%R10,%R12,8),%ZMM21

(1190) 0x46fdc4 VMOVUPD	0x40(%R10,%R12,8),%ZMM22

(1190) 0x46fdcc VMULPD	%ZMM18,%ZMM8,%ZMM23

(1190) 0x46fdd2 VSUBPD	%ZMM3,%ZMM21,%ZMM21

(1190) 0x46fdd8 VMULPD	%ZMM17,%ZMM8,%ZMM24

(1190) 0x46fdde VFMADD231PD	%ZMM19,%ZMM7,%ZMM24

(1190) 0x46fde4 VFMADD231PD	%ZMM20,%ZMM7,%ZMM23

(1190) 0x46fdea VSUBPD	%ZMM3,%ZMM22,%ZMM22

(1190) 0x46fdf0 VFMADD231PD	%ZMM22,%ZMM6,%ZMM23

(1190) 0x46fdf6 VMULPD	%ZMM17,%ZMM12,%ZMM25

(1190) 0x46fdfc VMULPD	%ZMM18,%ZMM12,%ZMM26

(1190) 0x46fe02 VFMADD231PD	%ZMM21,%ZMM6,%ZMM24

(1190) 0x46fe08 VFMADD231PD	%ZMM20,%ZMM11,%ZMM26

(1190) 0x46fe0e VFMADD231PD	%ZMM19,%ZMM11,%ZMM25

(1190) 0x46fe14 VMULPD	%ZMM18,%ZMM14,%ZMM18

(1190) 0x46fe1a VFMADD231PD	%ZMM21,%ZMM10,%ZMM25

(1190) 0x46fe20 VMULPD	%ZMM17,%ZMM14,%ZMM17

(1190) 0x46fe26 VFMADD231PD	%ZMM19,%ZMM13,%ZMM17

(1190) 0x46fe2c VFMADD231PD	%ZMM20,%ZMM13,%ZMM18

(1190) 0x46fe32 VFMADD231PD	%ZMM22,%ZMM10,%ZMM26

(1190) 0x46fe38 VFMADD231PD	%ZMM22,%ZMM9,%ZMM18

(1190) 0x46fe3e VFMADD231PD	%ZMM21,%ZMM9,%ZMM17

(1190) 0x46fe44 VMOVDQA64	%ZMM16,%ZMM19

(1190) 0x46fe4a VPTERNLOGQ	$-0x8,%ZMM15,%ZMM24,%ZMM19

(1190) 0x46fe51 VADDPD	%ZMM19,%ZMM24,%ZMM19

(1190) 0x46fe57 VMOVDQA64	%ZMM16,%ZMM20

(1190) 0x46fe5d VPTERNLOGQ	$-0x8,%ZMM15,%ZMM23,%ZMM20

(1190) 0x46fe64 VRNDSCALEPD	$0xb,%ZMM19,%ZMM19

(1190) 0x46fe6b VADDPD	%ZMM20,%ZMM23,%ZMM20

(1190) 0x46fe71 VRNDSCALEPD	$0xb,%ZMM20,%ZMM20

(1190) 0x46fe78 VMOVDQA64	%ZMM16,%ZMM21

(1190) 0x46fe7e VSUBPD	%ZMM20,%ZMM23,%ZMM20

(1190) 0x46fe84 VPTERNLOGQ	$-0x8,%ZMM15,%ZMM26,%ZMM21

(1190) 0x46fe8b VADDPD	%ZMM21,%ZMM26,%ZMM21

(1190) 0x46fe91 VRNDSCALEPD	$0xb,%ZMM21,%ZMM21

(1190) 0x46fe98 VSUBPD	%ZMM19,%ZMM24,%ZMM19

(1190) 0x46fe9e VMOVDQA64	%ZMM16,%ZMM22

(1190) 0x46fea4 VPTERNLOGQ	$-0x8,%ZMM15,%ZMM25,%ZMM22

(1190) 0x46feab VADDPD	%ZMM22,%ZMM25,%ZMM22

(1190) 0x46feb1 VRNDSCALEPD	$0xb,%ZMM22,%ZMM22

(1190) 0x46feb8 VMOVDQA64	%ZMM16,%ZMM23

(1190) 0x46febe VPTERNLOGQ	$-0x8,%ZMM15,%ZMM17,%ZMM23

(1190) 0x46fec5 VADDPD	%ZMM23,%ZMM17,%ZMM23

(1190) 0x46fecb VSUBPD	%ZMM22,%ZMM25,%ZMM22

(1190) 0x46fed1 VRNDSCALEPD	$0xb,%ZMM23,%ZMM23

(1190) 0x46fed8 VMOVDQA64	%ZMM16,%ZMM24

(1190) 0x46fede VPTERNLOGQ	$-0x8,%ZMM15,%ZMM18,%ZMM24

(1190) 0x46fee5 VSUBPD	%ZMM21,%ZMM26,%ZMM21

(1190) 0x46feeb VADDPD	%ZMM24,%ZMM18,%ZMM24

(1190) 0x46fef1 VRNDSCALEPD	$0xb,%ZMM24,%ZMM24

(1190) 0x46fef8 VMULPD	%ZMM19,%ZMM2,%ZMM25

(1190) 0x46fefe VSUBPD	%ZMM24,%ZMM18,%ZMM18

(1190) 0x46ff04 VMULPD	%ZMM20,%ZMM2,%ZMM24

(1190) 0x46ff0a VFMADD231PD	%ZMM21,%ZMM1,%ZMM24

(1190) 0x46ff10 VFMADD231PD	%ZMM22,%ZMM1,%ZMM25

(1190) 0x46ff16 VSUBPD	%ZMM23,%ZMM17,%ZMM17

(1190) 0x46ff1c VFMADD231PD	%ZMM0,%ZMM17,%ZMM25

(1190) 0x46ff22 VFMADD231PD	%ZMM0,%ZMM18,%ZMM24

(1190) 0x46ff28 VMOVUPD	%ZMM24,0x40(%RSI,%R12,8)

(1190) 0x46ff30 VMOVUPD	%ZMM25,(%RSI,%R12,8)

(1190) 0x46ff37 VBROADCASTSD	0x18(%RDI),%ZMM23

(1190) 0x46ff3e VMULPD	%ZMM20,%ZMM23,%ZMM26

(1190) 0x46ff44 VMULPD	%ZMM19,%ZMM23,%ZMM23

(1190) 0x46ff4a VBROADCASTSD	0x20(%RDI),%ZMM27

(1190) 0x46ff51 VFMADD231PD	%ZMM22,%ZMM27,%ZMM23

(1190) 0x46ff57 VFMADD231PD	%ZMM27,%ZMM21,%ZMM26

(1190) 0x46ff5d VBROADCASTSD	0x28(%RDI),%ZMM27

(1190) 0x46ff64 VFMADD231PD	%ZMM18,%ZMM27,%ZMM26

(1190) 0x46ff6a VFMADD231PD	%ZMM27,%ZMM17,%ZMM23

(1190) 0x46ff70 VMOVUPD	%ZMM23,(%RDX,%R12,8)

(1190) 0x46ff77 VMOVUPD	%ZMM26,0x40(%RDX,%R12,8)

(1190) 0x46ff7f VBROADCASTSD	0x30(%RDI),%ZMM27

(1190) 0x46ff86 VMULPD	%ZMM20,%ZMM27,%ZMM20

(1190) 0x46ff8c VBROADCASTSD	0x38(%RDI),%ZMM28

(1190) 0x46ff93 VMULPD	%ZMM19,%ZMM27,%ZMM19

(1190) 0x46ff99 VFMADD231PD	%ZMM22,%ZMM28,%ZMM19

(1190) 0x46ff9f VBROADCASTSD	0x40(%RDI),%ZMM22

(1190) 0x46ffa6 VFMADD231PD	%ZMM21,%ZMM28,%ZMM20

(1190) 0x46ffac VFMADD231PD	%ZMM18,%ZMM22,%ZMM20

(1190) 0x46ffb2 VMULPD	%ZMM24,%ZMM24,%ZMM18

(1190) 0x46ffb8 VMULPD	%ZMM25,%ZMM25,%ZMM21

(1190) 0x46ffbe VFMADD231PD	%ZMM17,%ZMM22,%ZMM19

(1190) 0x46ffc4 VFMADD231PD	%ZMM23,%ZMM23,%ZMM21

(1190) 0x46ffca VFMADD231PD	%ZMM26,%ZMM26,%ZMM18

(1190) 0x46ffd0 VFMADD231PD	%ZMM20,%ZMM20,%ZMM18

(1190) 0x46ffd6 VFMADD231PD	%ZMM19,%ZMM19,%ZMM21

(1190) 0x46ffdc VSQRTPD	%ZMM21,%ZMM17

(1190) 0x46ffe2 VMOVUPD	%ZMM19,(%RAX,%R12,8)

(1190) 0x46ffe9 VSQRTPD	%ZMM18,%ZMM18

(1190) 0x46ffef VMOVUPD	%ZMM20,0x40(%RAX,%R12,8)

(1190) 0x46fff7 VMOVUPD	%ZMM18,0x40(%RCX,%R12,8)

(1190) 0x46ffff VMOVUPD	%ZMM17,(%RCX,%R12,8)

(1190) 0x470006 ADD	$0x10,%R15D

(1190) 0x47000a CMP	%R14D,%R15D

(1190) 0x47000d JBE	46fd80

0x470013 CMP	%R8D,%EBP

0x470016 JE	470343

0x47001c VPBROADCASTD	%EBP,%ZMM15

0x470022 JMP	470087

0x470024 VPBROADCASTD	%EBP,%ZMM15

0x47002a VBROADCASTSD	%XMM5,%ZMM5

0x470030 VBROADCASTSD	%XMM4,%ZMM4

0x470036 VBROADCASTSD	%XMM3,%ZMM3

0x47003c VBROADCASTSD	%XMM8,%ZMM8

0x470042 VBROADCASTSD	%XMM7,%ZMM7

0x470048 VBROADCASTSD	%XMM6,%ZMM6

0x47004e VBROADCASTSD	%XMM12,%ZMM12

0x470054 VBROADCASTSD	%XMM11,%ZMM11

0x47005a VBROADCASTSD	%XMM10,%ZMM10

0x470060 VBROADCASTSD	%XMM14,%ZMM14

0x470066 VBROADCASTSD	%XMM13,%ZMM13

0x47006c VBROADCASTSD	%XMM9,%ZMM9

0x470072 VBROADCASTSD	%XMM2,%ZMM2

0x470078 VBROADCASTSD	%XMM1,%ZMM1

0x47007e VBROADCASTSD	%XMM0,%ZMM0

0x470084 XOR	%R8D,%R8D

0x470087 VPBROADCASTD	%R8D,%ZMM16

0x47008d VPSUBD	%ZMM16,%ZMM15,%ZMM15

0x470093 VPCMPNLEUD	0x84362(%RIP),%YMM15,%K1

0x47009e VEXTRACTI64X4	$0x1,%ZMM15,%YMM15

0x4700a5 VPCMPNLEUD	0x873b0(%RIP),%YMM15,%K2

0x4700b0 ADD	%R8D,%R9D

0x4700b3 MOVSXD	%R9D,%R8

0x4700b6 VMOVUPD	0x40(%RBX,%R8,8),%ZMM15{%K2}{z}

0x4700be VSUBPD	%ZMM5,%ZMM15,%ZMM15

0x4700c4 VMOVUPD	(%RBX,%R8,8),%ZMM16{%K1}{z}

0x4700cb VSUBPD	%ZMM5,%ZMM16,%ZMM5

0x4700d1 VMOVUPD	(%R11,%R8,8),%ZMM16{%K1}{z}

0x4700d8 VSUBPD	%ZMM4,%ZMM16,%ZMM16

0x4700de VMOVUPD	0x40(%R11,%R8,8),%ZMM17{%K2}{z}

0x4700e6 VSUBPD	%ZMM4,%ZMM17,%ZMM4

0x4700ec VMOVUPD	0x40(%R10,%R8,8),%ZMM17{%K2}{z}

0x4700f4 VSUBPD	%ZMM3,%ZMM17,%ZMM17

0x4700fa VMOVUPD	(%R10,%R8,8),%ZMM18{%K1}{z}

0x470101 VSUBPD	%ZMM3,%ZMM18,%ZMM3

0x470107 VMULPD	%ZMM15,%ZMM8,%ZMM18

0x47010d VMULPD	%ZMM5,%ZMM8,%ZMM8

0x470113 VFMADD231PD	%ZMM7,%ZMM16,%ZMM8

0x470119 VFMADD231PD	%ZMM7,%ZMM4,%ZMM18

0x47011f VFMADD231PD	%ZMM6,%ZMM17,%ZMM18

0x470125 VFMADD231PD	%ZMM6,%ZMM3,%ZMM8

0x47012b VMULPD	%ZMM5,%ZMM12,%ZMM6

0x470131 VMULPD	%ZMM15,%ZMM12,%ZMM7

0x470137 VFMADD231PD	%ZMM11,%ZMM4,%ZMM7

0x47013d VFMADD231PD	%ZMM11,%ZMM16,%ZMM6

0x470143 VFMADD231PD	%ZMM10,%ZMM3,%ZMM6

0x470149 VFMADD231PD	%ZMM10,%ZMM17,%ZMM7

0x47014f VMULPD	%ZMM15,%ZMM14,%ZMM10

0x470155 VMULPD	%ZMM5,%ZMM14,%ZMM5

0x47015b VFMADD231PD	%ZMM13,%ZMM16,%ZMM5

0x470161 VFMADD231PD	%ZMM13,%ZMM4,%ZMM10

0x470167 VFMADD231PD	%ZMM9,%ZMM17,%ZMM10

0x47016d VPBROADCASTQ	0x81ec9(%RIP),%ZMM4

0x470177 VPBROADCASTQ	0x872ff(%RIP),%ZMM11

0x470181 VFMADD231PD	%ZMM9,%ZMM3,%ZMM5

0x470187 VMOVDQA64	%ZMM11,%ZMM3

0x47018d VPTERNLOGQ	$-0x8,%ZMM4,%ZMM8,%ZMM3

0x470194 VADDPD	%ZMM3,%ZMM8,%ZMM3

0x47019a VRNDSCALEPD	$0xb,%ZMM3,%ZMM3

0x4701a1 VMOVDQA64	%ZMM11,%ZMM9

0x4701a7 VPTERNLOGQ	$-0x8,%ZMM4,%ZMM18,%ZMM9

0x4701ae VADDPD	%ZMM9,%ZMM18,%ZMM9

0x4701b4 VRNDSCALEPD	$0xb,%ZMM9,%ZMM9

0x4701bb VSUBPD	%ZMM9,%ZMM18,%ZMM9

0x4701c1 VSUBPD	%ZMM3,%ZMM8,%ZMM3

0x4701c7 VMOVDQA64	%ZMM11,%ZMM8

0x4701cd VPTERNLOGQ	$-0x8,%ZMM4,%ZMM7,%ZMM8

0x4701d4 VADDPD	%ZMM8,%ZMM7,%ZMM8

0x4701da VRNDSCALEPD	$0xb,%ZMM8,%ZMM8

0x4701e1 VMOVDQA64	%ZMM11,%ZMM12

0x4701e7 VPTERNLOGQ	$-0x8,%ZMM4,%ZMM6,%ZMM12

0x4701ee VADDPD	%ZMM12,%ZMM6,%ZMM12

0x4701f4 VRNDSCALEPD	$0xb,%ZMM12,%ZMM12

0x4701fb VSUBPD	%ZMM12,%ZMM6,%ZMM6

0x470201 VSUBPD	%ZMM8,%ZMM7,%ZMM7

0x470207 VMOVDQA64	%ZMM11,%ZMM8

0x47020d VPTERNLOGQ	$-0x8,%ZMM4,%ZMM5,%ZMM8

0x470214 VADDPD	%ZMM8,%ZMM5,%ZMM8

0x47021a VRNDSCALEPD	$0xb,%ZMM8,%ZMM8

0x470221 VPTERNLOGQ	$-0x8,%ZMM4,%ZMM10,%ZMM11

0x470228 VADDPD	%ZMM11,%ZMM10,%ZMM4

0x47022e VRNDSCALEPD	$0xb,%ZMM4,%ZMM4

0x470235 VSUBPD	%ZMM4,%ZMM10,%ZMM4

0x47023b VSUBPD	%ZMM8,%ZMM5,%ZMM5

0x470241 VMULPD	%ZMM3,%ZMM2,%ZMM8

0x470247 VMULPD	%ZMM9,%ZMM2,%ZMM2

0x47024d VFMADD231PD	%ZMM1,%ZMM7,%ZMM2

0x470253 VFMADD231PD	%ZMM1,%ZMM6,%ZMM8

0x470259 VFMADD231PD	%ZMM0,%ZMM5,%ZMM8

0x47025f VFMADD231PD	%ZMM0,%ZMM4,%ZMM2

0x470265 VMOVUPD	%ZMM2,0x40(%RSI,%R8,8){%K2}

0x47026d VMOVUPD	%ZMM8,(%RSI,%R8,8){%K1}

0x470274 VBROADCASTSD	0x18(%RDI),%ZMM0

0x47027b VMULPD	%ZMM3,%ZMM0,%ZMM1

0x470281 VMULPD	%ZMM9,%ZMM0,%ZMM0

0x470287 VBROADCASTSD	0x20(%RDI),%ZMM10

0x47028e VFMADD231PD	%ZMM7,%ZMM10,%ZMM0

0x470294 VFMADD231PD	%ZMM10,%ZMM6,%ZMM1

0x47029a VBROADCASTSD	0x28(%RDI),%ZMM10

0x4702a1 VFMADD231PD	%ZMM5,%ZMM10,%ZMM1

0x4702a7 VFMADD231PD	%ZMM10,%ZMM4,%ZMM0

0x4702ad VMOVUPD	%ZMM0,0x40(%RDX,%R8,8){%K2}

0x4702b5 VMOVUPD	%ZMM1,(%RDX,%R8,8){%K1}

0x4702bc VBROADCASTSD	0x30(%RDI),%ZMM10

0x4702c3 VMULPD	%ZMM3,%ZMM10,%ZMM3

0x4702c9 VMULPD	%ZMM9,%ZMM10,%ZMM9

0x4702cf VBROADCASTSD	0x38(%RDI),%ZMM10

0x4702d6 VFMADD231PD	%ZMM7,%ZMM10,%ZMM9

0x4702dc VFMADD231PD	%ZMM6,%ZMM10,%ZMM3

0x4702e2 VBROADCASTSD	0x40(%RDI),%ZMM6

0x4702e9 VFMADD231PD	%ZMM5,%ZMM6,%ZMM3

0x4702ef VFMADD231PD	%ZMM4,%ZMM6,%ZMM9

0x4702f5 VMULPD	%ZMM2,%ZMM2,%ZMM2

0x4702fb VMULPD	%ZMM8,%ZMM8,%ZMM4

0x470301 VFMADD231PD	%ZMM1,%ZMM1,%ZMM4

0x470307 VFMADD231PD	%ZMM0,%ZMM0,%ZMM2

0x47030d VFMADD231PD	%ZMM3,%ZMM3,%ZMM4

0x470313 VSQRTPD	%ZMM4,%ZMM0

0x470319 VFMADD231PD	%ZMM9,%ZMM9,%ZMM2

0x47031f VSQRTPD	%ZMM2,%ZMM1

0x470325 VMOVUPD	%ZMM9,0x40(%RAX,%R8,8){%K2}

0x47032d VMOVUPD	%ZMM3,(%RAX,%R8,8){%K1}

0x470334 VMOVUPD	%ZMM1,0x40(%RCX,%R8,8){%K2}

0x47033c VMOVUPD	%ZMM0,(%RCX,%R8,8){%K1}

0x470343 POP	%RBX

0x470344 POP	%R12

0x470346 POP	%R14

0x470348 POP	%R15

0x47034a POP	%RBP

0x47034b VZEROUPPER

0x47034e RET

0x47034f NOP

Coverage (%)	Name	Module
►36.00+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►29.99+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►19.68+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::upda[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►7.69+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.73+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.13+	qmcplusplus::SoaDistanceTableA[...]	exec
○	qmcplusplus::ParticleSet::comp[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 64% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 31.50 to 23.34 cycles (1.35x speedup).

Details

61% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
95% of SSE/AVX addition or subtraction instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 31.50 to 25.00 cycles (1.26x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTD: 3 occurrences►

Vector unaligned load/store instructions

Detected 14 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 14 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

68 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary function is loading 684 bytes (85 double precision FP elements). The binary function is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.60 FP operations per loaded or stored byte.

General properties

nb instructions	193
nb uops	192
loop length	1101
used x86 registers	15
used mmx registers	0
used xmm registers	15
used ymm registers	1
used zmm registers	19
nb stack references	1
ADD-SUB / MUL ratio	1.29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.00 cycles
front end	24.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	2.83	2.83	2.83	2.83	11.00	11.00	11.00	11.00	31.50	31.50	25.00	25.00	4.00	4.00
cycles	2.83	2.83	2.83	2.83	2.83	2.83	11.00	11.00	11.00	11.00	31.50	31.50	25.00	25.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

17.00

Cycles summary

Front-end	24.00
Dispatch	31.50
DIV/SQRT	17.00
Overall L1	31.50

Vectorization ratios

INT

all	59%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	62%

all	61%
load	22%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	14%

INT+FP

all	61%
load	23%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	31%

Vector efficiency ratios

INT

all	54%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	66%
load	31%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

INT+FP

all	64%
load	29%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	36%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 31.50 cycles. At this rate:

8% of peak load performance is reached (21.71 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 46fc70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x30(%RSP),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
SUB %R9D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 470343 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x6d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RSI),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RSI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RSI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RBX,%R10,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RBX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RSI,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x48(%RDI),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x50(%RDI),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x58(%RDI),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x60(%RDI),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x68(%RDI),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x70(%RDI),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x78(%RDI),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x80(%RDI),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x88(%RDI),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RDI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %EBP,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 470024 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x3b4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%R8),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ 0x822ce(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VPBROADCASTQ 0x87704(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 470343 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x6d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD %EBP,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
JMP 470087 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x417>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTD %EBP,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VBROADCASTSD %XMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VPBROADCASTD %R8D,%ZMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPSUBD %ZMM16,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPCMPNLEUD 0x84362(%RIP),%YMM15,%K1																				vect (50.0%)
VEXTRACTI64X4 $0x1,%ZMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPCMPNLEUD 0x873b0(%RIP),%YMM15,%K2																				vect (50.0%)
ADD %R8D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R9D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD 0x40(%RBX,%R8,8),%ZMM15{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%RBX,%R8,8),%ZMM16{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM16,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R11,%R8,8),%ZMM16{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD 0x40(%R11,%R8,8),%ZMM17{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM17,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%R8,8),%ZMM17{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R10,%R8,8),%ZMM18{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM18,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM8,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM16,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM4,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM3,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM12,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM4,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM14,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM14,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM16,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM4,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM17,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VPBROADCASTQ 0x81ec9(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VPBROADCASTQ 0x872ff(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VFMADD231PD %ZMM9,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM3,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM18,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM9,%ZMM18,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM18,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM7,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM8,%ZMM7,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM6,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM12,%ZMM6,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM8,%ZMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM11,%ZMM10,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM10,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM7,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x40(%RSI,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x18(%RDI),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM3,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x20(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM7,%ZMM10,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x28(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM5,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,0x40(%RDX,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDX,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x30(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM3,%ZMM10,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM10,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x38(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM7,%ZMM10,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM10,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x40(%RDI),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM5,%ZMM6,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM6,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM1,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM3,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM9,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVUPD %ZMM9,0x40(%RAX,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM3,(%RAX,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RCX,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM0,(%RCX,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

61% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
95% of SSE/AVX addition or subtraction instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 224 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTD: 3 occurrences►

Vector unaligned load/store instructions

Detected 14 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 14 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

68 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 720 FP arithmetical operations:

368: addition or subtraction (224 inside FMA instructions)
336: multiply (224 inside FMA instructions)
16: square root

The binary function is loading 684 bytes (85 double precision FP elements). The binary function is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.60 FP operations per loaded or stored byte.

General properties

nb instructions	193
nb uops	192
loop length	1101
used x86 registers	15
used mmx registers	0
used xmm registers	15
used ymm registers	1
used zmm registers	19
nb stack references	1
ADD-SUB / MUL ratio	1.29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.00 cycles
front end	24.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	2.83	2.83	2.83	2.83	11.00	11.00	11.00	11.00	31.50	31.50	25.00	25.00	4.00	4.00
cycles	2.83	2.83	2.83	2.83	2.83	2.83	11.00	11.00	11.00	11.00	31.50	31.50	25.00	25.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

17.00

Cycles summary

Front-end	24.00
Dispatch	31.50
DIV/SQRT	17.00
Overall L1	31.50

Vectorization ratios

INT

all	59%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	62%

all	61%
load	22%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	14%

INT+FP

all	61%
load	23%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	31%

Vector efficiency ratios

INT

all	54%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	66%
load	31%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

INT+FP

all	64%
load	29%
store	100%
mul	100%
add-sub	95%
fma	100%
div/sqrt	100%
other	36%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 31.50 cycles. At this rate:

8% of peak load performance is reached (21.71 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 46fc70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x30(%RSP),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
SUB %R9D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 470343 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x6d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RSI),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RSI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RSI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RBX,%R10,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RBX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%R8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RSI,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x48(%RDI),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x50(%RDI),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x58(%RDI),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x60(%RDI),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x68(%RDI),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x70(%RDI),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x78(%RDI),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x80(%RDI),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x88(%RDI),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RDI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %EBP,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 470024 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x3b4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%R8),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ 0x822ce(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VPBROADCASTQ 0x87704(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 470343 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x6d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD %EBP,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
JMP 470087 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x417>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTD %EBP,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VBROADCASTSD %XMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VPBROADCASTD %R8D,%ZMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPSUBD %ZMM16,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPCMPNLEUD 0x84362(%RIP),%YMM15,%K1																				vect (50.0%)
VEXTRACTI64X4 $0x1,%ZMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPCMPNLEUD 0x873b0(%RIP),%YMM15,%K2																				vect (50.0%)
ADD %R8D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R9D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD 0x40(%RBX,%R8,8),%ZMM15{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%RBX,%R8,8),%ZMM16{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM5,%ZMM16,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R11,%R8,8),%ZMM16{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD 0x40(%R11,%R8,8),%ZMM17{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM17,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD 0x40(%R10,%R8,8),%ZMM17{%K2}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVUPD (%R10,%R8,8),%ZMM18{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM18,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM8,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM16,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM4,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM3,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM12,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM12,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM4,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM3,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM15,%ZMM14,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM14,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM16,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM4,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM17,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VPBROADCASTQ 0x81ec9(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VPBROADCASTQ 0x872ff(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VFMADD231PD %ZMM9,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM3,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM18,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM9,%ZMM18,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM9,%ZMM18,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM7,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM8,%ZMM7,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM6,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM12,%ZMM6,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM12,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVDQA64 %ZMM11,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM8,%ZMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM4,%ZMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VADDPD %ZMM11,%ZMM10,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VRNDSCALEPD $0xb,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM4,%ZMM10,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VSUBPD %ZMM8,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM7,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM5,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,0x40(%RSI,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x18(%RDI),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM3,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x20(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM7,%ZMM10,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x28(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM5,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,0x40(%RDX,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDX,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VBROADCASTSD 0x30(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %ZMM3,%ZMM10,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM9,%ZMM10,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD 0x38(%RDI),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM7,%ZMM10,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM10,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD 0x40(%RDI),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %ZMM5,%ZMM6,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM6,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM1,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM3,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VFMADD231PD %ZMM9,%ZMM9,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VSQRTPD %ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	vect (100.0%)
VMOVUPD %ZMM9,0x40(%RAX,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM3,(%RAX,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RCX,%R8,8){%K2}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM0,(%RCX,%R8,8){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	1	vect (100.0%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	0.72	1.21
○Loop 1190 - - exec	0.72	1.20

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code