OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&, bool)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.62% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x44a3b0 PUSH	%RBP

0x44a3b1 PUSH	%R15

0x44a3b3 PUSH	%R14

0x44a3b5 PUSH	%R13

0x44a3b7 PUSH	%R12

0x44a3b9 PUSH	%RBX

0x44a3ba SUB	$0x78,%RSP

0x44a3be MOV	%RCX,%RBX

0x44a3c1 MOV	%RDX,%R15

0x44a3c4 MOV	%RDI,%R14

0x44a3c7 CMPL	$0,0xc(%RDI)

0x44a3cb JNE	44a420

0x44a3cd MOV	%RSI,%R12

0x44a3d0 MOV	0x468(%R14),%RDI

0x44a3d7 CALL	48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x44a3dc MOV	0x470(%R14),%RDI

0x44a3e3 MOV	0x478(%R14),%EDX

0x44a3ea MOV	0x47c(%R14),%ECX

0x44a3f1 LEA	0x90(%R14),%R8

0x44a3f8 LEA	0x110(%R14),%R9

0x44a3ff LEA	0x150(%R14),%RAX

0x44a406 MOV	(%RDI),%R10

0x44a409 MOV	%RAX,(%RSP)

0x44a40d MOV	%R12,%RSI

0x44a410 CALLQ	0x28(%R10)

0x44a414 MOV	0x468(%R14),%RDI

0x44a41b CALL	48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x44a420 MOVSXD	0x484(%R14),%RAX

0x44a427 TEST	%RAX,%RAX

0x44a42a JE	44a4ca

0x44a430 CMP	$0x1,%EAX

0x44a433 JNE	44a4dc

0x44a439 MOV	0x100(%R14),%RAX

0x44a440 VMOVDDUP	(%RAX),%XMM0

0x44a444 MOV	0x140(%R14),%RAX

0x44a44b MOVQ	$0,0x20(%RSP)

0x44a454 VMULPD	(%RAX),%XMM0,%XMM1

0x44a458 VMOVUPD	%XMM1,0x10(%RSP)

0x44a45e VMULSD	0x10(%RAX),%XMM0,%XMM2

0x44a463 VMOVSD	%XMM2,0x20(%RSP)

0x44a469 MOVSXD	0x478(%R14),%RAX

0x44a470 MOV	0x18(%R15),%RCX

0x44a474 LEA	(%RAX,%RAX,2),%RDX

0x44a478 VADDPD	(%RCX,%RDX,8),%XMM1,%XMM2

0x44a47d VMOVUPD	%XMM2,(%RCX,%RDX,8)

0x44a482 VMOVSD	0x10(%RCX,%RDX,8),%XMM2

0x44a488 VADDSD	0x20(%RSP),%XMM2,%XMM2

0x44a48e VMOVSD	%XMM2,0x10(%RCX,%RDX,8)

0x44a494 MOV	0x180(%R14),%RCX

0x44a49b VMOVUPD	0x18(%RSP),%XMM2

0x44a4a1 VMULPD	%XMM2,%XMM2,%XMM2

0x44a4a5 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0x44a4aa VADDSD	%XMM3,%XMM2,%XMM2

0x44a4ae MOV	0x18(%RBX),%RDX

0x44a4b2 VFMADD231SD	%XMM1,%XMM1,%XMM2

0x44a4b7 VMOVSD	(%RDX,%RAX,8),%XMM1

0x44a4bc VFMADD231SD	(%RCX),%XMM0,%XMM1

0x44a4c1 VSUBSD	%XMM2,%XMM1,%XMM0

0x44a4c5 VMOVSD	%XMM0,(%RDX,%RAX,8)

0x44a4ca ADD	$0x78,%RSP

0x44a4ce POP	%RBX

0x44a4cf POP	%R12

0x44a4d1 POP	%R13

0x44a4d3 POP	%R14

0x44a4d5 POP	%R15

0x44a4d7 POP	%RBP

0x44a4d8 VZEROUPPER

0x44a4db RET

0x44a4dc MOVSXD	0x478(%R14),%RCX

0x44a4e3 MOV	%RCX,0x68(%RSP)

0x44a4e8 MOV	0xd8(%R14),%RDX

0x44a4ef MOV	0x100(%R14),%R8

0x44a4f6 MOV	0x180(%R14),%RDI

0x44a4fd MOV	0x158(%R14),%R12

0x44a504 MOV	0x480(%R14),%R9D

0x44a50b MOV	0x140(%R14),%R10

0x44a512 MOV	0x118(%R14),%RCX

0x44a519 MOV	0x18(%R15),%R11

0x44a51d MOV	0x18(%RBX),%RBX

0x44a521 DEC	%RAX

0x44a524 MOV	%R9D,%R14D

0x44a527 AND	$-0x8,%R14D

0x44a52b VPBROADCASTQ	%R9,%ZMM0

0x44a531 MOV	%R9D,%R15D

0x44a534 SHR	$0x2,%R15D

0x44a538 MOV	%R9D,%EBP

0x44a53b AND	$-0x4,%EBP

0x44a53e MOV	%RDX,0x38(%RSP)

0x44a543 LEA	(,%RDX,8),%RSI

0x44a54b SAL	$0x3,%RCX

0x44a54f LEA	(%RCX,%RCX,2),%RDX

0x44a553 LEA	(%R15,%R15,2),%RCX

0x44a557 SAL	$0x5,%R15

0x44a55b SAL	$0x5,%RCX

0x44a55f ADD	%R10,%RCX

0x44a562 ADD	$0x10,%RCX

0x44a566 MOV	%RCX,0x40(%RSP)

0x44a56b MOV	%RDX,%RCX

0x44a56e ADD	$0x58,%R10

0x44a572 VMOVDQU64	0xab2c4(%RIP),%ZMM1

0x44a57c VXORPD	%XMM2,%XMM2,%XMM2

0x44a580 MOV	%R12,0x30(%RSP)

0x44a585 LEA	(,%R12,8),%RDX

0x44a58d MOV	%RDX,0x60(%RSP)

0x44a592 MOV	%RDI,0x50(%RSP)

0x44a597 MOV	%RDI,%RDX

0x44a59a XOR	%EDI,%EDI

0x44a59c MOV	%R8,0x58(%RSP)

0x44a5a1 MOV	%RCX,0x48(%RSP)

0x44a5a6 JMP	44a636

0x44a5ab NOPL	(%RAX,%RAX,1)

(851) 0x44a5b0 VMOVUPD	%XMM6,0x10(%RSP)

(851) 0x44a5b6 VMOVSD	%XMM7,0x20(%RSP)

(851) 0x44a5bc MOV	0x68(%RSP),%RDI

(851) 0x44a5c1 MOV	0x70(%RSP),%R13

(851) 0x44a5c6 ADD	%R13,%RDI

(851) 0x44a5c9 LEA	(%RDI,%RDI,2),%R12

(851) 0x44a5cd VMOVUPD	0x10(%RSP),%XMM6

(851) 0x44a5d3 VADDPD	(%R11,%R12,8),%XMM6,%XMM7

(851) 0x44a5d9 VMOVUPD	%XMM7,(%R11,%R12,8)

(851) 0x44a5df VMOVSD	0x10(%R11,%R12,8),%XMM7

(851) 0x44a5e6 VADDSD	0x20(%RSP),%XMM7,%XMM7

(851) 0x44a5ec VMOVSD	%XMM7,0x10(%R11,%R12,8)

(851) 0x44a5f3 VMOVUPD	0x18(%RSP),%XMM7

(851) 0x44a5f9 VMULPD	%XMM7,%XMM7,%XMM7

(851) 0x44a5fd VSHUFPD	$0x1,%XMM7,%XMM7,%XMM8

(851) 0x44a602 VADDSD	%XMM7,%XMM8,%XMM7

(851) 0x44a606 VSUBSD	%XMM7,%XMM5,%XMM5

(851) 0x44a60a VFMSUB213SD	(%RBX,%RDI,8),%XMM6,%XMM6

(851) 0x44a610 VSUBSD	%XMM6,%XMM5,%XMM5

(851) 0x44a614 VMOVSD	%XMM5,(%RBX,%RDI,8)

(851) 0x44a619 LEA	0x1(%R13),%RDI

(851) 0x44a61d ADD	%RSI,%R8

(851) 0x44a620 ADD	0x60(%RSP),%RDX

(851) 0x44a625 ADD	%RCX,%R10

(851) 0x44a628 ADD	%RCX,0x40(%RSP)

(851) 0x44a62d CMP	%RAX,%R13

(851) 0x44a630 JE	44a4ca

(851) 0x44a636 TEST	%R9D,%R9D

(851) 0x44a639 MOV	%RDI,0x70(%RSP)

(851) 0x44a63e JLE	44a6c0

(851) 0x44a644 TEST	%R14,%R14

(851) 0x44a647 JE	44a6f0

(851) 0x44a64d MOV	0x30(%RSP),%R13

(851) 0x44a652 IMUL	%RDI,%R13

(851) 0x44a656 MOV	0x38(%RSP),%R12

(851) 0x44a65b IMUL	%RDI,%R12

(851) 0x44a65f VXORPD	%XMM5,%XMM5,%XMM5

(851) 0x44a663 XOR	%EDI,%EDI

(851) 0x44a665 NOPW	%CS:(%RAX,%RAX,1)

  (854) 0x44a670 VMOVUPD	(%RDX,%RDI,8),%ZMM6

  (854) 0x44a677 VFMADD231PD	(%R8,%RDI,8),%ZMM6,%ZMM5

  (854) 0x44a67e ADD	$0x8,%RDI

  (854) 0x44a682 CMP	%R14,%RDI

  (854) 0x44a685 JB	44a670

(851) 0x44a687 VEXTRACTF64X4	$0x1,%ZMM5,%YMM6

(851) 0x44a68e VADDPD	%ZMM6,%ZMM5,%ZMM5

(851) 0x44a694 VEXTRACTF128	$0x1,%YMM5,%XMM6

(851) 0x44a69a VADDPD	%XMM6,%XMM5,%XMM5

(851) 0x44a69e VSHUFPD	$0x1,%XMM5,%XMM5,%XMM6

(851) 0x44a6a3 VADDSD	%XMM6,%XMM5,%XMM5

(851) 0x44a6a7 MOV	%R14,%RDI

(851) 0x44a6aa CMP	%R9,%R14

(851) 0x44a6ad JE	44a6c4

(851) 0x44a6af JMP	44a708

0x44a6b1 NOPW	%CS:(%RAX,%RAX,1)

(851) 0x44a6c0 VXORPD	%XMM5,%XMM5,%XMM5

(851) 0x44a6c4 VMOVUPD	%XMM2,0x10(%RSP)

(851) 0x44a6ca MOVQ	$0,0x20(%RSP)

(851) 0x44a6d3 TEST	%R9D,%R9D

(851) 0x44a6d6 JG	44a7b0

(851) 0x44a6dc JMP	44a5bc

0x44a6e1 NOPW	%CS:(%RAX,%RAX,1)

(851) 0x44a6f0 MOV	0x30(%RSP),%R13

(851) 0x44a6f5 IMUL	%RDI,%R13

(851) 0x44a6f9 MOV	0x38(%RSP),%R12

(851) 0x44a6fe IMUL	%RDI,%R12

(851) 0x44a702 VXORPD	%XMM5,%XMM5,%XMM5

(851) 0x44a706 XOR	%EDI,%EDI

(851) 0x44a708 VPBROADCASTQ	%RDI,%ZMM6

(851) 0x44a70e VPSUBQ	%ZMM6,%ZMM0,%ZMM6

(851) 0x44a714 VPCMPNLEUQ	%ZMM1,%ZMM6,%K1

(851) 0x44a71b ADD	%RDI,%R13

(851) 0x44a71e MOV	%RSI,%RCX

(851) 0x44a721 MOV	%R10,%RSI

(851) 0x44a724 MOV	%R11,%R10

(851) 0x44a727 MOV	%RBP,%R11

(851) 0x44a72a MOV	%RBX,%RBP

(851) 0x44a72d MOV	%RAX,%RBX

(851) 0x44a730 MOV	0x50(%RSP),%RAX

(851) 0x44a735 VMOVUPD	(%RAX,%R13,8),%ZMM6{%K1}{z}

(851) 0x44a73c MOV	%RBX,%RAX

(851) 0x44a73f MOV	%RBP,%RBX

(851) 0x44a742 MOV	%R11,%RBP

(851) 0x44a745 MOV	%R10,%R11

(851) 0x44a748 MOV	%RSI,%R10

(851) 0x44a74b MOV	%RCX,%RSI

(851) 0x44a74e MOV	0x48(%RSP),%RCX

(851) 0x44a753 VMOVAPD	%ZMM6,%ZMM4{%K1}

(851) 0x44a759 ADD	%RDI,%R12

(851) 0x44a75c MOV	0x58(%RSP),%RDI

(851) 0x44a761 VMOVUPD	(%RDI,%R12,8),%ZMM7{%K1}{z}

(851) 0x44a768 VMOVAPD	%ZMM7,%ZMM3{%K1}

(851) 0x44a76e VMULPD	%ZMM7,%ZMM6,%ZMM6{%K1}{z}

(851) 0x44a774 VEXTRACTF64X4	$0x1,%ZMM6,%YMM7

(851) 0x44a77b VADDPD	%ZMM7,%ZMM6,%ZMM6

(851) 0x44a781 VEXTRACTF128	$0x1,%YMM6,%XMM7

(851) 0x44a787 VADDPD	%XMM7,%XMM6,%XMM6

(851) 0x44a78b VSHUFPD	$0x1,%XMM6,%XMM6,%XMM7

(851) 0x44a790 VADDSD	%XMM7,%XMM6,%XMM6

(851) 0x44a794 VADDSD	%XMM6,%XMM5,%XMM5

(851) 0x44a798 VMOVUPD	%XMM2,0x10(%RSP)

(851) 0x44a79e MOVQ	$0,0x20(%RSP)

(851) 0x44a7a7 TEST	%R9D,%R9D

(851) 0x44a7aa JLE	44a5bc

(851) 0x44a7b0 VXORPD	%XMM6,%XMM6,%XMM6

(851) 0x44a7b4 VXORPD	%XMM7,%XMM7,%XMM7

(851) 0x44a7b8 CMP	$0x4,%R9D

(851) 0x44a7bc JB	44a82f

(851) 0x44a7be MOV	%R10,%R12

(851) 0x44a7c1 XOR	%R13D,%R13D

(851) 0x44a7c4 NOPW	%CS:(%RAX,%RAX,1)

  (853) 0x44a7d0 VMOVDDUP	(%R8,%R13,1),%XMM8

  (853) 0x44a7d6 VFMADD231SD	-0x48(%R12),%XMM8,%XMM7

  (853) 0x44a7dd VMOVDDUP	0x8(%R8,%R13,1),%XMM9

  (853) 0x44a7e4 VFMADD231SD	-0x30(%R12),%XMM9,%XMM7

  (853) 0x44a7eb VMOVDDUP	0x10(%R8,%R13,1),%XMM10

  (853) 0x44a7f2 VFMADD231SD	-0x18(%R12),%XMM10,%XMM7

  (853) 0x44a7f9 VFMADD231PD	-0x58(%R12),%XMM8,%XMM6

  (853) 0x44a800 VFMADD231PD	-0x40(%R12),%XMM9,%XMM6

  (853) 0x44a807 VFMADD231PD	-0x28(%R12),%XMM10,%XMM6

  (853) 0x44a80e VMOVDDUP	0x18(%R8,%R13,1),%XMM8

  (853) 0x44a815 VFMADD231PD	-0x10(%R12),%XMM8,%XMM6

  (853) 0x44a81c VFMADD231SD	(%R12),%XMM8,%XMM7

  (853) 0x44a822 ADD	$0x20,%R13

  (853) 0x44a826 ADD	$0x60,%R12

  (853) 0x44a82a CMP	%R13,%R15

  (853) 0x44a82d JNE	44a7d0

(851) 0x44a82f CMP	%R9,%RBP

(851) 0x44a832 JAE	44a5b0

(851) 0x44a838 MOV	0x40(%RSP),%R12

(851) 0x44a83d MOV	%RBP,%R13

  (852) 0x44a840 VMOVDDUP	(%R8,%R13,8),%XMM8

  (852) 0x44a846 VFMADD231PD	-0x10(%R12),%XMM8,%XMM6

  (852) 0x44a84d VFMADD231SD	(%R12),%XMM8,%XMM7

  (852) 0x44a853 INC	%R13

  (852) 0x44a856 ADD	$0x18,%R12

  (852) 0x44a85a CMP	%R13,%R9

  (852) 0x44a85d JNE	44a840

(851) 0x44a85f JMP	44a5b0

0x44a864 NOPW	%CS:(%RAX,%RAX,1)

0x44a86e XCHG	%AX,%AX

Coverage (%)	Name	Module
►46.69+	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►46.51+	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►1.50+	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.109	exec
►1.45+	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.43+	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.109	exec
►1.42+	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 5.00 cycles (2.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.50 to 10.39 cycles (1.39x speedup).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►
unknown: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 332 bytes (41 double precision FP elements). The binary function is storing 136 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	116
loop length	554
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	2
nb stack references	12
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	13.25	13.25	13.25	13.25	3.00	3.00	3.00	3.00	2.50	2.50
cycles	5.67	5.67	5.67	5.67	5.67	5.67	13.25	13.25	13.25	13.25	3.00	3.00	3.00	3.00	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	13.25
Overall L1	14.50

Vectorization ratios

INT

all	9%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	40%
load	33%
store	40%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	23%
load	28%
store	13%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	15%
load	27%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	17%
load	16%
store	17%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	16%
load	20%
store	13%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

8% of peak load performance is reached (22.90 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 13.25 cycles (1.09x speedup).

ASM code

In the binary file, the address of the function is: 44a3b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPL $0,0xc(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 44a420 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x70>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x468(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x470(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x478(%R14),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x47c(%R14),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x90(%R14),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x110(%R14),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x150(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALLQ 0x28(%R10)	4	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	2.20	N/A
MOV 0x468(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD 0x484(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 44a4ca <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x11a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 44a4dc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x12c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x100(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDDUP (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x140(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMULPD (%RAX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM1,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULSD 0x10(%RAX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD 0x478(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RAX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD (%RCX,%RDX,8),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM2,(%RCX,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD 0x10(%RCX,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x20(%RSP),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,0x10(%RCX,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x180(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231SD %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD (%RCX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVSXD 0x478(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd8(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x100(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x180(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x158(%R14),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x480(%R14),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x140(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R9,%ZMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %R9D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x2,%R15D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R9D,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x4,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%RDX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%RCX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%R15,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x5,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x58,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU64 0xab2c4(%RIP),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%R12,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R8,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 44a636 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x286>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 5.00 cycles (2.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►
unknown: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 332 bytes (41 double precision FP elements). The binary function is storing 136 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	116
loop length	554
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	2
nb stack references	12
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	13.25	13.25	13.25	13.25	3.00	3.00	3.00	3.00	2.50	2.50
cycles	5.67	5.67	5.67	5.67	5.67	5.67	13.25	13.25	13.25	13.25	3.00	3.00	3.00	3.00	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	13.25
Overall L1	14.50

Vectorization ratios

INT

all	9%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	40%
load	33%
store	40%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	23%
load	28%
store	13%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	15%
load	27%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	17%
load	16%
store	17%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	16%
load	20%
store	13%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

8% of peak load performance is reached (22.90 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 44a3b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPL $0,0xc(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JNE 44a420 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x70>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x468(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x470(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x478(%R14),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x47c(%R14),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x90(%R14),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x110(%R14),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x150(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALLQ 0x28(%R10)	4	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	2.20	N/A
MOV 0x468(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD 0x484(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 44a4ca <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x11a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 44a4dc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x12c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x100(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDDUP (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x140(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMULPD (%RAX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM1,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULSD 0x10(%RAX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD 0x478(%R14),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RAX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD (%RCX,%RDX,8),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVUPD %XMM2,(%RCX,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD 0x10(%RCX,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x20(%RSP),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,0x10(%RCX,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x180(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVUPD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231SD %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD231SD (%RCX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVSXD 0x478(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd8(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x100(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x180(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x158(%R14),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x480(%R14),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x140(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R9,%ZMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %R9D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x2,%R15D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R9D,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x4,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%RDX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%RCX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%R15,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x5,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x58,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU64 0xab2c4(%RIP),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%R12,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R8,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 44a636 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x286>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus:...–	0.62	1.03
▼Loop 851 - - exec–	0.00	0.01
○Loop 853 - - exec	0.38	0.63
○Loop 854 - - exec	0.23	0.39
○Loop 852 - - exec	0.00	0.00

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