OV - exec - Function qmcplusplus::SPOSet::evaluateDetRatios(qmcplusplus::VirtualParticleSet const&, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<double, std::allocator<double> > const&, std::vector<double, std::allocator<double> >&)

	Function: qmcplusplus::SPOSet::evaluateDetRatios(qmcplusplus::VirtualParticleSet const&, qmcplusplus ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x43f890 CMPQ	$0,0x260(%RSI)

0x43f898 JE	43fa23

0x43f89e PUSH	%RBP

0x43f89f PUSH	%R15

0x43f8a1 PUSH	%R14

0x43f8a3 PUSH	%R13

0x43f8a5 PUSH	%R12

0x43f8a7 PUSH	%RBX

0x43f8a8 SUB	$0x88,%RSP

0x43f8af MOV	%R8,%RBX

0x43f8b2 MOV	%RCX,%R14

0x43f8b5 MOV	%RDX,%R15

0x43f8b8 MOV	%RSI,%R12

0x43f8bb MOV	%RDI,%R13

0x43f8be XOR	%EBP,%EBP

0x43f8c0 JMP	43f8ed

0x43f8c2 NOPW	%CS:(%RAX,%RAX,1)

(754) 0x43f8d0 VXORPD	%XMM0,%XMM0,%XMM0

(754) 0x43f8d4 MOV	(%RBX),%RAX

(754) 0x43f8d7 VMOVSD	%XMM0,(%RAX,%RBP,8)

(754) 0x43f8dc INC	%RBP

(754) 0x43f8df CMP	%RBP,0x260(%R12)

(754) 0x43f8e7 JBE	43fa12

(754) 0x43f8ed MOV	(%R13),%RAX

(754) 0x43f8f1 MOV	%R13,%RDI

(754) 0x43f8f4 MOV	%R12,%RSI

(754) 0x43f8f7 MOV	%EBP,%EDX

(754) 0x43f8f9 MOV	%R15,%RCX

(754) 0x43f8fc VZEROUPPER

(754) 0x43f8ff CALLQ	0x10(%RAX)

(754) 0x43f902 MOV	0x8(%R15),%RDX

(754) 0x43f906 TEST	%EDX,%EDX

(754) 0x43f908 JLE	43f8d0

(754) 0x43f90a MOV	0x18(%R15),%RAX

(754) 0x43f90e MOV	0x18(%R14),%RCX

(754) 0x43f912 MOVSXD	%EDX,%RSI

(754) 0x43f915 MOV	%RSI,%RDX

(754) 0x43f918 AND	$-0x8,%RDX

(754) 0x43f91c JE	43f980

(754) 0x43f91e VXORPD	%XMM0,%XMM0,%XMM0

(754) 0x43f922 XOR	%EDI,%EDI

(754) 0x43f924 NOPW	%CS:(%RAX,%RAX,1)

  (755) 0x43f930 VMOVUPD	(%RCX,%RDI,8),%ZMM1

  (755) 0x43f937 VFMADD231PD	(%RAX,%RDI,8),%ZMM1,%ZMM0

  (755) 0x43f93e ADD	$0x8,%RDI

  (755) 0x43f942 CMP	%RDX,%RDI

  (755) 0x43f945 JL	43f930

(754) 0x43f947 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

(754) 0x43f94e VADDPD	%ZMM1,%ZMM0,%ZMM0

(754) 0x43f954 VEXTRACTF128	$0x1,%YMM0,%XMM1

(754) 0x43f95a VADDPD	%XMM1,%XMM0,%XMM0

(754) 0x43f95e VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(754) 0x43f963 VADDSD	%XMM1,%XMM0,%XMM0

(754) 0x43f967 CMP	%RDX,%RSI

(754) 0x43f96a VMOVUPD	(%RSP),%ZMM3

(754) 0x43f971 JNE	43f995

(754) 0x43f973 JMP	43f8d4

0x43f978 NOPL	(%RAX,%RAX,1)

(754) 0x43f980 VPBROADCASTQ	%RSI,%ZMM1

(754) 0x43f986 VXORPD	%XMM0,%XMM0,%XMM0

(754) 0x43f98a XOR	%EDX,%EDX

(754) 0x43f98c VMOVUPD	(%RSP),%ZMM3

(754) 0x43f993 JMP	43f99b

(754) 0x43f995 VPBROADCASTQ	%RSI,%ZMM1

(754) 0x43f99b VPBROADCASTQ	%RDX,%ZMM2

(754) 0x43f9a1 VPSUBQ	%ZMM2,%ZMM1,%ZMM1

(754) 0x43f9a7 VPCMPNLEUQ	0xb57ce(%RIP),%ZMM1,%K1

(754) 0x43f9b2 VMOVUPD	(%RCX,%RDX,8),%ZMM1{%K1}{z}

(754) 0x43f9b9 VMOVAPD	%ZMM1,%ZMM3{%K1}

(754) 0x43f9bf VMOVUPD	%ZMM3,(%RSP)

(754) 0x43f9c6 VMOVUPD	(%RAX,%RDX,8),%ZMM2{%K1}{z}

(754) 0x43f9cd VMOVUPD	0x40(%RSP),%ZMM3

(754) 0x43f9d5 VMOVAPD	%ZMM2,%ZMM3{%K1}

(754) 0x43f9db VMOVUPD	%ZMM3,0x40(%RSP)

(754) 0x43f9e3 VMULPD	%ZMM2,%ZMM1,%ZMM1{%K1}{z}

(754) 0x43f9e9 VEXTRACTF64X4	$0x1,%ZMM1,%YMM2

(754) 0x43f9f0 VADDPD	%ZMM2,%ZMM1,%ZMM1

(754) 0x43f9f6 VEXTRACTF128	$0x1,%YMM1,%XMM2

(754) 0x43f9fc VADDPD	%XMM2,%XMM1,%XMM1

(754) 0x43fa00 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

(754) 0x43fa05 VADDSD	%XMM2,%XMM1,%XMM1

(754) 0x43fa09 VADDSD	%XMM1,%XMM0,%XMM0

(754) 0x43fa0d JMP	43f8d4

0x43fa12 ADD	$0x88,%RSP

0x43fa19 POP	%RBX

0x43fa1a POP	%R12

0x43fa1c POP	%R13

0x43fa1e POP	%R14

0x43fa20 POP	%R15

0x43fa22 POP	%RBP

0x43fa23 VZEROUPPER

0x43fa26 RET

0x43fa27 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Module
►95.19+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.84+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.13 to 0.22 cycles (14.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes.

General properties

nb instructions	28
nb uops	25
loop length	102
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.25	0.25	0.25	0.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.25	0.25	0.25	0.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Dispatch	1.00
Overall L1	3.13

Vectorization ratios

all	12%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.13 cycles. At this rate:

1% of peak load performance is reached (2.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.13 to 1.00 cycles (3.13x speedup).

ASM code

In the binary file, the address of the function is: 43f890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
CMPQ $0,0x260(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 43fa23 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x193>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBP,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43f8ed <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes.

General properties

nb instructions	28
nb uops	25
loop length	102
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.25	0.25	0.25	0.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.25	0.25	0.25	0.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Dispatch	1.00
Overall L1	3.13

Vectorization ratios

all	12%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.13 cycles. At this rate:

1% of peak load performance is reached (2.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 43f890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
CMPQ $0,0x260(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 43fa23 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x193>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBP,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43f8ed <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::SPOSet::evaluateDetRatios(qmcplusplus::VirtualParticleSet const&, qmcplusplus::Vector >&, qmcplusplus::Vector > const&, std::vector >&)–	0.04	0.06
▼Loop 754 - - exec–	0.00	0.01
○Loop 755 - - exec	0.03	0.06

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code