OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: :0-0	Coverage (incl. loops): 10.54% \| (excl. loops): 0.01%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x43e2b0 PUSH	%RBP

0x43e2b1 PUSH	%R15

0x43e2b3 PUSH	%R14

0x43e2b5 PUSH	%R13

0x43e2b7 PUSH	%R12

0x43e2b9 PUSH	%RBX

0x43e2ba SUB	$0x898,%RSP

0x43e2c1 MOV	%R9,0xe8(%RSP)

0x43e2c9 MOV	%R8,0xe0(%RSP)

0x43e2d1 MOV	%RCX,0xd8(%RSP)

0x43e2d9 MOV	%EDX,%EBX

0x43e2db MOV	%RSI,%R13

0x43e2de MOV	%RDI,%R14

0x43e2e1 MOV	0x358(%RDI),%RDI

0x43e2e8 MOV	%RDI,0xf0(%RSP)

0x43e2f0 CALL	48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x43e2f5 MOVSXD	%EBX,%RAX

0x43e2f8 LEA	(%RAX,%RAX,2),%RCX

0x43e2fc SAL	$0x3,%RCX

0x43e300 ADD	0x40(%R13),%RCX

0x43e304 LEA	0x128(%R13),%RDX

0x43e30b CMP	%EAX,0x124(%R13)

0x43e312 CMOVNE	%RCX,%RDX

0x43e316 VMOVDDUP	(%RDX),%XMM0

0x43e31a VMULSD	0xe8(%R14),%XMM0,%XMM1

0x43e323 VMOVDDUP	0x8(%RDX),%XMM2

0x43e328 VFMADD231SD	0x100(%R14),%XMM2,%XMM1

0x43e331 VMOVDDUP	0x10(%RDX),%XMM3

0x43e336 VFMADD231SD	0x118(%R14),%XMM3,%XMM1

0x43e33f VMULPD	0xd8(%R14),%XMM0,%XMM0

0x43e348 VFMADD231PD	0xf0(%R14),%XMM2,%XMM0

0x43e351 VFMADD231PD	0x108(%R14),%XMM3,%XMM0

0x43e35a VMOVUPD	%XMM0,0xa0(%RSP)

0x43e363 VMOVSD	%XMM1,0xb0(%RSP)

0x43e36c MOV	$0x7,%AL

0x43e36e KMOVD	%EAX,%K1

0x43e372 VMOVUPD	0xa0(%RSP),%YMM0{%K1}{z}

0x43e37a VXORPD	%XMM1,%XMM1,%XMM1

0x43e37e VCMPPD	$0x1,%YMM1,%YMM0,%K2

0x43e385 VCMPPD	$0xe,0xb6d00(%RIP){1to0},%YMM0,%K0{%K2}

0x43e390 VROUNDPD	$0x9,%YMM0,%YMM1

0x43e396 KNOTW	%K0,%K2

0x43e39a VSUBPD	%YMM1,%YMM0,%YMM0{%K2}{z}

0x43e3a0 VMOVUPD	%YMM0,0xa0(%RSP){%K1}

0x43e3a8 MOV	%R14,0x50(%RSP)

0x43e3ad MOV	0x30(%R14),%EAX

0x43e3b1 MOV	%RAX,0x58(%RSP)

0x43e3b6 TEST	%EAX,%EAX

0x43e3b8 JLE	43f6ef

0x43e3be MOV	0x50(%RSP),%RAX

0x43e3c3 MOV	0x2f8(%RAX),%RCX

0x43e3ca MOV	%RCX,0x130(%RSP)

0x43e3d2 MOV	0x310(%RAX),%RCX

0x43e3d9 MOV	%RCX,0x128(%RSP)

0x43e3e1 VMOVSD	0xa0(%RSP),%XMM0

0x43e3ea VMOVSD	%XMM0,0x120(%RSP)

0x43e3f3 VMOVSD	0xa8(%RSP),%XMM0

0x43e3fc VMOVSD	%XMM0,0x118(%RSP)

0x43e405 VMOVSD	0xb0(%RSP),%XMM0

0x43e40e VMOVSD	%XMM0,0x110(%RSP)

0x43e417 MOV	0x328(%RAX),%RCX

0x43e41e MOV	%RCX,0x108(%RSP)

0x43e426 MOV	0x340(%RAX),%RCX

0x43e42d MOV	%RCX,0x100(%RSP)

0x43e435 MOVSXD	0x40(%RAX),%R12

0x43e439 LEA	(,%R12,8),%R15

0x43e441 DECQ	0x58(%RSP)

0x43e446 MOV	%R12,%RDI

0x43e449 AND	$-0x8,%RDI

0x43e44d VPBROADCASTQ	%R12,%ZMM0

0x43e453 VMOVDQU64	%ZMM0,0x510(%RSP)

0x43e45e XOR	%EDX,%EDX

0x43e460 VMOVDDUP	0xb3bb0(%RIP),%XMM0

0x43e468 VMOVUPS	%XMM0,0x210(%RSP)

0x43e471 MOV	%RDI,0x78(%RSP)

0x43e476 MOV	%R12,0x70(%RSP)

0x43e47b MOV	%R15,0xf8(%RSP)

0x43e483 JMP	43e4cd

0x43e485 NOPW	%CS:(%RAX,%RAX,1)

(749) 0x43e490 MOV	0x60(%RSP),%R11

(749) 0x43e495 VMOVUPD	%ZMM14,0x3d0(%RSP)

(749) 0x43e4a0 VMOVUPD	%ZMM13,0x410(%RSP)

(749) 0x43e4ab VMOVUPD	%ZMM12,0x450(%RSP)

(749) 0x43e4b6 LEA	0x1(%R11),%RDX

(749) 0x43e4ba CMP	0x58(%RSP),%R11

(749) 0x43e4bf MOV	0xf8(%RSP),%R15

(749) 0x43e4c7 JE	43f6ef

(749) 0x43e4cd LEA	(,%RDX,8),%RAX

(749) 0x43e4d5 MOV	0x130(%RSP),%RCX

(749) 0x43e4dd MOV	(%RCX,%RDX,8),%R12

(749) 0x43e4e1 MOV	%RDX,0x60(%RSP)

(749) 0x43e4e6 LEA	(%RDX,%RDX,2),%RCX

(749) 0x43e4ea MOV	0x128(%RSP),%RDX

(749) 0x43e4f2 MOV	(%RDX,%RCX,8),%RBX

(749) 0x43e4f6 LEA	(%RAX,%RAX,4),%RAX

(749) 0x43e4fa MOV	0x108(%RSP),%RCX

(749) 0x43e502 MOV	0x18(%RCX,%RAX,1),%RCX

(749) 0x43e507 MOV	%RCX,(%RSP)

(749) 0x43e50b MOV	0x100(%RSP),%RCX

(749) 0x43e513 MOV	0x18(%RCX,%RAX,1),%R13

(749) 0x43e518 VMOVSD	0x120(%RSP),%XMM0

(749) 0x43e521 VSUBSD	0x28(%R12),%XMM0,%XMM0

(749) 0x43e528 VMOVSD	0x118(%RSP),%XMM1

(749) 0x43e531 VSUBSD	0x50(%R12),%XMM1,%XMM1

(749) 0x43e538 VMOVSD	0x110(%RSP),%XMM2

(749) 0x43e541 VSUBSD	0x78(%R12),%XMM2,%XMM2

(749) 0x43e548 VMOVSD	0x48(%R12),%XMM3

(749) 0x43e54f VMOVSD	0x70(%R12),%XMM4

(749) 0x43e556 VMOVUPD	%XMM3,0x230(%RSP)

(749) 0x43e55f VMULSD	%XMM0,%XMM3,%XMM0

(749) 0x43e563 MOVSXD	0x38(%R12),%RAX

(749) 0x43e568 MOV	%RAX,0x48(%RSP)

(749) 0x43e56d VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM17

(749) 0x43e574 VSUBSD	%XMM17,%XMM0,%XMM3

(749) 0x43e57a VMOVUPD	%XMM4,0x240(%RSP)

(749) 0x43e583 VMULSD	%XMM1,%XMM4,%XMM0

(749) 0x43e587 MOVSXD	0x60(%R12),%RAX

(749) 0x43e58c MOV	%RAX,0x28(%RSP)

(749) 0x43e591 VRNDSCALESD	$0x9,%XMM0,%XMM0,%XMM18

(749) 0x43e598 VSUBSD	%XMM18,%XMM0,%XMM0

(749) 0x43e59e VMOVSD	0x98(%R12),%XMM1

(749) 0x43e5a8 VMOVUPD	%XMM1,0x220(%RSP)

(749) 0x43e5b1 VMULSD	%XMM2,%XMM1,%XMM1

(749) 0x43e5b5 MOVSXD	0x88(%R12),%RAX

(749) 0x43e5bd MOV	%RAX,0x8(%RSP)

(749) 0x43e5c2 VRNDSCALESD	$0x9,%XMM1,%XMM1,%XMM19

(749) 0x43e5c9 VSUBSD	%XMM19,%XMM1,%XMM16

(749) 0x43e5cf VMOVSD	0xb6ac1(%RIP),%XMM13

(749) 0x43e5d7 VMULSD	%XMM3,%XMM13,%XMM1

(749) 0x43e5db VMOVSD	0xb3a35(%RIP),%XMM15

(749) 0x43e5e3 VSUBSD	%XMM1,%XMM15,%XMM2

(749) 0x43e5e7 VMULSD	%XMM3,%XMM3,%XMM4

(749) 0x43e5eb VMOVDDUP	%XMM3,%XMM5

(749) 0x43e5ef VMOVUPD	0x210(%RSP),%XMM7

(749) 0x43e5f8 VBLENDPD	$0x1,%XMM2,%XMM7,%XMM2

(749) 0x43e5fe VMULPD	%XMM2,%XMM5,%XMM2

(749) 0x43e602 VMOVUPD	0xb6ad6(%RIP),%XMM8

(749) 0x43e60a VADDPD	%XMM2,%XMM8,%XMM6

(749) 0x43e60e VUNPCKLPD	%XMM4,%XMM5,%XMM5

(749) 0x43e612 VMOVUPD	0xb6ad6(%RIP),%XMM9

(749) 0x43e61a VFMADD213PD	%XMM9,%XMM6,%XMM5

(749) 0x43e61f VMOVUPD	%XMM5,0x270(%RSP)

(749) 0x43e628 VMOVAPD	%XMM3,%XMM5

(749) 0x43e62c VMOVSD	0xb39fc(%RIP),%XMM14

(749) 0x43e634 VFMADD213SD	%XMM15,%XMM14,%XMM5

(749) 0x43e639 VFMADD213SD	%XMM15,%XMM3,%XMM5

(749) 0x43e63e VFMADD213SD	%XMM13,%XMM3,%XMM5

(749) 0x43e643 VMOVSD	%XMM5,0x280(%RSP)

(749) 0x43e64c VMULSD	%XMM4,%XMM1,%XMM1

(749) 0x43e650 VMOVSD	%XMM1,0x288(%RSP)

(749) 0x43e659 VMOVAPD	%XMM3,%XMM1

(749) 0x43e65d VMOVSD	0xb39d3(%RIP),%XMM6

(749) 0x43e665 VFMADD213SD	%XMM6,%XMM14,%XMM1

(749) 0x43e66a VFMADD213SD	%XMM14,%XMM3,%XMM1

(749) 0x43e66f VMOVSD	%XMM1,0x1f0(%RSP)

(749) 0x43e678 VMOVAPD	%XMM3,%XMM1

(749) 0x43e67c VMOVSD	0xb6a2c(%RIP),%XMM10

(749) 0x43e684 VMOVSD	0xb39ec(%RIP),%XMM11

(749) 0x43e68c VFMADD213SD	%XMM11,%XMM10,%XMM1

(749) 0x43e691 VMULSD	%XMM3,%XMM1,%XMM1

(749) 0x43e695 VMOVSD	%XMM1,0x1f8(%RSP)

(749) 0x43e69e VMOVAPD	%XMM3,%XMM1

(749) 0x43e6a2 VFMSUB213SD	%XMM6,%XMM10,%XMM1

(749) 0x43e6a7 VFNMADD213SD	%XMM15,%XMM3,%XMM1

(749) 0x43e6ac VMOVSD	%XMM1,0x200(%RSP)

(749) 0x43e6b5 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM1

(749) 0x43e6ba VMULSD	%XMM3,%XMM1,%XMM1

(749) 0x43e6be VMOVSD	%XMM1,0x208(%RSP)

(749) 0x43e6c7 VSUBSD	%XMM3,%XMM6,%XMM1

(749) 0x43e6cb VMOVSD	%XMM1,0x1b0(%RSP)

(749) 0x43e6d4 VMOVAPD	%XMM3,%XMM1

(749) 0x43e6d8 VMOVSD	0xb48c8(%RIP),%XMM12

(749) 0x43e6e0 VFMADD213SD	%XMM11,%XMM12,%XMM1

(749) 0x43e6e5 VMOVSD	%XMM1,0x1b8(%RSP)

(749) 0x43e6ee VMOVAPD	%XMM3,%XMM1

(749) 0x43e6f2 VFNMADD213SD	%XMM6,%XMM12,%XMM1

(749) 0x43e6f7 VMOVSD	%XMM1,0x1c0(%RSP)

(749) 0x43e700 VMOVSD	%XMM3,0x1c8(%RSP)

(749) 0x43e709 VMULSD	%XMM0,%XMM13,%XMM1

(749) 0x43e70d VSUBSD	%XMM1,%XMM15,%XMM2

(749) 0x43e711 VMULSD	%XMM0,%XMM0,%XMM3

(749) 0x43e715 VMOVDDUP	%XMM0,%XMM4

(749) 0x43e719 VBLENDPD	$0x1,%XMM2,%XMM7,%XMM2

(749) 0x43e71f VMULPD	%XMM2,%XMM4,%XMM2

(749) 0x43e723 VADDPD	%XMM2,%XMM8,%XMM5

(749) 0x43e727 VUNPCKLPD	%XMM3,%XMM4,%XMM4

(749) 0x43e72b VFMADD213PD	%XMM9,%XMM5,%XMM4

(749) 0x43e730 VMOVUPD	%XMM4,0x250(%RSP)

(749) 0x43e739 VMOVAPD	%XMM0,%XMM4

(749) 0x43e73d VFMADD213SD	%XMM15,%XMM14,%XMM4

(749) 0x43e742 VFMADD213SD	%XMM15,%XMM0,%XMM4

(749) 0x43e747 VFMADD213SD	%XMM13,%XMM0,%XMM4

(749) 0x43e74c VMOVSD	%XMM4,0x260(%RSP)

(749) 0x43e755 VMULSD	%XMM3,%XMM1,%XMM1

(749) 0x43e759 VMOVSD	%XMM1,0x268(%RSP)

(749) 0x43e762 VMOVAPD	%XMM0,%XMM1

(749) 0x43e766 VFMADD213SD	%XMM6,%XMM14,%XMM1

(749) 0x43e76b VFMADD213SD	%XMM14,%XMM0,%XMM1

(749) 0x43e770 VMOVSD	%XMM1,0x1d0(%RSP)

(749) 0x43e779 VMOVAPD	%XMM0,%XMM1

(749) 0x43e77d VFMADD213SD	%XMM11,%XMM10,%XMM1

(749) 0x43e782 VMULSD	%XMM0,%XMM1,%XMM1

(749) 0x43e786 VMOVSD	%XMM1,0x1d8(%RSP)

(749) 0x43e78f VMOVAPD	%XMM0,%XMM1

(749) 0x43e793 VFMSUB213SD	%XMM6,%XMM10,%XMM1

(749) 0x43e798 VFNMADD213SD	%XMM15,%XMM0,%XMM1

(749) 0x43e79d VMOVSD	%XMM1,0x1e0(%RSP)

(749) 0x43e7a6 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM1

(749) 0x43e7ab VMULSD	%XMM0,%XMM1,%XMM1

(749) 0x43e7af VMOVSD	%XMM1,0x1e8(%RSP)

(749) 0x43e7b8 VSUBSD	%XMM0,%XMM6,%XMM1

(749) 0x43e7bc VMOVSD	%XMM1,0x190(%RSP)

(749) 0x43e7c5 VMOVAPD	%XMM0,%XMM1

(749) 0x43e7c9 VFMADD213SD	%XMM11,%XMM12,%XMM1

(749) 0x43e7ce VMOVSD	%XMM1,0x198(%RSP)

(749) 0x43e7d7 VMOVAPD	%XMM0,%XMM1

(749) 0x43e7db VFNMADD213SD	%XMM6,%XMM12,%XMM1

(749) 0x43e7e0 VMOVSD	%XMM1,0x1a0(%RSP)

(749) 0x43e7e9 VMOVSD	%XMM0,0x1a8(%RSP)

(749) 0x43e7f2 VMULSD	%XMM15,%XMM16,%XMM12

(749) 0x43e7f8 VADDSD	0xb68a0(%RIP),%XMM12,%XMM13

(749) 0x43e800 VMULSD	%XMM16,%XMM16,%XMM14

(749) 0x43e806 VFMADD213SD	0xb6899(%RIP),%XMM14,%XMM13

(749) 0x43e80f MOV	0x10(%R12),%RAX

(749) 0x43e814 MOV	%RAX,0x68(%RSP)

(749) 0x43e819 MOV	0x18(%R12),%RAX

(749) 0x43e81e MOV	%RAX,0x40(%RSP)

(749) 0x43e823 MOV	0x20(%R12),%R11

(749) 0x43e828 MOVSXD	0xe8(%R12),%RBP

(749) 0x43e830 TEST	%R15,%R15

(749) 0x43e833 JE	43ea1f

(749) 0x43e839 MOV	%RBX,%RDI

(749) 0x43e83c XOR	%ESI,%ESI

(749) 0x43e83e MOV	%R15,%RDX

(749) 0x43e841 VMOVUPS	%ZMM29,0x4d0(%RSP)

(749) 0x43e84c VMOVUPS	%ZMM26,0x490(%RSP)

(749) 0x43e857 VMOVUPS	%ZMM25,0x310(%RSP)

(749) 0x43e862 VMOVUPS	%ZMM28,0x2d0(%RSP)

(749) 0x43e86d VMOVUPS	%ZMM27,0x290(%RSP)

(749) 0x43e878 VMOVUPS	%ZMM30,0x390(%RSP)

(749) 0x43e883 VMOVUPS	%ZMM31,0x350(%RSP)

(749) 0x43e88e MOV	%R11,0x30(%RSP)

(749) 0x43e893 VMOVUPD	%XMM16,0x90(%RSP)

(749) 0x43e89b VMOVSD	%XMM17,0x20(%RSP)

(749) 0x43e8a3 VMOVSD	%XMM18,0x18(%RSP)

(749) 0x43e8ab VMOVSD	%XMM19,0x10(%RSP)

(749) 0x43e8b3 VMOVUPD	%XMM12,0x80(%RSP)

(749) 0x43e8bc VMOVUPD	%XMM13,0xc0(%RSP)

(749) 0x43e8c5 VMOVSD	%XMM14,0x38(%RSP)

(749) 0x43e8cb VZEROUPPER

(749) 0x43e8ce CALL	4e3580 <_intel_fast_memset>

(749) 0x43e8d3 MOV	(%RSP),%R14

(749) 0x43e8d7 MOV	%R14,%RDI

(749) 0x43e8da XOR	%ESI,%ESI

(749) 0x43e8dc MOV	%R15,%RDX

(749) 0x43e8df CALL	4e3580 <_intel_fast_memset>

(749) 0x43e8e4 LEA	(%R14,%RBP,8),%RDI

(749) 0x43e8e8 XOR	%ESI,%ESI

(749) 0x43e8ea MOV	%R15,%RDX

(749) 0x43e8ed CALL	4e3580 <_intel_fast_memset>

(749) 0x43e8f2 MOV	%RBP,%RAX

(749) 0x43e8f5 SAL	$0x4,%RAX

(749) 0x43e8f9 LEA	(%R14,%RAX,1),%RDI

(749) 0x43e8fd MOV	%RAX,%R14

(749) 0x43e900 XOR	%ESI,%ESI

(749) 0x43e902 MOV	%R15,%RDX

(749) 0x43e905 CALL	4e3580 <_intel_fast_memset>

(749) 0x43e90a MOV	%R13,%RDI

(749) 0x43e90d XOR	%ESI,%ESI

(749) 0x43e90f MOV	%R15,%RDX

(749) 0x43e912 CALL	4e3580 <_intel_fast_memset>

(749) 0x43e917 LEA	(,%RBP,8),%RDI

(749) 0x43e91f ADD	%R13,%RDI

(749) 0x43e922 XOR	%ESI,%ESI

(749) 0x43e924 MOV	%R15,%RDX

(749) 0x43e927 CALL	4e3580 <_intel_fast_memset>

(749) 0x43e92c ADD	%R13,%R14

(749) 0x43e92f MOV	%R14,%RDI

(749) 0x43e932 XOR	%ESI,%ESI

(749) 0x43e934 MOV	%R15,%RDX

(749) 0x43e937 CALL	4e3580 <_intel_fast_memset>

(749) 0x43e93c LEA	(,%RBP,2),%RAX

(749) 0x43e944 ADD	%RBP,%RAX

(749) 0x43e947 LEA	(,%RAX,8),%RDI

(749) 0x43e94f ADD	%R13,%RDI

(749) 0x43e952 XOR	%ESI,%ESI

(749) 0x43e954 MOV	%R15,%RDX

(749) 0x43e957 CALL	4e3580 <_intel_fast_memset>

(749) 0x43e95c MOV	%RBP,%RDI

(749) 0x43e95f SAL	$0x5,%RDI

(749) 0x43e963 ADD	%R13,%RDI

(749) 0x43e966 XOR	%ESI,%ESI

(749) 0x43e968 MOV	%R15,%RDX

(749) 0x43e96b CALL	4e3580 <_intel_fast_memset>

(749) 0x43e970 LEA	(,%RBP,4),%RAX

(749) 0x43e978 ADD	%RBP,%RAX

(749) 0x43e97b LEA	(,%RAX,8),%RDI

(749) 0x43e983 ADD	%R13,%RDI

(749) 0x43e986 XOR	%ESI,%ESI

(749) 0x43e988 MOV	%R15,%RDX

(749) 0x43e98b CALL	4e3580 <_intel_fast_memset>

(749) 0x43e990 VMOVSD	0x38(%RSP),%XMM14

(749) 0x43e996 VMOVUPD	0xc0(%RSP),%XMM13

(749) 0x43e99f VMOVUPD	0x80(%RSP),%XMM12

(749) 0x43e9a8 VMOVSD	0x10(%RSP),%XMM19

(749) 0x43e9b0 VMOVSD	0x18(%RSP),%XMM18

(749) 0x43e9b8 VMOVSD	0x20(%RSP),%XMM17

(749) 0x43e9c0 VMOVUPD	0x90(%RSP),%XMM16

(749) 0x43e9c8 MOV	0x30(%RSP),%R11

(749) 0x43e9cd VMOVUPD	0x350(%RSP),%ZMM31

(749) 0x43e9d8 VMOVUPD	0x390(%RSP),%ZMM30

(749) 0x43e9e3 VMOVUPD	0x290(%RSP),%ZMM27

(749) 0x43e9ee VMOVUPD	0x2d0(%RSP),%ZMM28

(749) 0x43e9f9 VMOVUPD	0x310(%RSP),%ZMM25

(749) 0x43ea04 VMOVUPD	0x490(%RSP),%ZMM26

(749) 0x43ea0f VMOVUPD	0x4d0(%RSP),%ZMM29

(749) 0x43ea1a MOV	0x78(%RSP),%RDI

(749) 0x43ea1f VCVTTSD2SI	%XMM17,%ECX

(749) 0x43ea25 VCVTTSD2SI	%XMM18,%EDX

(749) 0x43ea2b VCVTTSD2SI	%XMM19,%EAX

(749) 0x43ea31 VMOVSD	0xb665f(%RIP),%XMM3

(749) 0x43ea39 VMULSD	%XMM3,%XMM16,%XMM1

(749) 0x43ea3f VMOVSD	0xb35d1(%RIP),%XMM9

(749) 0x43ea47 VSUBSD	%XMM1,%XMM9,%XMM0

(749) 0x43ea4b VMOVSD	0xb35dd(%RIP),%XMM5

(749) 0x43ea53 VFMADD213SD	%XMM5,%XMM16,%XMM0

(749) 0x43ea59 VFMADD213SD	%XMM3,%XMM16,%XMM0

(749) 0x43ea5f VMOVAPD	%XMM16,%XMM2

(749) 0x43ea65 VFMADD213SD	%XMM9,%XMM5,%XMM2

(749) 0x43ea6a VFMADD213SD	%XMM9,%XMM16,%XMM2

(749) 0x43ea70 VFMADD213SD	%XMM3,%XMM16,%XMM2

(749) 0x43ea76 VMOVAPD	%XMM16,%XMM4

(749) 0x43ea7c VMOVSD	0xb35b4(%RIP),%XMM3

(749) 0x43ea84 VFMADD213SD	%XMM3,%XMM5,%XMM4

(749) 0x43ea89 VFMADD213SD	%XMM5,%XMM16,%XMM4

(749) 0x43ea8f VMOVAPD	%XMM16,%XMM5

(749) 0x43ea95 VMOVSD	0xb6613(%RIP),%XMM7

(749) 0x43ea9d VMOVSD	0xb35d3(%RIP),%XMM8

(749) 0x43eaa5 VFMADD213SD	%XMM8,%XMM7,%XMM5

(749) 0x43eaaa VMOVAPD	%XMM16,%XMM6

(749) 0x43eab0 VFMSUB213SD	%XMM3,%XMM7,%XMM6

(749) 0x43eab5 VFNMADD213SD	%XMM9,%XMM16,%XMM6

(749) 0x43eabb VSUBSD	%XMM16,%XMM3,%XMM9

(749) 0x43eac1 VMOVAPD	%XMM16,%XMM10

(749) 0x43eac7 VMOVSD	0xb44d9(%RIP),%XMM7

(749) 0x43eacf VFMADD213SD	%XMM8,%XMM7,%XMM10

(749) 0x43ead4 VMOVAPD	%XMM16,%XMM11

(749) 0x43eada VFNMADD213SD	%XMM3,%XMM7,%XMM11

(749) 0x43eadf MOV	0x8(%R12),%R9

(749) 0x43eae4 MOV	0x28(%RSP),%R12

(749) 0x43eae9 DEC	%R12

(749) 0x43eaec MOV	%EDX,%ESI

(749) 0x43eaee SAR	$0x1f,%ESI

(749) 0x43eaf1 ANDN	%EDX,%ESI,%EDX

(749) 0x43eaf6 CMP	%RDX,%R12

(749) 0x43eaf9 CMOVGE	%RDX,%R12

(749) 0x43eafd VMULSD	%XMM1,%XMM14,%XMM3

(749) 0x43eb01 MOV	0x40(%RSP),%R8

(749) 0x43eb06 MOV	%R8,%RDX

(749) 0x43eb09 IMUL	%R12,%RDX

(749) 0x43eb0d MOV	0x48(%RSP),%R14

(749) 0x43eb12 DEC	%R14

(749) 0x43eb15 MOV	%ECX,%ESI

(749) 0x43eb17 SAR	$0x1f,%ESI

(749) 0x43eb1a ANDN	%ECX,%ESI,%ECX

(749) 0x43eb1f CMP	%RCX,%R14

(749) 0x43eb22 CMOVGE	%RCX,%R14

(749) 0x43eb26 MOV	0x68(%RSP),%RSI

(749) 0x43eb2b MOV	%RSI,%RCX

(749) 0x43eb2e IMUL	%R14,%RCX

(749) 0x43eb32 ADD	%RDX,%RCX

(749) 0x43eb35 MOV	0x8(%RSP),%R15

(749) 0x43eb3a DEC	%R15

(749) 0x43eb3d MOV	%EAX,%EDX

(749) 0x43eb3f SAR	$0x1f,%EDX

(749) 0x43eb42 ANDN	%EAX,%EDX,%EAX

(749) 0x43eb47 CMP	%RAX,%R15

(749) 0x43eb4a CMOVGE	%RAX,%R15

(749) 0x43eb4e MOV	%R11,%RAX

(749) 0x43eb51 IMUL	%R15,%RAX

(749) 0x43eb55 LEA	(%RCX,%RAX,1),%RDX

(749) 0x43eb59 LEA	(%R11,%RAX,1),%R10

(749) 0x43eb5d ADD	%RCX,%R10

(749) 0x43eb60 MOV	%R10,0x180(%RSP)

(749) 0x43eb68 LEA	(%RCX,%R11,2),%R10

(749) 0x43eb6c ADD	%RAX,%R10

(749) 0x43eb6f MOV	%R10,0x178(%RSP)

(749) 0x43eb77 LEA	(%R11,%R11,2),%R10

(749) 0x43eb7b ADD	%R10,%RAX

(749) 0x43eb7e ADD	%RCX,%RAX

(749) 0x43eb81 MOV	%RAX,0x188(%RSP)

(749) 0x43eb89 VBROADCASTSD	%XMM0,%ZMM0

(749) 0x43eb8f VBROADCASTSD	%XMM13,%ZMM1

(749) 0x43eb95 VBROADCASTSD	%XMM2,%ZMM2

(749) 0x43eb9b VBROADCASTSD	%XMM3,%ZMM3

(749) 0x43eba1 VBROADCASTSD	%XMM4,%ZMM4

(749) 0x43eba7 VBROADCASTSD	%XMM5,%ZMM5

(749) 0x43ebad VBROADCASTSD	%XMM6,%ZMM6

(749) 0x43ebb3 VBROADCASTSD	%XMM12,%ZMM7

(749) 0x43ebb9 VBROADCASTSD	%XMM16,%ZMM8

(749) 0x43ebbf VBROADCASTSD	%XMM9,%ZMM9

(749) 0x43ebc5 VBROADCASTSD	%XMM10,%ZMM10

(749) 0x43ebcb VBROADCASTSD	%XMM11,%ZMM11

(749) 0x43ebd1 LEA	(%RDX,%R11,1),%RAX

(749) 0x43ebd5 MOV	%RAX,0x168(%RSP)

(749) 0x43ebdd LEA	(%RDX,%R11,2),%RAX

(749) 0x43ebe1 MOV	%RAX,0x160(%RSP)

(749) 0x43ebe9 LEA	(,%R8,8),%RAX

(749) 0x43ebf1 MOV	%RAX,0x490(%RSP)

(749) 0x43ebf9 IMUL	%RAX,%R12

(749) 0x43ebfd LEA	(,%RSI,8),%RAX

(749) 0x43ec05 MOV	%RAX,0x140(%RSP)

(749) 0x43ec0d IMUL	%RAX,%R14

(749) 0x43ec11 ADD	%R12,%R14

(749) 0x43ec14 SAL	$0x3,%R11

(749) 0x43ec18 LEA	0x3(%R15),%RCX

(749) 0x43ec1c IMUL	%R11,%RCX

(749) 0x43ec20 LEA	0x2(%R15),%RSI

(749) 0x43ec24 IMUL	%R11,%RSI

(749) 0x43ec28 LEA	0x1(%R15),%R8

(749) 0x43ec2c IMUL	%R11,%R8

(749) 0x43ec30 IMUL	%R15,%R11

(749) 0x43ec34 LEA	(,%RBP,2),%RAX

(749) 0x43ec3c MOV	%RAX,0x20(%RSP)

(749) 0x43ec41 MOV	%RDX,0x38(%RSP)

(749) 0x43ec46 ADD	%RDX,%R10

(749) 0x43ec49 MOV	%R10,0x170(%RSP)

(749) 0x43ec51 ADD	%R14,%RCX

(749) 0x43ec54 ADD	%R14,%RSI

(749) 0x43ec57 ADD	%R14,%R8

(749) 0x43ec5a ADD	%R9,%R11

(749) 0x43ec5d ADD	%R14,%R11

(749) 0x43ec60 MOV	%RCX,%R14

(749) 0x43ec63 MOV	%RBP,%RCX

(749) 0x43ec66 SAL	$0x4,%RCX

(749) 0x43ec6a ADD	%R9,%R14

(749) 0x43ec6d ADD	%R9,%RSI

(749) 0x43ec70 MOV	%R9,0xc0(%RSP)

(749) 0x43ec78 ADD	%R9,%R8

(749) 0x43ec7b MOV	%RSI,%R9

(749) 0x43ec7e LEA	(,%RBP,2),%RAX

(749) 0x43ec86 ADD	%RBP,%RAX

(749) 0x43ec89 MOV	%RAX,0x80(%RSP)

(749) 0x43ec91 LEA	(,%RBP,4),%RAX

(749) 0x43ec99 MOV	%RAX,0x18(%RSP)

(749) 0x43ec9e LEA	(%RBP,%RBP,4),%RAX

(749) 0x43eca3 MOV	%RAX,0x10(%RSP)

(749) 0x43eca8 MOV	%RCX,0x138(%RSP)

(749) 0x43ecb0 MOV	(%RSP),%RAX

(749) 0x43ecb4 ADD	%RAX,%RCX

(749) 0x43ecb7 LEA	(,%RBP,8),%RSI

(749) 0x43ecbf LEA	(%RAX,%RBP,8),%RAX

(749) 0x43ecc3 MOV	0x70(%RSP),%R12

(749) 0x43ecc8 VMOVUPD	0x450(%RSP),%ZMM12

(749) 0x43ecd3 VMOVUPD	0x410(%RSP),%ZMM13

(749) 0x43ecde VMOVUPD	0x3d0(%RSP),%ZMM14

(749) 0x43ece9 MOV	%RBP,%R15

(749) 0x43ecec XOR	%EDX,%EDX

(749) 0x43ecee JMP	43ed32

  (751) 0x43ecf0 LEA	0x1(%RBP),%RDX

  (751) 0x43ecf4 MOV	0x140(%RSP),%R8

  (751) 0x43ecfc MOV	0x158(%RSP),%R14

  (751) 0x43ed04 ADD	%R8,%R14

  (751) 0x43ed07 MOV	0x150(%RSP),%R9

  (751) 0x43ed0f ADD	%R8,%R9

  (751) 0x43ed12 MOV	0x148(%RSP),%R10

  (751) 0x43ed1a ADD	%R8,%R10

  (751) 0x43ed1d MOV	0x30(%RSP),%R11

  (751) 0x43ed22 ADD	%R8,%R11

  (751) 0x43ed25 MOV	%R10,%R8

  (751) 0x43ed28 CMP	$0x3,%RBP

  (751) 0x43ed2c JE	43f370

  (751) 0x43ed32 MOV	%RDX,0x4d0(%RSP)

  (751) 0x43ed3a VMOVSD	0x1b0(%RSP,%RDX,8),%XMM15

  (751) 0x43ed43 VMOVSD	%XMM15,0x310(%RSP)

  (751) 0x43ed4c VMOVSD	0x1f0(%RSP,%RDX,8),%XMM15

  (751) 0x43ed55 VMOVSD	%XMM15,0x2d0(%RSP)

  (751) 0x43ed5e VMOVSD	0x270(%RSP,%RDX,8),%XMM15

  (751) 0x43ed67 VMOVSD	%XMM15,0x290(%RSP)

  (751) 0x43ed70 MOV	0x68(%RSP),%R10

  (751) 0x43ed75 IMUL	%RDX,%R10

  (751) 0x43ed79 MOV	%R10,0x90(%RSP)

  (751) 0x43ed81 MOV	%R11,0x30(%RSP)

  (751) 0x43ed86 MOV	%R8,0x148(%RSP)

  (751) 0x43ed8e MOV	%R9,0x150(%RSP)

  (751) 0x43ed96 MOV	%R14,0x158(%RSP)

  (751) 0x43ed9e XOR	%EDX,%EDX

  (751) 0x43eda0 JMP	43f0ae

0x43eda5 NOPW	%CS:(%RAX,%RAX,1)

    (752) 0x43edb0 MOV	0x40(%RSP),%R10

    (752) 0x43edb5 IMUL	%RDX,%R10

    (752) 0x43edb9 ADD	0x90(%RSP),%R10

    (752) 0x43edc1 VBROADCASTSD	%XMM17,%ZMM20

    (752) 0x43edc7 VBROADCASTSD	%XMM19,%ZMM19

    (752) 0x43edcd VBROADCASTSD	%XMM16,%ZMM17

    (752) 0x43edd3 VBROADCASTSD	%XMM18,%ZMM18

    (752) 0x43edd9 VBROADCASTSD	%XMM21,%ZMM16

    (752) 0x43eddf VBROADCASTSD	%XMM15,%ZMM15

    (752) 0x43ede5 MOV	0x170(%RSP),%RDX

    (752) 0x43eded MOV	%RDX,0x28(%RSP)

    (752) 0x43edf2 MOV	0x160(%RSP),%RDX

    (752) 0x43edfa MOV	0x168(%RSP),%RDI

    (752) 0x43ee02 XOR	%EBP,%EBP

    (752) 0x43ee04 MOV	%R15,0x8(%RSP)

    (752) 0x43ee09 VPBROADCASTQ	%RBP,%ZMM21

    (752) 0x43ee0f VMOVDQU64	0x510(%RSP),%ZMM22

    (752) 0x43ee1a VPSUBQ	%ZMM21,%ZMM22,%ZMM21

    (752) 0x43ee20 VPCMPNLEUQ	0xb6315(%RIP),%ZMM21,%K1

    (752) 0x43ee2b ADD	%RBP,%R10

    (752) 0x43ee2e MOV	0x38(%RSP),%R15

    (752) 0x43ee33 LEA	(%R15,%R10,1),%R12

    (752) 0x43ee37 MOV	0xc0(%RSP),%R15

    (752) 0x43ee3f VMOVUPD	(%R15,%R12,8),%ZMM21{%K1}{z}

    (752) 0x43ee46 MOV	0x70(%RSP),%R12

    (752) 0x43ee4b ADD	%R10,%RDI

    (752) 0x43ee4e VMOVUPD	(%R15,%RDI,8),%ZMM22{%K1}{z}

    (752) 0x43ee55 VMOVUPD	0x790(%RSP),%ZMM24

    (752) 0x43ee60 VMOVAPD	%ZMM21,%ZMM24{%K1}

    (752) 0x43ee66 VMOVUPD	0x7d0(%RSP),%ZMM23

    (752) 0x43ee71 VMOVAPD	%ZMM22,%ZMM23{%K1}

    (752) 0x43ee77 ADD	%R10,%RDX

    (752) 0x43ee7a VMOVUPD	(%R15,%RDX,8),%ZMM21{%K1}{z}

    (752) 0x43ee81 VMOVAPD	%ZMM21,%ZMM14{%K1}

    (752) 0x43ee87 ADD	0x28(%RSP),%R10

    (752) 0x43ee8c VMOVUPD	(%R15,%R10,8),%ZMM21{%K1}{z}

    (752) 0x43ee93 MOV	0x8(%RSP),%R15

    (752) 0x43ee98 VMOVAPD	%ZMM21,%ZMM13{%K1}

    (752) 0x43ee9e VMULPD	%ZMM4,%ZMM24,%ZMM21

    (752) 0x43eea4 VMULPD	%ZMM5,%ZMM23,%ZMM22

    (752) 0x43eeaa VFMADD231PD	%ZMM7,%ZMM13,%ZMM22

    (752) 0x43eeb0 VFMADD231PD	%ZMM6,%ZMM14,%ZMM21

    (752) 0x43eeb6 VFMADD231PD	%ZMM22,%ZMM8,%ZMM21

    (752) 0x43eebc VMOVUPD	(%R13,%RBP,8),%ZMM22{%K1}{z}

    (752) 0x43eec4 VMOVAPD	%ZMM22,%ZMM12{%K1}

    (752) 0x43eeca VMULPD	%ZMM0,%ZMM24,%ZMM22

    (752) 0x43eed0 VFMADD231PD	%ZMM1,%ZMM23,%ZMM22

    (752) 0x43eed6 VFMADD231PD	%ZMM2,%ZMM14,%ZMM22

    (752) 0x43eedc VFMADD231PD	%ZMM13,%ZMM3,%ZMM22

    (752) 0x43eee2 VFMADD213PD	%ZMM12,%ZMM22,%ZMM20

    (752) 0x43eee8 VMOVUPD	%ZMM20,(%R13,%RBP,8){%K1}

    (752) 0x43eef0 MOV	%R15,%RDX

    (752) 0x43eef3 ADD	%RBP,%RDX

    (752) 0x43eef6 VMOVUPD	(%R13,%RDX,8),%ZMM20{%K1}{z}

    (752) 0x43eefe VMOVAPD	%ZMM20,%ZMM31{%K1}

    (752) 0x43ef04 VFMADD213PD	%ZMM31,%ZMM22,%ZMM19

    (752) 0x43ef0a VMOVUPD	%ZMM19,(%R13,%RDX,8){%K1}

    (752) 0x43ef12 MOV	0x20(%RSP),%RDI

    (752) 0x43ef17 ADD	%RBP,%RDI

    (752) 0x43ef1a VMOVUPD	(%R13,%RDI,8),%ZMM19{%K1}{z}

    (752) 0x43ef22 VMOVAPD	%ZMM19,%ZMM30{%K1}

    (752) 0x43ef28 VMOVAPD	%ZMM17,%ZMM19

    (752) 0x43ef2e VFMADD213PD	%ZMM30,%ZMM21,%ZMM19

    (752) 0x43ef34 VMOVUPD	%ZMM19,(%R13,%RDI,8){%K1}

    (752) 0x43ef3c MOV	0x80(%RSP),%R10

    (752) 0x43ef44 LEA	(%R10,%RBP,1),%R10

    (752) 0x43ef48 VMOVUPD	(%R13,%R10,8),%ZMM19{%K1}{z}

    (752) 0x43ef50 VMOVUPD	0x810(%RSP),%ZMM20

    (752) 0x43ef5b VMOVAPD	%ZMM19,%ZMM20{%K1}

    (752) 0x43ef61 VMOVUPD	%ZMM20,0x810(%RSP)

    (752) 0x43ef6c VFMADD213PD	%ZMM20,%ZMM22,%ZMM18

    (752) 0x43ef72 VMOVUPD	%ZMM18,(%R13,%R10,8){%K1}

    (752) 0x43ef7a MOV	0x18(%RSP),%R10

    (752) 0x43ef7f LEA	(%R10,%RBP,1),%R10

    (752) 0x43ef83 VMOVUPD	(%R13,%R10,8),%ZMM18{%K1}{z}

    (752) 0x43ef8b VMOVUPD	0x850(%RSP),%ZMM19

    (752) 0x43ef96 VMOVAPD	%ZMM18,%ZMM19{%K1}

    (752) 0x43ef9c VMOVAPD	%ZMM16,%ZMM18

    (752) 0x43efa2 VMOVUPD	%ZMM19,0x850(%RSP)

    (752) 0x43efad VFMADD213PD	%ZMM19,%ZMM21,%ZMM18

    (752) 0x43efb3 VMOVUPD	%ZMM18,(%R13,%R10,8){%K1}

    (752) 0x43efbb MOV	0x10(%RSP),%R10

    (752) 0x43efc0 LEA	(%R10,%RBP,1),%R10

    (752) 0x43efc4 VMOVUPD	(%R13,%R10,8),%ZMM18{%K1}{z}

    (752) 0x43efcc VMOVAPD	%ZMM18,%ZMM27{%K1}

    (752) 0x43efd2 VMOVUPD	%ZMM24,0x790(%RSP)

    (752) 0x43efdd VMULPD	%ZMM9,%ZMM24,%ZMM18

    (752) 0x43efe3 VMOVUPD	%ZMM23,0x7d0(%RSP)

    (752) 0x43efee VFMADD231PD	%ZMM10,%ZMM23,%ZMM18

    (752) 0x43eff4 VFMADD231PD	%ZMM11,%ZMM14,%ZMM18

    (752) 0x43effa VFMADD231PD	%ZMM8,%ZMM13,%ZMM18

    (752) 0x43f000 VFMADD213PD	%ZMM27,%ZMM15,%ZMM18

    (752) 0x43f006 VMOVUPD	%ZMM18,(%R13,%R10,8){%K1}

    (752) 0x43f00e MOV	(%RSP),%R10

    (752) 0x43f012 VMOVUPD	(%R10,%RBP,8),%ZMM18{%K1}{z}

    (752) 0x43f019 VMOVAPD	%ZMM18,%ZMM28{%K1}

    (752) 0x43f01f VFMADD213PD	%ZMM28,%ZMM22,%ZMM17

    (752) 0x43f025 VMOVUPD	%ZMM17,(%R10,%RBP,8){%K1}

    (752) 0x43f02c VMOVUPD	(%R10,%RDX,8),%ZMM17{%K1}{z}

    (752) 0x43f033 VMOVAPD	%ZMM17,%ZMM25{%K1}

    (752) 0x43f039 VFMADD213PD	%ZMM25,%ZMM22,%ZMM16

    (752) 0x43f03f VMOVUPD	%ZMM16,(%R10,%RDX,8){%K1}

    (752) 0x43f046 VMOVUPD	(%R10,%RDI,8),%ZMM16{%K1}{z}

    (752) 0x43f04d VMOVAPD	%ZMM16,%ZMM26{%K1}

    (752) 0x43f053 VFMADD213PD	%ZMM26,%ZMM15,%ZMM21

    (752) 0x43f059 VMOVUPD	%ZMM21,(%R10,%RDI,8){%K1}

    (752) 0x43f060 VMOVUPD	(%RBX,%RBP,8),%ZMM16{%K1}{z}

    (752) 0x43f067 VMOVAPD	%ZMM16,%ZMM29{%K1}

    (752) 0x43f06d VFMADD213PD	%ZMM29,%ZMM15,%ZMM22

    (752) 0x43f073 VMOVUPD	%ZMM22,(%RBX,%RBP,8){%K1}

    (752) 0x43f07a MOV	0x48(%RSP),%R10

    (752) 0x43f07f LEA	0x1(%R10),%RDX

    (752) 0x43f083 MOV	0x490(%RSP),%RDI

    (752) 0x43f08b ADD	%RDI,%R14

    (752) 0x43f08e ADD	%RDI,%R9

    (752) 0x43f091 ADD	%RDI,%R8

    (752) 0x43f094 ADD	%RDI,%R11

    (752) 0x43f097 CMP	$0x3,%R10

    (752) 0x43f09b MOV	0x78(%RSP),%RDI

    (752) 0x43f0a0 MOV	0x4d0(%RSP),%RBP

    (752) 0x43f0a8 JE	43ecf0

    (752) 0x43f0ae TEST	%R12D,%R12D

    (752) 0x43f0b1 MOV	%RDX,0x48(%RSP)

    (752) 0x43f0b6 JLE	43f07a

    (752) 0x43f0b8 VMOVSD	0x250(%RSP,%RDX,8),%XMM15

    (752) 0x43f0c1 VMULSD	0x310(%RSP),%XMM15,%XMM17

    (752) 0x43f0c9 VMOVSD	0x2d0(%RSP),%XMM19

    (752) 0x43f0d1 VMULSD	%XMM19,%XMM15,%XMM16

    (752) 0x43f0d7 VMOVSD	0x290(%RSP),%XMM20

    (752) 0x43f0df VMULSD	%XMM20,%XMM15,%XMM15

    (752) 0x43f0e5 VMOVSD	0x1d0(%RSP,%RDX,8),%XMM18

    (752) 0x43f0ed VMULSD	%XMM19,%XMM18,%XMM19

    (752) 0x43f0f3 VMULSD	%XMM20,%XMM18,%XMM21

    (752) 0x43f0f9 VMULSD	0x190(%RSP,%RDX,8),%XMM20,%XMM18

    (752) 0x43f101 TEST	%RDI,%RDI

    (752) 0x43f104 JE	43edb0

    (752) 0x43f10a MOV	%R15,0x8(%RSP)

    (752) 0x43f10f VMOVUPD	%ZMM14,0x3d0(%RSP)

    (752) 0x43f11a VMOVUPD	%ZMM13,0x410(%RSP)

    (752) 0x43f125 VMOVUPD	%ZMM12,0x450(%RSP)

    (752) 0x43f130 VMOVUPD	%ZMM31,0x350(%RSP)

    (752) 0x43f13b VMOVUPD	%ZMM30,0x390(%RSP)

    (752) 0x43f146 VMOVAPD	%ZMM27,%ZMM12

    (752) 0x43f14c VMOVAPD	%ZMM25,%ZMM30

    (752) 0x43f152 VMOVAPD	%ZMM26,%ZMM31

    (752) 0x43f158 MOV	0x40(%RSP),%R10

    (752) 0x43f15d IMUL	%RDX,%R10

    (752) 0x43f161 ADD	0x90(%RSP),%R10

    (752) 0x43f169 VBROADCASTSD	%XMM17,%ZMM20

    (752) 0x43f16f VBROADCASTSD	%XMM19,%ZMM19

    (752) 0x43f175 VBROADCASTSD	%XMM16,%ZMM17

    (752) 0x43f17b VBROADCASTSD	%XMM18,%ZMM18

    (752) 0x43f181 VBROADCASTSD	%XMM21,%ZMM16

    (752) 0x43f187 VBROADCASTSD	%XMM15,%ZMM15

    (752) 0x43f18d XOR	%R15D,%R15D

    (752) 0x43f190 MOV	(%RSP),%RBP

    (752) 0x43f194 NOPW	%CS:(%RAX,%RAX,1)

      (753) 0x43f1a0 VMOVUPD	(%R11,%R15,8),%ZMM21

      (753) 0x43f1a7 VMOVUPD	(%R8,%R15,8),%ZMM22

      (753) 0x43f1ae VMOVUPD	(%R9,%R15,8),%ZMM23

      (753) 0x43f1b5 VMOVUPD	(%R14,%R15,8),%ZMM24

      (753) 0x43f1bc VMULPD	%ZMM0,%ZMM21,%ZMM25

      (753) 0x43f1c2 VFMADD231PD	%ZMM1,%ZMM22,%ZMM25

      (753) 0x43f1c8 VFMADD231PD	%ZMM2,%ZMM23,%ZMM25

      (753) 0x43f1ce VFMADD231PD	%ZMM24,%ZMM3,%ZMM25

      (753) 0x43f1d4 VMULPD	%ZMM4,%ZMM21,%ZMM26

      (753) 0x43f1da VMULPD	%ZMM5,%ZMM22,%ZMM27

      (753) 0x43f1e0 VFMADD231PD	%ZMM7,%ZMM24,%ZMM27

      (753) 0x43f1e6 VFMADD231PD	%ZMM6,%ZMM23,%ZMM26

      (753) 0x43f1ec VFMADD231PD	%ZMM27,%ZMM8,%ZMM26

      (753) 0x43f1f2 VMULPD	%ZMM9,%ZMM21,%ZMM21

      (753) 0x43f1f8 VFMADD231PD	%ZMM22,%ZMM10,%ZMM21

      (753) 0x43f1fe VFMADD231PD	%ZMM23,%ZMM11,%ZMM21

      (753) 0x43f204 VFMADD231PD	%ZMM24,%ZMM8,%ZMM21

      (753) 0x43f20a LEA	(%R13,%R15,8),%RDX

      (753) 0x43f20f VMOVUPD	(%R13,%R15,8),%ZMM22

      (753) 0x43f217 VFMADD231PD	%ZMM25,%ZMM20,%ZMM22

      (753) 0x43f21d VMOVUPD	%ZMM22,(%R13,%R15,8)

      (753) 0x43f225 VMOVUPD	(%RSI,%RDX,1),%ZMM22

      (753) 0x43f22c VFMADD231PD	%ZMM25,%ZMM19,%ZMM22

      (753) 0x43f232 VMOVUPD	%ZMM22,(%RSI,%RDX,1)

      (753) 0x43f239 LEA	(%RDX,%RSI,1),%RDX

      (753) 0x43f23d VMOVUPD	(%RSI,%RDX,1),%ZMM22

      (753) 0x43f244 VFMADD231PD	%ZMM17,%ZMM26,%ZMM22

      (753) 0x43f24a VMOVUPD	%ZMM22,(%RSI,%RDX,1)

      (753) 0x43f251 LEA	(%RDX,%RSI,1),%RDX

      (753) 0x43f255 VMOVUPD	(%RSI,%RDX,1),%ZMM22

      (753) 0x43f25c VFMADD231PD	%ZMM25,%ZMM18,%ZMM22

      (753) 0x43f262 VMOVUPD	%ZMM22,(%RSI,%RDX,1)

      (753) 0x43f269 LEA	(%RDX,%RSI,1),%RDX

      (753) 0x43f26d VMOVUPD	(%RSI,%RDX,1),%ZMM22

      (753) 0x43f274 VFMADD231PD	%ZMM16,%ZMM26,%ZMM22

      (753) 0x43f27a VMOVUPD	%ZMM22,(%RSI,%RDX,1)

      (753) 0x43f281 LEA	(%RDX,%RSI,1),%RDX

      (753) 0x43f285 VFMADD213PD	(%RSI,%RDX,1),%ZMM15,%ZMM21

      (753) 0x43f28c VMOVUPD	%ZMM21,(%RSI,%RDX,1)

      (753) 0x43f293 VMOVUPD	(%RBP,%R15,8),%ZMM21

      (753) 0x43f29b VFMADD231PD	%ZMM17,%ZMM25,%ZMM21

      (753) 0x43f2a1 VMOVUPD	%ZMM21,(%RBP,%R15,8)

      (753) 0x43f2a9 VMOVUPD	(%RAX,%R15,8),%ZMM21

      (753) 0x43f2b0 VFMADD231PD	%ZMM16,%ZMM25,%ZMM21

      (753) 0x43f2b6 VMOVUPD	%ZMM21,(%RAX,%R15,8)

      (753) 0x43f2bd VFMADD213PD	(%RCX,%R15,8),%ZMM15,%ZMM26

      (753) 0x43f2c4 VMOVUPD	%ZMM26,(%RCX,%R15,8)

      (753) 0x43f2cb VFMADD213PD	(%RBX,%R15,8),%ZMM15,%ZMM25

      (753) 0x43f2d2 VMOVUPD	%ZMM25,(%RBX,%R15,8)

      (753) 0x43f2d9 ADD	$0x8,%R15

      (753) 0x43f2dd CMP	%RDI,%R15

      (753) 0x43f2e0 JL	43f1a0

    (752) 0x43f2e6 MOV	0x188(%RSP),%RDX

    (752) 0x43f2ee MOV	%RDX,0x28(%RSP)

    (752) 0x43f2f3 MOV	0x178(%RSP),%RDX

    (752) 0x43f2fb MOV	%RDI,%R15

    (752) 0x43f2fe MOV	0x180(%RSP),%RDI

    (752) 0x43f306 MOV	%R15,%RBP

    (752) 0x43f309 CMP	%R12,%R15

    (752) 0x43f30c VMOVAPD	%ZMM31,%ZMM26

    (752) 0x43f312 VMOVAPD	%ZMM30,%ZMM25

    (752) 0x43f318 VMOVAPD	%ZMM12,%ZMM27

    (752) 0x43f31e VMOVUPD	0x390(%RSP),%ZMM30

    (752) 0x43f329 VMOVUPD	0x350(%RSP),%ZMM31

    (752) 0x43f334 VMOVUPD	0x450(%RSP),%ZMM12

    (752) 0x43f33f VMOVUPD	0x410(%RSP),%ZMM13

    (752) 0x43f34a VMOVUPD	0x3d0(%RSP),%ZMM14

    (752) 0x43f355 MOV	0x8(%RSP),%R15

    (752) 0x43f35a JNE	43ee04

    (752) 0x43f360 JMP	43f07a

0x43f365 NOPW	%CS:(%RAX,%RAX,1)

(749) 0x43f370 TEST	%R12D,%R12D

(749) 0x43f373 JE	43e490

(749) 0x43f379 VMOVUPD	0x230(%RSP),%XMM7

(749) 0x43f382 VMULSD	%XMM7,%XMM7,%XMM5

(749) 0x43f386 VMOVUPD	0x240(%RSP),%XMM6

(749) 0x43f38f VMULSD	%XMM6,%XMM6,%XMM4

(749) 0x43f393 VMOVUPD	0x220(%RSP),%XMM9

(749) 0x43f39c VMULSD	%XMM9,%XMM9,%XMM3

(749) 0x43f3a1 VMULSD	%XMM7,%XMM6,%XMM2

(749) 0x43f3a5 VMULSD	%XMM7,%XMM9,%XMM1

(749) 0x43f3a9 VMULSD	%XMM6,%XMM9,%XMM0

(749) 0x43f3ad TEST	%RDI,%RDI

(749) 0x43f3b0 MOV	0x60(%RSP),%R11

(749) 0x43f3b5 VBROADCASTSD	%XMM7,%ZMM8

(749) 0x43f3bb VBROADCASTSD	%XMM6,%ZMM7

(749) 0x43f3c1 VBROADCASTSD	%XMM9,%ZMM6

(749) 0x43f3c7 VBROADCASTSD	%XMM5,%ZMM5

(749) 0x43f3cd VBROADCASTSD	%XMM4,%ZMM4

(749) 0x43f3d3 VBROADCASTSD	%XMM3,%ZMM3

(749) 0x43f3d9 VBROADCASTSD	%XMM2,%ZMM2

(749) 0x43f3df VBROADCASTSD	%XMM1,%ZMM1

(749) 0x43f3e5 VBROADCASTSD	%XMM0,%ZMM0

(749) 0x43f3eb JE	43f4e0

(749) 0x43f3f1 MOV	%R15,%RDX

(749) 0x43f3f4 SAL	$0x5,%RDX

(749) 0x43f3f8 ADD	%R13,%RDX

(749) 0x43f3fb LEA	(%R15,%R15,4),%RSI

(749) 0x43f3ff LEA	(,%RSI,8),%RSI

(749) 0x43f407 ADD	%R13,%RSI

(749) 0x43f40a MOV	%RDI,%R10

(749) 0x43f40d LEA	(%R15,%R15,2),%RDI

(749) 0x43f411 LEA	(,%RDI,8),%RDI

(749) 0x43f419 ADD	%R13,%RDI

(749) 0x43f41c MOV	0x138(%RSP),%R14

(749) 0x43f424 ADD	%R13,%R14

(749) 0x43f427 LEA	(,%R15,8),%R8

(749) 0x43f42f ADD	%R13,%R8

(749) 0x43f432 XOR	%R9D,%R9D

(749) 0x43f435 MOV	(%RSP),%RBX

(749) 0x43f439 NOPL	(%RAX)

  (750) 0x43f440 VMULPD	(%RBX,%R9,8),%ZMM8,%ZMM9

  (750) 0x43f447 VMOVUPD	%ZMM9,(%RBX,%R9,8)

  (750) 0x43f44e VMULPD	(%RAX,%R9,8),%ZMM7,%ZMM9

  (750) 0x43f455 VMOVUPD	%ZMM9,(%RAX,%R9,8)

  (750) 0x43f45c VMULPD	(%RCX,%R9,8),%ZMM6,%ZMM9

  (750) 0x43f463 VMOVUPD	%ZMM9,(%RCX,%R9,8)

  (750) 0x43f46a VMULPD	(%R13,%R9,8),%ZMM5,%ZMM9

  (750) 0x43f472 VMOVUPD	%ZMM9,(%R13,%R9,8)

  (750) 0x43f47a VMULPD	(%RDI,%R9,8),%ZMM4,%ZMM9

  (750) 0x43f481 VMOVUPD	%ZMM9,(%RDI,%R9,8)

  (750) 0x43f488 VMULPD	(%RSI,%R9,8),%ZMM3,%ZMM9

  (750) 0x43f48f VMOVUPD	%ZMM9,(%RSI,%R9,8)

  (750) 0x43f496 VMULPD	(%R8,%R9,8),%ZMM2,%ZMM9

  (750) 0x43f49d VMOVUPD	%ZMM9,(%R8,%R9,8)

  (750) 0x43f4a4 VMULPD	(%R14,%R9,8),%ZMM1,%ZMM9

  (750) 0x43f4ab VMOVUPD	%ZMM9,(%R14,%R9,8)

  (750) 0x43f4b2 VMULPD	(%RDX,%R9,8),%ZMM0,%ZMM9

  (750) 0x43f4b9 VMOVUPD	%ZMM9,(%RDX,%R9,8)

  (750) 0x43f4c0 ADD	$0x8,%R9

  (750) 0x43f4c4 CMP	%R10,%R9

  (750) 0x43f4c7 JL	43f440

(749) 0x43f4cd MOV	%R10,%RAX

(749) 0x43f4d0 CMP	%R12,%R10

(749) 0x43f4d3 MOV	%R10,%RDI

(749) 0x43f4d6 JE	43e495

(749) 0x43f4dc JMP	43f4e6

0x43f4de XCHG	%AX,%AX

(749) 0x43f4e0 XOR	%EAX,%EAX

(749) 0x43f4e2 MOV	(%RSP),%RBX

(749) 0x43f4e6 VPBROADCASTQ	%RAX,%ZMM9

(749) 0x43f4ec VMOVDQU64	0x510(%RSP),%ZMM10

(749) 0x43f4f7 VPSUBQ	%ZMM9,%ZMM10,%ZMM9

(749) 0x43f4fd VPCMPNLEUQ	0xb5c38(%RIP),%ZMM9,%K1

(749) 0x43f508 VMOVUPD	(%RBX,%RAX,8),%ZMM9{%K1}{z}

(749) 0x43f50f VMOVUPD	0x550(%RSP),%ZMM10

(749) 0x43f51a VMOVAPD	%ZMM9,%ZMM10{%K1}

(749) 0x43f520 VMOVUPD	%ZMM10,0x550(%RSP)

(749) 0x43f52b VMULPD	%ZMM8,%ZMM10,%ZMM8

(749) 0x43f531 VMOVUPD	%ZMM8,(%RBX,%RAX,8){%K1}

(749) 0x43f538 ADD	%RAX,%R15

(749) 0x43f53b VMOVUPD	(%RBX,%R15,8),%ZMM8{%K1}{z}

(749) 0x43f542 VMOVUPD	0x590(%RSP),%ZMM9

(749) 0x43f54d VMOVAPD	%ZMM8,%ZMM9{%K1}

(749) 0x43f553 VMOVUPD	%ZMM9,0x590(%RSP)

(749) 0x43f55e VMULPD	%ZMM7,%ZMM9,%ZMM7

(749) 0x43f564 VMOVUPD	%ZMM7,(%RBX,%R15,8){%K1}

(749) 0x43f56b MOV	0x20(%RSP),%RCX

(749) 0x43f570 ADD	%RAX,%RCX

(749) 0x43f573 VMOVUPD	(%RBX,%RCX,8),%ZMM7{%K1}{z}

(749) 0x43f57a VMOVUPD	0x5d0(%RSP),%ZMM8

(749) 0x43f585 VMOVAPD	%ZMM7,%ZMM8{%K1}

(749) 0x43f58b VMOVUPD	%ZMM8,0x5d0(%RSP)

(749) 0x43f596 VMULPD	%ZMM6,%ZMM8,%ZMM6

(749) 0x43f59c VMOVUPD	%ZMM6,(%RBX,%RCX,8){%K1}

(749) 0x43f5a3 VMOVUPD	(%R13,%RAX,8),%ZMM6{%K1}{z}

(749) 0x43f5ab VMOVUPD	0x610(%RSP),%ZMM7

(749) 0x43f5b6 VMOVAPD	%ZMM6,%ZMM7{%K1}

(749) 0x43f5bc VMOVUPD	%ZMM7,0x610(%RSP)

(749) 0x43f5c7 VMULPD	%ZMM7,%ZMM5,%ZMM5

(749) 0x43f5cd VMOVUPD	%ZMM5,(%R13,%RAX,8){%K1}

(749) 0x43f5d5 MOV	0x80(%RSP),%RDX

(749) 0x43f5dd ADD	%RAX,%RDX

(749) 0x43f5e0 VMOVUPD	(%R13,%RDX,8),%ZMM5{%K1}{z}

(749) 0x43f5e8 VMOVUPD	0x650(%RSP),%ZMM6

(749) 0x43f5f3 VMOVAPD	%ZMM5,%ZMM6{%K1}

(749) 0x43f5f9 VMOVUPD	%ZMM6,0x650(%RSP)

(749) 0x43f604 VMULPD	%ZMM6,%ZMM4,%ZMM4

(749) 0x43f60a VMOVUPD	%ZMM4,(%R13,%RDX,8){%K1}

(749) 0x43f612 MOV	0x10(%RSP),%RDX

(749) 0x43f617 ADD	%RAX,%RDX

(749) 0x43f61a VMOVUPD	(%R13,%RDX,8),%ZMM4{%K1}{z}

(749) 0x43f622 VMOVUPD	0x690(%RSP),%ZMM5

(749) 0x43f62d VMOVAPD	%ZMM4,%ZMM5{%K1}

(749) 0x43f633 VMOVUPD	%ZMM5,0x690(%RSP)

(749) 0x43f63e VMULPD	%ZMM5,%ZMM3,%ZMM3

(749) 0x43f644 VMOVUPD	%ZMM3,(%R13,%RDX,8){%K1}

(749) 0x43f64c VMOVUPD	(%R13,%R15,8),%ZMM3{%K1}{z}

(749) 0x43f654 VMOVUPD	0x6d0(%RSP),%ZMM4

(749) 0x43f65f VMOVAPD	%ZMM3,%ZMM4{%K1}

(749) 0x43f665 VMOVUPD	%ZMM4,0x6d0(%RSP)

(749) 0x43f670 VMULPD	%ZMM4,%ZMM2,%ZMM2

(749) 0x43f676 VMOVUPD	%ZMM2,(%R13,%R15,8){%K1}

(749) 0x43f67e VMOVUPD	(%R13,%RCX,8),%ZMM2{%K1}{z}

(749) 0x43f686 VMOVUPD	0x710(%RSP),%ZMM3

(749) 0x43f691 VMOVAPD	%ZMM2,%ZMM3{%K1}

(749) 0x43f697 VMOVUPD	%ZMM3,0x710(%RSP)

(749) 0x43f6a2 VMULPD	%ZMM3,%ZMM1,%ZMM1

(749) 0x43f6a8 VMOVUPD	%ZMM1,(%R13,%RCX,8){%K1}

(749) 0x43f6b0 MOV	0x18(%RSP),%RCX

(749) 0x43f6b5 ADD	%RAX,%RCX

(749) 0x43f6b8 VMOVUPD	(%R13,%RCX,8),%ZMM1{%K1}{z}

(749) 0x43f6c0 VMOVUPD	0x750(%RSP),%ZMM2

(749) 0x43f6cb VMOVAPD	%ZMM1,%ZMM2{%K1}

(749) 0x43f6d1 VMOVUPD	%ZMM2,0x750(%RSP)

(749) 0x43f6dc VMULPD	%ZMM2,%ZMM0,%ZMM0

(749) 0x43f6e2 VMOVUPD	%ZMM0,(%R13,%RCX,8){%K1}

(749) 0x43f6ea JMP	43e495

0x43f6ef MOV	0xf0(%RSP),%RDI

0x43f6f7 VZEROUPPER

0x43f6fa CALL	48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x43f6ff MOV	0x50(%RSP),%R13

0x43f704 MOV	0x30(%R13),%ESI

0x43f708 TEST	%ESI,%ESI

0x43f70a MOV	0xe8(%RSP),%R14

0x43f712 MOV	0xe0(%RSP),%R15

0x43f71a MOV	0xd8(%RSP),%R12

0x43f722 JLE	43f869

0x43f728 MOV	0x8(%R13),%EDX

0x43f72c MOV	0x40(%R13),%EDI

0x43f730 XOR	%EAX,%EAX

0x43f732 JMP	43f74c

0x43f734 NOPW	%CS:(%RAX,%RAX,1)

(747) 0x43f740 MOVSXD	%ESI,%RCX

(747) 0x43f743 CMP	%RCX,%RAX

(747) 0x43f746 JGE	43f869

(747) 0x43f74c MOV	%RAX,%RCX

(747) 0x43f74f MOV	%ECX,%R8D

(747) 0x43f752 IMUL	%ESI,%R8D

(747) 0x43f756 INC	%RAX

(747) 0x43f759 MOV	%EDI,%R9D

(747) 0x43f75c IMUL	%EAX,%R9D

(747) 0x43f760 CMP	%R9D,%EDX

(747) 0x43f763 CMOVL	%EDX,%R9D

(747) 0x43f767 CMP	%R9D,%R8D

(747) 0x43f76a JGE	43f740

(747) 0x43f76c MOVSXD	%R8D,%RSI

(747) 0x43f76f MOVSXD	%R8D,%RDX

(747) 0x43f772 LEA	(%RDX,%RDX,2),%R8

(747) 0x43f776 ADD	$0x2,%R8

(747) 0x43f77a LEA	(%RCX,%RCX,2),%R9

(747) 0x43f77e XOR	%R10D,%R10D

(747) 0x43f781 NOPW	%CS:(%RAX,%RAX,1)

  (748) 0x43f790 MOV	0x310(%R13),%RDX

  (748) 0x43f797 MOV	(%RDX,%R9,8),%RDX

  (748) 0x43f79b VMOVSD	(%RDX,%R10,8),%XMM0

  (748) 0x43f7a1 MOV	0x18(%R12),%RDX

  (748) 0x43f7a6 VMOVSD	%XMM0,(%RDX,%RSI,8)

  (748) 0x43f7ab MOV	0x328(%R13),%RDX

  (748) 0x43f7b2 LEA	(,%RCX,8),%RDI

  (748) 0x43f7ba LEA	(%RDI,%RDI,4),%RDI

  (748) 0x43f7be MOV	0x18(%RDX,%RDI,1),%R11

  (748) 0x43f7c3 VPBROADCASTQ	%R11,%XMM0

  (748) 0x43f7c9 VPBROADCASTQ	%R10,%XMM1

  (748) 0x43f7cf MOVSXD	0x8(%RDX,%RDI,1),%RDX

  (748) 0x43f7d4 VMOVQ	%RDX,%XMM2

  (748) 0x43f7d9 VPSLLDQ	$0x8,%XMM2,%XMM2

  (748) 0x43f7de VPADDQ	%XMM2,%XMM1,%XMM1

  (748) 0x43f7e2 VPSLLQ	$0x3,%XMM1,%XMM1

  (748) 0x43f7e7 VPADDQ	%XMM1,%XMM0,%XMM0

  (748) 0x43f7eb VMOVQ	%XMM0,%RBX

  (748) 0x43f7f0 VMOVSD	(%RBX),%XMM1

  (748) 0x43f7f4 VPEXTRQ	$0x1,%XMM0,%RBX

  (748) 0x43f7fa VMOVHPS	(%RBX),%XMM1,%XMM0

  (748) 0x43f7fe LEA	(%R10,%RDX,2),%RDX

  (748) 0x43f802 VMOVSD	(%R11,%RDX,8),%XMM1

  (748) 0x43f808 MOV	0x18(%R15),%RDX

  (748) 0x43f80c VMOVUPS	%XMM0,-0x10(%RDX,%R8,8)

  (748) 0x43f813 VMOVSD	%XMM1,(%RDX,%R8,8)

  (748) 0x43f819 MOV	0x340(%R13),%RDX

  (748) 0x43f820 MOV	0x18(%RDX,%RDI,1),%RDX

  (748) 0x43f825 VMOVSD	(%RDX,%R10,8),%XMM0

  (748) 0x43f82b MOV	0x18(%R14),%RDX

  (748) 0x43f82f VMOVSD	%XMM0,(%RDX,%RSI,8)

  (748) 0x43f834 INC	%RSI

  (748) 0x43f837 MOV	0x8(%R13),%EDX

  (748) 0x43f83b MOV	0x40(%R13),%EDI

  (748) 0x43f83f MOV	%EDI,%R11D

  (748) 0x43f842 IMUL	%EAX,%R11D

  (748) 0x43f846 CMP	%R11D,%EDX

  (748) 0x43f849 CMOVL	%EDX,%R11D

  (748) 0x43f84d MOVSXD	%R11D,%R11

  (748) 0x43f850 ADD	$0x3,%R8

  (748) 0x43f854 INC	%R10

  (748) 0x43f857 CMP	%R11,%RSI

  (748) 0x43f85a JL	43f790

(747) 0x43f860 MOV	0x30(%R13),%ESI

(747) 0x43f864 JMP	43f740

0x43f869 ADD	$0x898,%RSP

0x43f870 POP	%RBX

0x43f871 POP	%R12

0x43f873 POP	%R13

0x43f875 POP	%R14

0x43f877 POP	%R15

0x43f879 POP	%RBP

0x43f87a RET

0x43f87b MOV	%RAX,%RDI

0x43f87e CALL	40d0d0 <__clang_call_terminate>

0x43f883 NOPW	%CS:(%RAX,%RAX,1)

0x43f88d NOPL	(%RAX)

Coverage (%)	Name	Module
►79.88+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►7.49+	qmcplusplus::SPOSet::evaluate_[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►7.18+	qmcplusplus::SPOSet::evaluate_[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	main.extracted.116	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.52+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.30+	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::rat[...]	exec
○	main.extracted.109	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 6.00 cycles (2.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.50 to 8.28 cycles (1.75x speedup).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
18% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 13.63 cycles (1.06x speedup).

Workaround

Read less array elements
Write less array elements

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__clang_call_terminate: 1 occurrences►
qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 1 occurrences►
VCMPPD: 1 occurrences►
VMOVDQU64: 1 occurrences►
VPBROADCASTQ: 1 occurrences►

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 19 FP arithmetical operations:

10: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 296 bytes (37 double precision FP elements). The binary function is storing 272 bytes (34 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	109
nb uops	109
loop length	624
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	1
nb stack references	21
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.63 cycles
front end	13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	14.50	14.50	14.50	14.50	4.25	4.25	4.25	4.25	4.50	4.50
cycles	4.00	4.00	4.00	4.00	4.00	4.00	14.50	14.50	14.50	14.50	4.25	4.25	4.25	4.25	4.50	4.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.63
Dispatch	14.50
Overall L1	14.50

Vectorization ratios

INT

all	6%
load	0%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	46%
load	33%
store	42%
mul	50%
add-sub	100%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	25%
load	20%
store	18%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	14%
load	11%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	24%
load	20%
store	21%
mul	18%
add-sub	50%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

INT+FP

all	19%
load	16%
store	19%
mul	18%
add-sub	31%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

7% of peak load performance is reached (20.41 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43e2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x898,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RAX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD 0x40(%R13),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA 0x128(%R13),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %EAX,0x124(%R13)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVNE %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDDUP (%RDX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0xe8(%R14),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP 0x8(%RDX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x100(%R14),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP 0x10(%RDX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x118(%R14),%XMM3,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULPD 0xd8(%R14),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0xf0(%R14),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x108(%R14),%XMM3,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM0,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM1,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x7,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VMOVUPD 0xa0(%RSP),%YMM0{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x1,%YMM1,%YMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0xe,0xb6d00(%RIP){1to0},%YMM0,%K0{%K2}	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VROUNDPD $0x9,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
KNOTW %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSUBPD %YMM1,%YMM0,%YMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD %YMM0,0xa0(%RSP){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %R14,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 43f6ef <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x143f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2f8(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x310(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0xa0(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0xa8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0xb0(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x328(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x340(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x40(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (,%R12,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DECQ 0x58(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R12,%ZMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQU64 %ZMM0,0x510(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDDUP 0xb3bb0(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPS %XMM0,0x210(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 43e4cd <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x21d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xf0(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%R13),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xe8(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xd8(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 43f869 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x15b9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R13),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%R13),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43f74c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x149c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x898,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 40d0d0 <__clang_call_terminate>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 6.00 cycles (2.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
18% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 13.63 cycles (1.06x speedup).

Workaround

Read less array elements
Write less array elements

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__clang_call_terminate: 1 occurrences►
qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 1 occurrences►
VCMPPD: 1 occurrences►
VMOVDQU64: 1 occurrences►
VPBROADCASTQ: 1 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 19 FP arithmetical operations:

10: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 296 bytes (37 double precision FP elements). The binary function is storing 272 bytes (34 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	109
nb uops	109
loop length	624
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	1
nb stack references	21
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.63 cycles
front end	13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	14.50	14.50	14.50	14.50	4.25	4.25	4.25	4.25	4.50	4.50
cycles	4.00	4.00	4.00	4.00	4.00	4.00	14.50	14.50	14.50	14.50	4.25	4.25	4.25	4.25	4.50	4.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.63
Dispatch	14.50
Overall L1	14.50

Vectorization ratios

INT

all	6%
load	0%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	46%
load	33%
store	42%
mul	50%
add-sub	100%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	25%
load	20%
store	18%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	14%
load	11%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	24%
load	20%
store	21%
mul	18%
add-sub	50%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

INT+FP

all	19%
load	16%
store	19%
mul	18%
add-sub	31%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

7% of peak load performance is reached (20.41 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43e2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x898,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RAX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD 0x40(%R13),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA 0x128(%R13),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %EAX,0x124(%R13)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVNE %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDDUP (%RDX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0xe8(%R14),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP 0x8(%RDX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x100(%R14),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP 0x10(%RDX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x118(%R14),%XMM3,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULPD 0xd8(%R14),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0xf0(%R14),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x108(%R14),%XMM3,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM0,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM1,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x7,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VMOVUPD 0xa0(%RSP),%YMM0{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x1,%YMM1,%YMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0xe,0xb6d00(%RIP){1to0},%YMM0,%K0{%K2}	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VROUNDPD $0x9,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
KNOTW %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSUBPD %YMM1,%YMM0,%YMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD %YMM0,0xa0(%RSP){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %R14,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 43f6ef <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x143f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2f8(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x310(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0xa0(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0xa8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0xb0(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x328(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x340(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x40(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (,%R12,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DECQ 0x58(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R12,%ZMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQU64 %ZMM0,0x510(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDDUP 0xb3bb0(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPS %XMM0,0x210(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 43e4cd <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x21d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xf0(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%R13),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xe8(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xd8(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 43f869 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x15b9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%R13),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%R13),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43f74c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x149c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x898,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 40d0d0 <__clang_call_terminate>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator >...–	10.54	17.54
▼Loop 749 - - exec–	0.00	0.01
○Loop 750 - - exec	0.03	0.05
▼Loop 751 - - exec–	0.00	0.01
▼Loop 752 - - exec–	0.01	0.02
○Loop 753 - - exec	10.03	16.63
▼Loop 747 - - exec–	0.00	0.01
○Loop 748 - - exec	0.45	0.74

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