OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: :0-0	Coverage (incl. loops): 25.50% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x43db50 PUSH	%RBP

0x43db51 PUSH	%R15

0x43db53 PUSH	%R14

0x43db55 PUSH	%R13

0x43db57 PUSH	%R12

0x43db59 PUSH	%RBX

0x43db5a SUB	$0x168,%RSP

0x43db61 MOV	%RCX,0xa0(%RSP)

0x43db69 MOV	%EDX,%EBP

0x43db6b MOV	%RSI,%R12

0x43db6e MOV	%RDI,%RBX

0x43db71 MOV	0x358(%RDI),%RDI

0x43db78 MOV	%RDI,0xa8(%RSP)

0x43db80 CALL	48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x43db85 MOVSXD	%EBP,%RAX

0x43db88 LEA	(%RAX,%RAX,2),%RCX

0x43db8c SAL	$0x3,%RCX

0x43db90 ADD	0x40(%R12),%RCX

0x43db95 LEA	0x128(%R12),%RDX

0x43db9d CMP	%EAX,0x124(%R12)

0x43dba5 CMOVNE	%RCX,%RDX

0x43dba9 VMOVDDUP	(%RDX),%XMM0

0x43dbad VMULSD	0xe8(%RBX),%XMM0,%XMM1

0x43dbb5 VMOVDDUP	0x8(%RDX),%XMM2

0x43dbba VFMADD231SD	0x100(%RBX),%XMM2,%XMM1

0x43dbc3 VMOVDDUP	0x10(%RDX),%XMM3

0x43dbc8 VFMADD231SD	0x118(%RBX),%XMM3,%XMM1

0x43dbd1 VMULPD	0xd8(%RBX),%XMM0,%XMM0

0x43dbd9 VFMADD231PD	0xf0(%RBX),%XMM2,%XMM0

0x43dbe2 VFMADD231PD	0x108(%RBX),%XMM3,%XMM0

0x43dbeb VMOVUPD	%XMM0,0x60(%RSP)

0x43dbf1 VMOVSD	%XMM1,0x70(%RSP)

0x43dbf7 MOV	$0x7,%AL

0x43dbf9 KMOVD	%EAX,%K1

0x43dbfd VMOVUPD	0x60(%RSP),%YMM0{%K1}{z}

0x43dc05 VXORPD	%XMM1,%XMM1,%XMM1

0x43dc09 VCMPPD	$0x1,%YMM1,%YMM0,%K2

0x43dc10 VCMPPD	$0xe,0xb7475(%RIP){1to0},%YMM0,%K0{%K2}

0x43dc1b VROUNDPD	$0x9,%YMM0,%YMM1

0x43dc21 KNOTW	%K0,%K2

0x43dc25 VSUBPD	%YMM1,%YMM0,%YMM0{%K2}{z}

0x43dc2b VMOVUPD	%YMM0,0x60(%RSP){%K1}

0x43dc33 MOV	%RBX,0x40(%RSP)

0x43dc38 MOV	0x30(%RBX),%EAX

0x43dc3b MOV	%RAX,0x48(%RSP)

0x43dc40 TEST	%EAX,%EAX

0x43dc42 JLE	43e20b

0x43dc48 MOV	0x40(%RSP),%RAX

0x43dc4d MOV	0x2f8(%RAX),%RCX

0x43dc54 MOV	%RCX,0xd8(%RSP)

0x43dc5c MOV	0x310(%RAX),%RCX

0x43dc63 MOV	%RCX,0xd0(%RSP)

0x43dc6b VMOVSD	0x60(%RSP),%XMM0

0x43dc71 VMOVSD	%XMM0,0xc8(%RSP)

0x43dc7a VMOVSD	0x68(%RSP),%XMM0

0x43dc80 VMOVSD	%XMM0,0xc0(%RSP)

0x43dc89 VMOVSD	0x70(%RSP),%XMM0

0x43dc8f VMOVSD	%XMM0,0xb8(%RSP)

0x43dc98 MOVSXD	0x40(%RAX),%R12

0x43dc9c CMP	$0x1,%R12

0x43dca0 MOV	%R12,%RBX

0x43dca3 ADC	$0,%RBX

0x43dca7 LEA	(,%R12,8),%RBP

0x43dcaf DECQ	0x48(%RSP)

0x43dcb4 MOV	%RBX,%RAX

0x43dcb7 SHR	$0x1,%RAX

0x43dcba MOV	%RAX,0x108(%RSP)

0x43dcc2 MOV	%RBX,%R15

0x43dcc5 AND	$-0x2,%R15

0x43dcc9 XOR	%ECX,%ECX

0x43dccb VMOVSD	0xb73c5(%RIP),%XMM10

0x43dcd3 VMOVSD	0xb433d(%RIP),%XMM11

0x43dcdb VMOVDDUP	0xb4335(%RIP),%XMM0

0x43dce3 VMOVUPD	%XMM0,0x110(%RSP)

0x43dcec MOV	%RBP,0xb0(%RSP)

0x43dcf4 JMP	43dd22

0x43dcf6 NOPW	%CS:(%RAX,%RAX,1)

(743) 0x43dd00 MOV	0x100(%RSP),%RCX

(743) 0x43dd08 LEA	0x1(%RCX),%RAX

(743) 0x43dd0c CMP	0x48(%RSP),%RCX

(743) 0x43dd11 MOV	%RAX,%RCX

(743) 0x43dd14 MOV	0xb0(%RSP),%RBP

(743) 0x43dd1c JE	43e20b

(743) 0x43dd22 MOV	0xd8(%RSP),%RAX

(743) 0x43dd2a MOV	(%RAX,%RCX,8),%R14

(743) 0x43dd2e MOV	%RCX,0x100(%RSP)

(743) 0x43dd36 LEA	(%RCX,%RCX,2),%RAX

(743) 0x43dd3a MOV	0xd0(%RSP),%RCX

(743) 0x43dd42 MOV	(%RCX,%RAX,8),%R13

(743) 0x43dd46 VMOVSD	0xc8(%RSP),%XMM0

(743) 0x43dd4f VSUBSD	0x28(%R14),%XMM0,%XMM0

(743) 0x43dd55 VMOVSD	0xc0(%RSP),%XMM1

(743) 0x43dd5e VSUBSD	0x50(%R14),%XMM1,%XMM1

(743) 0x43dd64 VMOVSD	0xb8(%RSP),%XMM2

(743) 0x43dd6d VSUBSD	0x78(%R14),%XMM2,%XMM2

(743) 0x43dd73 VMULSD	0x48(%R14),%XMM0,%XMM0

(743) 0x43dd79 MOVSXD	0x38(%R14),%R9

(743) 0x43dd7d VROUNDSD	$0x9,%XMM0,%XMM0,%XMM14

(743) 0x43dd83 VSUBSD	%XMM14,%XMM0,%XMM0

(743) 0x43dd88 VMULSD	0x70(%R14),%XMM1,%XMM1

(743) 0x43dd8e MOVSXD	0x60(%R14),%RAX

(743) 0x43dd92 MOV	%RAX,0x38(%RSP)

(743) 0x43dd97 VRNDSCALESD	$0x9,%XMM1,%XMM1,%XMM16

(743) 0x43dd9e VSUBSD	%XMM16,%XMM1,%XMM1

(743) 0x43dda4 VMULSD	0x98(%R14),%XMM2,%XMM2

(743) 0x43ddad MOVSXD	0x88(%R14),%R11

(743) 0x43ddb4 VRNDSCALESD	$0x9,%XMM2,%XMM2,%XMM17

(743) 0x43ddbb VSUBSD	%XMM17,%XMM2,%XMM15

(743) 0x43ddc1 VMULSD	%XMM0,%XMM10,%XMM2

(743) 0x43ddc5 VSUBSD	%XMM2,%XMM11,%XMM3

(743) 0x43ddc9 VMULSD	%XMM0,%XMM0,%XMM4

(743) 0x43ddcd VMOVDDUP	%XMM0,%XMM5

(743) 0x43ddd1 VMOVUPD	0x110(%RSP),%XMM7

(743) 0x43ddda VBLENDPD	$0x1,%XMM3,%XMM7,%XMM3

(743) 0x43dde0 VMULPD	%XMM3,%XMM5,%XMM3

(743) 0x43dde4 VMOVUPD	0xb72f4(%RIP),%XMM8

(743) 0x43ddec VADDPD	%XMM3,%XMM8,%XMM6

(743) 0x43ddf0 VUNPCKLPD	%XMM4,%XMM5,%XMM5

(743) 0x43ddf4 VMOVUPD	0xb72f4(%RIP),%XMM9

(743) 0x43ddfc VFMADD213PD	%XMM9,%XMM6,%XMM5

(743) 0x43de01 VMOVUPD	%XMM5,0x140(%RSP)

(743) 0x43de0a VSHUFPD	$0x1,%XMM3,%XMM3,%XMM3

(743) 0x43de0f VSUBSD	%XMM3,%XMM11,%XMM3

(743) 0x43de13 VFMADD213SD	%XMM11,%XMM0,%XMM3

(743) 0x43de18 VFMADD213SD	%XMM10,%XMM0,%XMM3

(743) 0x43de1d VMOVSD	%XMM3,0x150(%RSP)

(743) 0x43de26 VMULSD	%XMM4,%XMM2,%XMM0

(743) 0x43de2a VMOVSD	%XMM0,0x158(%RSP)

(743) 0x43de33 VMULSD	%XMM1,%XMM10,%XMM0

(743) 0x43de37 VSUBSD	%XMM0,%XMM11,%XMM2

(743) 0x43de3b VMULSD	%XMM1,%XMM1,%XMM3

(743) 0x43de3f VMOVDDUP	%XMM1,%XMM4

(743) 0x43de43 VBLENDPD	$0x1,%XMM2,%XMM7,%XMM2

(743) 0x43de49 VMULPD	%XMM2,%XMM4,%XMM2

(743) 0x43de4d VADDPD	%XMM2,%XMM8,%XMM5

(743) 0x43de51 VUNPCKLPD	%XMM3,%XMM4,%XMM4

(743) 0x43de55 VFMADD213PD	%XMM9,%XMM5,%XMM4

(743) 0x43de5a VMOVUPD	%XMM4,0x120(%RSP)

(743) 0x43de63 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM2

(743) 0x43de68 VSUBSD	%XMM2,%XMM11,%XMM2

(743) 0x43de6c VFMADD213SD	%XMM11,%XMM1,%XMM2

(743) 0x43de71 VFMADD213SD	%XMM10,%XMM1,%XMM2

(743) 0x43de76 VMOVSD	%XMM2,0x130(%RSP)

(743) 0x43de7f VMULSD	%XMM3,%XMM0,%XMM0

(743) 0x43de83 VMOVSD	%XMM0,0x138(%RSP)

(743) 0x43de8c VMULSD	%XMM10,%XMM15,%XMM1

(743) 0x43de91 VSUBSD	%XMM1,%XMM11,%XMM12

(743) 0x43de95 VFMADD213SD	0xb4192(%RIP),%XMM15,%XMM12

(743) 0x43de9e VMULSD	%XMM11,%XMM15,%XMM0

(743) 0x43dea3 VADDSD	0xb71f5(%RIP),%XMM0,%XMM13

(743) 0x43deab VMULSD	%XMM15,%XMM15,%XMM2

(743) 0x43deb0 VFMADD213SD	0xb71ef(%RIP),%XMM2,%XMM13

(743) 0x43deb9 MOV	0x10(%R14),%RAX

(743) 0x43debd MOV	%RAX,0x50(%RSP)

(743) 0x43dec2 MOV	0x18(%R14),%RAX

(743) 0x43dec6 MOV	%RAX,0x58(%RSP)

(743) 0x43decb MOV	0x20(%R14),%RAX

(743) 0x43decf MOV	%RAX,0x30(%RSP)

(743) 0x43ded4 TEST	%RBP,%RBP

(743) 0x43ded7 JE	43dfa3

(743) 0x43dedd MOV	%R13,%RDI

(743) 0x43dee0 XOR	%ESI,%ESI

(743) 0x43dee2 MOV	%RBP,%RDX

(743) 0x43dee5 VMOVUPD	%XMM12,0x90(%RSP)

(743) 0x43deee VMOVUPD	%XMM13,0x80(%RSP)

(743) 0x43def7 MOV	%R9,0x28(%RSP)

(743) 0x43defc MOV	%R11,0x20(%RSP)

(743) 0x43df01 VMOVSD	%XMM14,0x18(%RSP)

(743) 0x43df07 VMOVSD	%XMM15,0x10(%RSP)

(743) 0x43df0d VMOVSD	%XMM16,0x8(%RSP)

(743) 0x43df15 VMOVSD	%XMM17,0xf8(%RSP)

(743) 0x43df1d VMOVSD	%XMM1,0xf0(%RSP)

(743) 0x43df26 VMOVSD	%XMM2,0xe8(%RSP)

(743) 0x43df2f VMOVSD	%XMM0,0xe0(%RSP)

(743) 0x43df38 VZEROUPPER

(743) 0x43df3b CALL	4e3580 <_intel_fast_memset>

(743) 0x43df40 VMOVSD	0xe0(%RSP),%XMM0

(743) 0x43df49 VMOVSD	0xe8(%RSP),%XMM2

(743) 0x43df52 VMOVSD	0xf0(%RSP),%XMM1

(743) 0x43df5b VMOVSD	0xf8(%RSP),%XMM17

(743) 0x43df63 VMOVSD	0x8(%RSP),%XMM16

(743) 0x43df6b VMOVSD	0x10(%RSP),%XMM15

(743) 0x43df71 VMOVSD	0x18(%RSP),%XMM14

(743) 0x43df77 MOV	0x20(%RSP),%R11

(743) 0x43df7c MOV	0x28(%RSP),%R9

(743) 0x43df81 VMOVUPD	0x80(%RSP),%XMM13

(743) 0x43df8a VMOVUPD	0x90(%RSP),%XMM12

(743) 0x43df93 VMOVSD	0xb407d(%RIP),%XMM11

(743) 0x43df9b VMOVSD	0xb70f5(%RIP),%XMM10

(743) 0x43dfa3 VCVTTSD2SI	%XMM14,%EDX

(743) 0x43dfa8 VCVTTSD2SI	%XMM16,%ESI

(743) 0x43dfae VCVTTSD2SI	%XMM17,%ECX

(743) 0x43dfb4 VFMADD213SD	%XMM10,%XMM15,%XMM12

(743) 0x43dfb9 VSUBSD	%XMM0,%XMM11,%XMM0

(743) 0x43dfbd VFMADD213SD	%XMM11,%XMM15,%XMM0

(743) 0x43dfc2 VFMADD213SD	%XMM10,%XMM15,%XMM0

(743) 0x43dfc7 MOV	0x8(%R14),%RAX

(743) 0x43dfcb VMULSD	%XMM2,%XMM1,%XMM1

(743) 0x43dfcf VMOVDDUP	%XMM13,%XMM2

(743) 0x43dfd4 VMOVDDUP	%XMM12,%XMM3

(743) 0x43dfd9 VMOVDDUP	%XMM0,%XMM4

(743) 0x43dfdd VMOVDDUP	%XMM1,%XMM5

(743) 0x43dfe1 MOV	0x38(%RSP),%R14

(743) 0x43dfe6 DEC	%R14

(743) 0x43dfe9 MOV	%ESI,%EDI

(743) 0x43dfeb SAR	$0x1f,%EDI

(743) 0x43dfee ANDN	%ESI,%EDI,%ESI

(743) 0x43dff3 CMP	%RSI,%R14

(743) 0x43dff6 CMOVGE	%RSI,%R14

(743) 0x43dffa MOV	0x58(%RSP),%R8

(743) 0x43dfff IMUL	%R8,%R14

(743) 0x43e003 DEC	%R9

(743) 0x43e006 MOV	%EDX,%ESI

(743) 0x43e008 SAR	$0x1f,%ESI

(743) 0x43e00b ANDN	%EDX,%ESI,%EDX

(743) 0x43e010 CMP	%RDX,%R9

(743) 0x43e013 CMOVGE	%RDX,%R9

(743) 0x43e017 MOV	0x50(%RSP),%RSI

(743) 0x43e01c IMUL	%RSI,%R9

(743) 0x43e020 DEC	%R11

(743) 0x43e023 MOV	%ECX,%EDX

(743) 0x43e025 SAR	$0x1f,%EDX

(743) 0x43e028 ANDN	%ECX,%EDX,%ECX

(743) 0x43e02d CMP	%RCX,%R11

(743) 0x43e030 CMOVGE	%RCX,%R11

(743) 0x43e034 MOV	0x30(%RSP),%RBP

(743) 0x43e039 MOV	%RBP,%RCX

(743) 0x43e03c IMUL	%R11,%RCX

(743) 0x43e040 LEA	(%R15,%RCX,1),%RDI

(743) 0x43e044 ADD	%R9,%RDI

(743) 0x43e047 LEA	(%RDI,%R14,1),%R10

(743) 0x43e04b ADD	%RBP,%RDI

(743) 0x43e04e ADD	%R14,%RDI

(743) 0x43e051 MOV	%RDI,0x38(%RSP)

(743) 0x43e056 LEA	(%R10,%RBP,2),%RDX

(743) 0x43e05a MOV	%RDX,0x90(%RSP)

(743) 0x43e062 LEA	(,%RBP,2),%RDI

(743) 0x43e06a ADD	%RBP,%RDI

(743) 0x43e06d MOV	%R10,0x80(%RSP)

(743) 0x43e075 ADD	%R10,%RDI

(743) 0x43e078 ADD	%R14,%R9

(743) 0x43e07b LEA	0x3(%R11),%RDX

(743) 0x43e07f IMUL	%RBP,%RDX

(743) 0x43e083 ADD	%R9,%RDX

(743) 0x43e086 LEA	(%RAX,%RDX,8),%R14

(743) 0x43e08a LEA	(,%RSI,8),%RDX

(743) 0x43e092 MOV	%RDX,0x8(%RSP)

(743) 0x43e097 LEA	0x2(%R11),%RDX

(743) 0x43e09b IMUL	%RBP,%RDX

(743) 0x43e09f INC	%R11

(743) 0x43e0a2 IMUL	%RBP,%R11

(743) 0x43e0a6 LEA	(,%R8,8),%R10

(743) 0x43e0ae ADD	%R9,%RDX

(743) 0x43e0b1 LEA	(%RAX,%RDX,8),%RDX

(743) 0x43e0b5 ADD	%R9,%R11

(743) 0x43e0b8 LEA	(%RAX,%R11,8),%RSI

(743) 0x43e0bc MOV	%RDX,%R11

(743) 0x43e0bf ADD	%RCX,%R9

(743) 0x43e0c2 LEA	(%RAX,%R9,8),%RBP

(743) 0x43e0c6 MOV	%RSI,%R9

(743) 0x43e0c9 XOR	%ECX,%ECX

(743) 0x43e0cb JMP	43e108

0x43e0cd NOPL	(%RAX)

  (744) 0x43e0d0 MOV	0x10(%RSP),%RSI

  (744) 0x43e0d5 LEA	0x1(%RSI),%RCX

  (744) 0x43e0d9 MOV	0x30(%RSP),%R14

  (744) 0x43e0de MOV	0x8(%RSP),%RDX

  (744) 0x43e0e3 ADD	%RDX,%R14

  (744) 0x43e0e6 MOV	0x28(%RSP),%R11

  (744) 0x43e0eb ADD	%RDX,%R11

  (744) 0x43e0ee MOV	0x20(%RSP),%R9

  (744) 0x43e0f3 ADD	%RDX,%R9

  (744) 0x43e0f6 MOV	0x18(%RSP),%RBP

  (744) 0x43e0fb ADD	%RDX,%RBP

  (744) 0x43e0fe CMP	$0x3,%RSI

  (744) 0x43e102 JE	43dd00

  (744) 0x43e108 VMOVSD	0x140(%RSP,%RCX,8),%XMM6

  (744) 0x43e111 MOV	0x50(%RSP),%R8

  (744) 0x43e116 MOV	%RCX,0x10(%RSP)

  (744) 0x43e11b IMUL	%RCX,%R8

  (744) 0x43e11f MOV	%RBP,0x18(%RSP)

  (744) 0x43e124 MOV	%R9,0x20(%RSP)

  (744) 0x43e129 MOV	%R11,0x28(%RSP)

  (744) 0x43e12e MOV	%R14,0x30(%RSP)

  (744) 0x43e133 XOR	%ECX,%ECX

  (744) 0x43e135 JMP	43e15d

0x43e137 NOPW	(%RAX,%RAX,1)

    (745) 0x43e140 LEA	0x1(%RCX),%RDX

    (745) 0x43e144 ADD	%R10,%R14

    (745) 0x43e147 ADD	%R10,%R11

    (745) 0x43e14a ADD	%R10,%R9

    (745) 0x43e14d ADD	%R10,%RBP

    (745) 0x43e150 CMP	$0x3,%RCX

    (745) 0x43e154 MOV	%RDX,%RCX

    (745) 0x43e157 JE	43e0d0

    (745) 0x43e15d TEST	%R12D,%R12D

    (745) 0x43e160 JE	43e140

    (745) 0x43e162 VMULSD	0x120(%RSP,%RCX,8),%XMM6,%XMM7

    (745) 0x43e16b CMP	$0x2,%RBX

    (745) 0x43e16f JB	43e1af

    (745) 0x43e171 VMOVDDUP	%XMM7,%XMM8

    (745) 0x43e175 MOV	0x108(%RSP),%RDX

    (745) 0x43e17d XOR	%ESI,%ESI

    (745) 0x43e17f NOP

      (746) 0x43e180 VMULPD	(%RBP,%RSI,1),%XMM3,%XMM9

      (746) 0x43e186 VFMADD231PD	(%R9,%RSI,1),%XMM2,%XMM9

      (746) 0x43e18c VFMADD231PD	(%R11,%RSI,1),%XMM4,%XMM9

      (746) 0x43e192 VFMADD231PD	(%R14,%RSI,1),%XMM5,%XMM9

      (746) 0x43e198 VFMADD213PD	(%R13,%RSI,1),%XMM8,%XMM9

      (746) 0x43e19f VMOVUPD	%XMM9,(%R13,%RSI,1)

      (746) 0x43e1a6 ADD	$0x10,%RSI

      (746) 0x43e1aa DEC	%RDX

      (746) 0x43e1ad JNE	43e180

    (745) 0x43e1af CMP	%RBX,%R15

    (745) 0x43e1b2 JAE	43e140

    (745) 0x43e1b4 MOV	0x58(%RSP),%RDX

    (745) 0x43e1b9 IMUL	%RCX,%RDX

    (745) 0x43e1bd ADD	%R8,%RDX

    (745) 0x43e1c0 MOV	0x80(%RSP),%RSI

    (745) 0x43e1c8 ADD	%RDX,%RSI

    (745) 0x43e1cb VMULSD	(%RAX,%RSI,8),%XMM12,%XMM8

    (745) 0x43e1d0 MOV	0x38(%RSP),%RSI

    (745) 0x43e1d5 ADD	%RDX,%RSI

    (745) 0x43e1d8 VFMADD231SD	(%RAX,%RSI,8),%XMM13,%XMM8

    (745) 0x43e1de MOV	0x90(%RSP),%RSI

    (745) 0x43e1e6 ADD	%RDX,%RSI

    (745) 0x43e1e9 VFMADD231SD	(%RAX,%RSI,8),%XMM0,%XMM8

    (745) 0x43e1ef ADD	%RDI,%RDX

    (745) 0x43e1f2 VFMADD231SD	(%RAX,%RDX,8),%XMM1,%XMM8

    (745) 0x43e1f8 VFMADD213SD	(%R13,%R15,8),%XMM7,%XMM8

    (745) 0x43e1ff VMOVSD	%XMM8,(%R13,%R15,8)

    (745) 0x43e206 JMP	43e140

0x43e20b MOV	0xa8(%RSP),%RDI

0x43e213 VZEROUPPER

0x43e216 CALL	48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x43e21b MOV	0x40(%RSP),%R12

0x43e220 MOV	0x30(%R12),%EAX

0x43e225 TEST	%EAX,%EAX

0x43e227 MOV	0xa0(%RSP),%R15

0x43e22f JLE	43e295

0x43e231 XOR	%EBX,%EBX

0x43e233 XOR	%R14D,%R14D

0x43e236 JMP	43e24c

0x43e238 NOPL	(%RAX,%RAX,1)

(742) 0x43e240 MOVSXD	%EAX,%RCX

(742) 0x43e243 ADD	$0x18,%RBX

(742) 0x43e247 CMP	%RCX,%R14

(742) 0x43e24a JGE	43e295

(742) 0x43e24c MOV	%R14D,%EDX

(742) 0x43e24f IMUL	%EAX,%EDX

(742) 0x43e252 INC	%R14

(742) 0x43e255 MOV	0x40(%R12),%ECX

(742) 0x43e25a IMUL	%R14D,%ECX

(742) 0x43e25e MOV	0x8(%R12),%ESI

(742) 0x43e263 CMP	%ECX,%ESI

(742) 0x43e265 CMOVL	%ESI,%ECX

(742) 0x43e268 SUB	%EDX,%ECX

(742) 0x43e26a JLE	43e240

(742) 0x43e26c MOVSXD	%EDX,%RDI

(742) 0x43e26f SAL	$0x3,%RDI

(742) 0x43e273 ADD	0x18(%R15),%RDI

(742) 0x43e277 MOV	0x310(%R12),%RAX

(742) 0x43e27f MOV	(%RAX,%RBX,1),%RSI

(742) 0x43e283 MOV	%ECX,%EDX

(742) 0x43e285 SAL	$0x3,%RDX

(742) 0x43e289 CALL	4040a0 <memmove@plt>

(742) 0x43e28e MOV	0x30(%R12),%EAX

(742) 0x43e293 JMP	43e240

0x43e295 ADD	$0x168,%RSP

0x43e29c POP	%RBX

0x43e29d POP	%R12

0x43e29f POP	%R13

0x43e2a1 POP	%R14

0x43e2a3 POP	%R15

0x43e2a5 POP	%RBP

0x43e2a6 RET

0x43e2a7 MOV	%RAX,%RDI

0x43e2aa CALL	40d0d0 <__clang_call_terminate>

0x43e2af NOP

Coverage (%)	Name	Module
►95.06+	qmcplusplus::SPOSet::evaluateD[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.83+	qmcplusplus::SPOSet::evaluateD[...]	exec
○	miniqmcreference::DiracDetermi[...]	exec
○	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 6.25 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

21% of SSE/AVX loads are used in vector version.
18% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__clang_call_terminate: 1 occurrences►
qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 1 occurrences►
VCMPPD: 1 occurrences►

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 19 FP arithmetical operations:

10: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 272 bytes (34 double precision FP elements). The binary function is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	102
nb uops	102
loop length	524
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	0
nb stack references	15
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	12.00	12.00	12.00	12.00	4.00	4.00	4.00	4.00	3.50	3.50
cycles	4.50	4.50	4.50	4.50	4.50	4.50	12.00	12.00	12.00	12.00	4.00	4.00	4.00	4.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.75
Dispatch	12.00
Overall L1	12.75

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	42%
load	29%
store	42%
mul	50%
add-sub	100%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	25%
load	21%
store	18%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	23%
load	19%
store	21%
mul	18%
add-sub	50%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

INT+FP

all	17%
load	17%
store	16%
mul	18%
add-sub	31%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 12.75 cycles. At this rate:

8% of peak load performance is reached (21.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.75 to 12.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the function is: 43db50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %EDX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EBP,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RAX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD 0x40(%R12),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA 0x128(%R12),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %EAX,0x124(%R12)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVNE %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDDUP (%RDX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0xe8(%RBX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP 0x8(%RDX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x100(%RBX),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP 0x10(%RDX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x118(%RBX),%XMM3,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULPD 0xd8(%RBX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0xf0(%RBX),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x108(%RBX),%XMM3,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM1,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x7,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VMOVUPD 0x60(%RSP),%YMM0{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x1,%YMM1,%YMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0xe,0xb7475(%RIP){1to0},%YMM0,%K0{%K2}	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VROUNDPD $0x9,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
KNOTW %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSUBPD %YMM1,%YMM0,%YMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD %YMM0,0x60(%RSP){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 43e20b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2f8(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x310(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x60(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x68(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x70(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD 0x40(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADC $0,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R12,8),%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DECQ 0x48(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x2,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD 0xb73c5(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0xb433d(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0xb4335(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RBP,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 43dd22 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x1d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xa8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xa0(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JLE 43e295 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x745>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43e24c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 40d0d0 <__clang_call_terminate>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 6.25 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

21% of SSE/AVX loads are used in vector version.
18% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__clang_call_terminate: 1 occurrences►
qmcplusplus::TimerType
::start(): 1 occurrences►
qmcplusplus::TimerType
::stop(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVD: 1 occurrences►
VCMPPD: 1 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 19 FP arithmetical operations:

10: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 272 bytes (34 double precision FP elements). The binary function is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	102
nb uops	102
loop length	524
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	0
nb stack references	15
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	12.00	12.00	12.00	12.00	4.00	4.00	4.00	4.00	3.50	3.50
cycles	4.50	4.50	4.50	4.50	4.50	4.50	12.00	12.00	12.00	12.00	4.00	4.00	4.00	4.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.75
Dispatch	12.00
Overall L1	12.75

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	42%
load	29%
store	42%
mul	50%
add-sub	100%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	25%
load	21%
store	18%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	23%
load	19%
store	21%
mul	18%
add-sub	50%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

INT+FP

all	17%
load	17%
store	16%
mul	18%
add-sub	31%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 12.75 cycles. At this rate:

8% of peak load performance is reached (21.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 43db50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %EDX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x358(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 48ac70 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EBP,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RAX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD 0x40(%R12),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA 0x128(%R12),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %EAX,0x124(%R12)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMOVNE %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDDUP (%RDX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0xe8(%RBX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP 0x8(%RDX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x100(%RBX),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVDDUP 0x10(%RDX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VFMADD231SD 0x118(%RBX),%XMM3,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULPD 0xd8(%RBX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VFMADD231PD 0xf0(%RBX),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VFMADD231PD 0x108(%RBX),%XMM3,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM1,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x7,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
VMOVUPD 0x60(%RSP),%YMM0{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x1,%YMM1,%YMM0,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0xe,0xb7475(%RIP){1to0},%YMM0,%K0{%K2}	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VROUNDPD $0x9,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
KNOTW %K0,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VSUBPD %YMM1,%YMM0,%YMM0{%K2}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD %YMM0,0x60(%RSP){%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 43e20b <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2f8(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x310(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x60(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x68(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD 0x70(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSXD 0x40(%RAX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADC $0,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R12,8),%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DECQ 0x48(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x2,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD 0xb73c5(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0xb433d(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP 0xb4335(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RBP,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 43dd22 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x1d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xa8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 48ae30 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xa0(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JLE 43e295 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x745>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43e24c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 40d0d0 <__clang_call_terminate>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	25.50	42.46
▼Loop 743 - - exec–	0.00	0.01
▼Loop 744 - - exec–	0.00	0.01
▼Loop 745 - - exec–	0.00	0.01
○Loop 746 - - exec	25.49	42.27
○Loop 742 - - exec	0.00	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code