OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: :0-0	Coverage (incl. loops): 1.11% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x421340 PUSH	%RBP

0x421341 PUSH	%R15

0x421343 PUSH	%R14

0x421345 PUSH	%R13

0x421347 PUSH	%R12

0x421349 PUSH	%RBX

0x42134a SUB	$0x188,%RSP

0x421351 MOV	0x8(%RDX),%RAX

0x421355 MOV	%RDX,0x18(%RSP)

0x42135a CMP	(%RDX),%RAX

0x42135d JE	4219c9

0x421363 MOV	%RSI,%RCX

0x421366 MOV	%RDI,%RBX

0x421369 XOR	%R14D,%R14D

0x42136c MOV	%RDI,0x8(%RSP)

0x421371 MOV	%RSI,0x10(%RSP)

0x421376 JMP	4213ea

0x421378 NOPL	(%RAX,%RAX,1)

(323) 0x421380 VXORPD	%XMM0,%XMM0,%XMM0

(323) 0x421384 VMOVUPD	0x80(%RSP),%ZMM30

(323) 0x42138c VMOVUPD	0x40(%RSP),%ZMM31

(323) 0x421394 VMOVUPD	%ZMM31,0x40(%RSP)

(323) 0x42139c VMOVUPD	%ZMM30,0x80(%RSP)

(323) 0x4213a4 VMOVSD	0x20(%RSP),%XMM1

(323) 0x4213aa VSUBSD	%XMM0,%XMM1,%XMM0

(323) 0x4213ae VZEROUPPER

(323) 0x4213b1 CALL	4d3c70 <exp>

(323) 0x4213b6 MOV	0x18(%RSP),%RCX

(323) 0x4213bb MOV	(%RCX),%RAX

(323) 0x4213be MOV	0x28(%RSP),%R14

(323) 0x4213c3 VMOVSD	%XMM0,(%RAX,%R14,8)

(323) 0x4213c9 INC	%R14

(323) 0x4213cc MOV	0x8(%RCX),%RCX

(323) 0x4213d0 SUB	%RAX,%RCX

(323) 0x4213d3 SAR	$0x3,%RCX

(323) 0x4213d7 CMP	%R14,%RCX

(323) 0x4213da MOV	0x10(%RSP),%RCX

(323) 0x4213df MOV	0x8(%RSP),%RBX

(323) 0x4213e4 JBE	4219c9

(323) 0x4213ea CMPB	$0,0x298(%RCX)

(323) 0x4213f1 JE	4219db

(323) 0x4213f7 MOVSXD	0x2a0(%RCX),%R15

(323) 0x4213fe MOV	0xd8(%RBX),%RAX

(323) 0x421405 VMOVSD	(%RAX,%R15,8),%XMM0

(323) 0x42140b VMOVSD	%XMM0,0x20(%RSP)

(323) 0x421411 MOV	0x290(%RCX),%RBP

(323) 0x421418 MOV	0x248(%RBX),%ESI

(323) 0x42141e MOV	%RCX,%RDI

(323) 0x421421 VZEROUPPER

(323) 0x421424 CALL	461f70 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>

(323) 0x421429 MOV	0xa0(%RBX),%RCX

(323) 0x421430 TEST	%RCX,%RCX

(323) 0x421433 MOV	%R14,0x28(%RSP)

(323) 0x421438 JE	421380

(323) 0x42143e MOV	0x48(%RAX),%RAX

(323) 0x421442 LEA	(%R14,%R14,4),%RDX

(323) 0x421446 MOV	0x18(%RAX,%RDX,8),%RAX

(323) 0x42144b MOV	%RAX,(%RSP)

(323) 0x42144f MOV	0x18(%RBP),%RDX

(323) 0x421453 MOV	(%RDX,%R15,4),%EDI

(323) 0x421457 IMUL	%ECX,%EDI

(323) 0x42145a MOV	0x1d0(%RBX),%RDX

(323) 0x421461 MOV	0x200(%RBX),%RAX

(323) 0x421468 MOV	%RAX,0x38(%RSP)

(323) 0x42146d MOVSXD	%EDI,%RAX

(323) 0x421470 MOV	%RAX,0x30(%RSP)

(323) 0x421475 DEC	%RCX

(323) 0x421478 VPBROADCASTD	%R15D,%ZMM1

(323) 0x42147e VXORPD	%XMM0,%XMM0,%XMM0

(323) 0x421482 XOR	%R8D,%R8D

(323) 0x421485 VMOVDQU64	0xd21f1(%RIP),%ZMM28

(323) 0x42148f VMOVDQU64	0xd21a7(%RIP),%ZMM29

(323) 0x421499 VMOVUPD	0x80(%RSP),%ZMM30

(323) 0x4214a1 VMOVUPD	0x40(%RSP),%ZMM31

(323) 0x4214a9 MOV	%R15,%RDI

(323) 0x4214ac JMP	4214cc

0x4214ae XCHG	%AX,%AX

  (324) 0x4214b0 VXORPD	%XMM21,%XMM21,%XMM21

  (324) 0x4214b6 VADDSD	%XMM0,%XMM21,%XMM0

  (324) 0x4214bc LEA	0x1(%R8),%RSI

  (324) 0x4214c0 CMP	%RCX,%R8

  (324) 0x4214c3 MOV	%RSI,%R8

  (324) 0x4214c6 JE	421394

  (324) 0x4214cc MOV	0x268(%RBP),%R9

  (324) 0x4214d3 MOV	0x18(%R9),%R9

  (324) 0x4214d7 MOV	(%R9,%R8,4),%R15

  (324) 0x4214db MOV	%R15,%R14

  (324) 0x4214de SHR	$0x20,%R14

  (324) 0x4214e2 SUB	%R15D,%R14D

  (324) 0x4214e5 TEST	%R14D,%R14D

  (324) 0x4214e8 JLE	4214b0

  (324) 0x4214ea MOV	0x30(%RSP),%RAX

  (324) 0x4214ef LEA	(%R8,%RAX,1),%R9

  (324) 0x4214f3 MOV	0x38(%RSP),%RAX

  (324) 0x4214f8 MOV	(%RAX,%R9,8),%R9

  (324) 0x4214fc VMOVSD	0x8(%R9),%XMM2

  (324) 0x421502 MOV	%R14D,%R14D

  (324) 0x421505 MOV	%R14,%R11

  (324) 0x421508 MOVSXD	%R15D,%R13

  (324) 0x42150b MOV	$-0x10,%ESI

  (324) 0x421510 AND	%RSI,%R11

  (324) 0x421513 JE	421800

  (324) 0x421519 MOV	%RDI,%RAX

  (324) 0x42151c VMOVQ	%R15,%XMM3

  (324) 0x421521 VBROADCASTSD	%XMM2,%ZMM4

  (324) 0x421527 MOV	(%RSP),%RSI

  (324) 0x42152b LEA	(%RSI,%R13,8),%R12

  (324) 0x42152f XOR	%R10D,%R10D

  (324) 0x421532 XOR	%EBX,%EBX

  (324) 0x421534 NOPW	%CS:(%RAX,%RAX,1)

    (327) 0x421540 VMOVUPD	(%R12,%RBX,8),%ZMM5

    (327) 0x421547 VMOVUPD	0x40(%R12,%RBX,8),%ZMM6

    (327) 0x42154f VMOVD	%EBX,%XMM7

    (327) 0x421553 VPADDD	%XMM3,%XMM7,%XMM7

    (327) 0x421557 VPBROADCASTD	%XMM7,%ZMM7

    (327) 0x42155d VPADDD	%ZMM29,%ZMM7,%ZMM7

    (327) 0x421563 VPCMPNEQD	%ZMM1,%ZMM7,%K0

    (327) 0x42156a VCMPPD	$0x1,%ZMM4,%ZMM5,%K1

    (327) 0x421571 VCMPPD	$0x1,%ZMM4,%ZMM6,%K2

    (327) 0x421578 KUNPCKBW	%K1,%K2,%K3

    (327) 0x42157c KANDW	%K0,%K3,%K3

    (327) 0x421580 MOVSXD	%R10D,%R10

    (327) 0x421583 KANDB	%K0,%K1,%K1

    (327) 0x421587 VCOMPRESSPD	%ZMM5,(%RDX,%R10,8){%K1}

    (327) 0x42158e LEA	(%RDX,%R10,8),%RSI

    (327) 0x421592 KSHIFTRW	$0x8,%K0,%K0

    (327) 0x421598 KANDB	%K0,%K2,%K2

    (327) 0x42159c KMOVB	%K1,%EDI

    (327) 0x4215a0 POPCNT	%EDI,%EDI

    (327) 0x4215a4 VCOMPRESSPD	%ZMM6,(%RSI,%RDI,8){%K2}

    (327) 0x4215ab KMOVW	%K3,%ESI

    (327) 0x4215af POPCNT	%ESI,%ESI

    (327) 0x4215b3 ADD	%ESI,%R10D

    (327) 0x4215b6 ADD	$0x10,%RBX

    (327) 0x4215ba CMP	%R11,%RBX

    (327) 0x4215bd JB	421540

  (324) 0x4215bf CMP	%R14,%R11

  (324) 0x4215c2 MOV	%RAX,%RDI

  (324) 0x4215c5 JNE	421806

  (324) 0x4215cb TEST	%R10D,%R10D

  (324) 0x4215ce JLE	4214b0

  (324) 0x4215d4 VMOVSD	0x238(%R9),%XMM4

  (324) 0x4215dd MOV	0x218(%R9),%R11

  (324) 0x4215e4 VMOVSD	0x18(%R9),%XMM21

  (324) 0x4215eb VMOVSD	0x20(%R9),%XMM2

  (324) 0x4215f1 VMOVSD	0x28(%R9),%XMM6

  (324) 0x4215f7 VMOVSD	0x30(%R9),%XMM5

  (324) 0x4215fd VMOVSD	0x38(%R9),%XMM13

  (324) 0x421603 VMOVSD	0x40(%R9),%XMM12

  (324) 0x421609 VMOVSD	0x48(%R9),%XMM15

  (324) 0x42160f VMOVSD	0x50(%R9),%XMM14

  (324) 0x421615 VMOVSD	0x58(%R9),%XMM7

  (324) 0x42161b VMOVSD	0x60(%R9),%XMM3

  (324) 0x421621 VMOVSD	0x68(%R9),%XMM10

  (324) 0x421627 VMOVSD	0x70(%R9),%XMM9

  (324) 0x42162d VMOVSD	0x78(%R9),%XMM16

  (324) 0x421634 VMOVSD	0x80(%R9),%XMM8

  (324) 0x42163d VMOVSD	0x88(%R9),%XMM18

  (324) 0x421644 VMOVSD	0x90(%R9),%XMM17

  (324) 0x42164b MOV	%R10D,%R10D

  (324) 0x42164e MOV	%R10,%R9

  (324) 0x421651 VPBROADCASTQ	%R10,%ZMM19

  (324) 0x421657 VPBROADCASTQ	%R11,%ZMM11

  (324) 0x42165d MOV	$-0x8,%ESI

  (324) 0x421662 VBROADCASTSD	%XMM4,%ZMM20

  (324) 0x421668 VBROADCASTSD	%XMM21,%ZMM4

  (324) 0x42166e VBROADCASTSD	%XMM2,%ZMM2

  (324) 0x421674 VBROADCASTSD	%XMM6,%ZMM6

  (324) 0x42167a VBROADCASTSD	%XMM5,%ZMM5

  (324) 0x421680 VBROADCASTSD	%XMM13,%ZMM13

  (324) 0x421686 VBROADCASTSD	%XMM12,%ZMM12

  (324) 0x42168c VBROADCASTSD	%XMM15,%ZMM15

  (324) 0x421692 VBROADCASTSD	%XMM14,%ZMM14

  (324) 0x421698 VBROADCASTSD	%XMM7,%ZMM7

  (324) 0x42169e VBROADCASTSD	%XMM3,%ZMM3

  (324) 0x4216a4 VBROADCASTSD	%XMM10,%ZMM10

  (324) 0x4216aa VBROADCASTSD	%XMM9,%ZMM9

  (324) 0x4216b0 VBROADCASTSD	%XMM16,%ZMM16

  (324) 0x4216b6 VBROADCASTSD	%XMM8,%ZMM8

  (324) 0x4216bc VBROADCASTSD	%XMM18,%ZMM18

  (324) 0x4216c2 VBROADCASTSD	%XMM17,%ZMM17

  (324) 0x4216c8 AND	%RSI,%R9

  (324) 0x4216cb JE	42184b

  (324) 0x4216d1 VXORPD	%XMM21,%XMM21,%XMM21

  (324) 0x4216d7 XOR	%R14D,%R14D

  (324) 0x4216da NOPW	(%RAX,%RAX,1)

    (325) 0x4216e0 VMULPD	(%RDX,%R14,8),%ZMM20,%ZMM22

    (325) 0x4216e7 VCVTTPD2DQ	%ZMM22,%YMM23

    (325) 0x4216ed VRNDSCALEPD	$0xb,%ZMM22,%ZMM24

    (325) 0x4216f4 VSUBPD	%ZMM24,%ZMM22,%ZMM22

    (325) 0x4216fa VXORPD	%XMM24,%XMM24,%XMM24

    (325) 0x421700 KXNORW	%K0,%K0,%K1

    (325) 0x421704 VGATHERDPD	(%R11,%YMM23,8),%ZMM24{%K1}

    (325) 0x42170b VXORPD	%XMM25,%XMM25,%XMM25

    (325) 0x421711 KXNORW	%K0,%K0,%K1

    (325) 0x421715 VGATHERDPD	0x8(%R11,%YMM23,8),%ZMM25{%K1}

    (325) 0x42171d VXORPD	%XMM26,%XMM26,%XMM26

    (325) 0x421723 KXNORW	%K0,%K0,%K1

    (325) 0x421727 VGATHERDPD	0x10(%R11,%YMM23,8),%ZMM26{%K1}

    (325) 0x42172f VXORPD	%XMM27,%XMM27,%XMM27

    (325) 0x421735 KXNORW	%K0,%K0,%K1

    (325) 0x421739 VGATHERDPD	0x18(%R11,%YMM23,8),%ZMM27{%K1}

    (325) 0x421741 VMOVAPD	%ZMM22,%ZMM23

    (325) 0x421747 VFMADD213PD	%ZMM2,%ZMM4,%ZMM23

    (325) 0x42174d VFMADD213PD	%ZMM6,%ZMM22,%ZMM23

    (325) 0x421753 VFMADD213PD	%ZMM5,%ZMM22,%ZMM23

    (325) 0x421759 VFMADD213PD	%ZMM21,%ZMM24,%ZMM23

    (325) 0x42175f VMOVAPD	%ZMM22,%ZMM21

    (325) 0x421765 VFMADD213PD	%ZMM12,%ZMM13,%ZMM21

    (325) 0x42176b VFMADD213PD	%ZMM15,%ZMM22,%ZMM21

    (325) 0x421771 VFMADD213PD	%ZMM14,%ZMM22,%ZMM21

    (325) 0x421777 VFMADD213PD	%ZMM23,%ZMM25,%ZMM21

    (325) 0x42177d VMOVAPD	%ZMM22,%ZMM23

    (325) 0x421783 VFMADD213PD	%ZMM3,%ZMM7,%ZMM23

    (325) 0x421789 VFMADD213PD	%ZMM10,%ZMM22,%ZMM23

    (325) 0x42178f VFMADD213PD	%ZMM9,%ZMM22,%ZMM23

    (325) 0x421795 VFMADD213PD	%ZMM21,%ZMM26,%ZMM23

    (325) 0x42179b VMOVAPD	%ZMM22,%ZMM21

    (325) 0x4217a1 VFMADD213PD	%ZMM8,%ZMM16,%ZMM21

    (325) 0x4217a7 VFMADD213PD	%ZMM18,%ZMM22,%ZMM21

    (325) 0x4217ad VFMADD213PD	%ZMM17,%ZMM22,%ZMM21

    (325) 0x4217b3 VFMADD213PD	%ZMM23,%ZMM27,%ZMM21

    (325) 0x4217b9 ADD	$0x8,%R14

    (325) 0x4217bd CMP	%R9,%R14

    (325) 0x4217c0 JB	4216e0

  (324) 0x4217c6 VEXTRACTF64X4	$0x1,%ZMM21,%YMM22

  (324) 0x4217cd VADDPD	%ZMM22,%ZMM21,%ZMM21

  (324) 0x4217d3 VEXTRACTF32X4	$0x1,%YMM21,%XMM22

  (324) 0x4217da VADDPD	%XMM22,%XMM21,%XMM21

  (324) 0x4217e0 VSHUFPD	$0x1,%XMM21,%XMM21,%XMM22

  (324) 0x4217e7 VADDSD	%XMM22,%XMM21,%XMM21

  (324) 0x4217ed CMP	%R10,%R9

  (324) 0x4217f0 JE	4214b6

  (324) 0x4217f6 JMP	421854

0x4217f8 NOPL	(%RAX,%RAX,1)

  (324) 0x421800 XOR	%R10D,%R10D

  (324) 0x421803 XOR	%R11D,%R11D

  (324) 0x421806 MOV	%EDI,%R12D

  (324) 0x421809 SUB	%R15D,%R12D

  (324) 0x42180c MOV	(%RSP),%RAX

  (324) 0x421810 LEA	(%RAX,%R13,8),%RBX

  (324) 0x421814 JMP	42182c

0x421816 NOPW	%CS:(%RAX,%RAX,1)

    (326) 0x421820 INC	%R11

    (326) 0x421823 CMP	%R11,%R14

    (326) 0x421826 JE	4215cb

    (326) 0x42182c VMOVSD	(%RBX,%R11,8),%XMM3

    (326) 0x421832 VUCOMISD	%XMM3,%XMM2

    (326) 0x421836 JBE	421820

    (326) 0x421838 CMP	%R11D,%R12D

    (326) 0x42183b JE	421820

    (326) 0x42183d MOVSXD	%R10D,%R10

    (326) 0x421840 VMOVSD	%XMM3,(%RDX,%R10,8)

    (326) 0x421846 INC	%R10D

    (326) 0x421849 JMP	421820

  (324) 0x42184b VXORPD	%XMM21,%XMM21,%XMM21

  (324) 0x421851 XOR	%R9D,%R9D

  (324) 0x421854 VPBROADCASTQ	%R9,%ZMM22

  (324) 0x42185a VPSUBQ	%ZMM22,%ZMM19,%ZMM19

  (324) 0x421860 VPCMPNLEUQ	%ZMM28,%ZMM19,%K1

  (324) 0x421867 VMOVUPD	(%RDX,%R9,8),%ZMM19{%K1}{z}

  (324) 0x42186e VMOVUPD	0xc0(%RSP),%ZMM22

  (324) 0x421876 VMOVAPD	%ZMM19,%ZMM22{%K1}

  (324) 0x42187c VMOVUPD	%ZMM22,0xc0(%RSP)

  (324) 0x421884 VMULPD	%ZMM22,%ZMM20,%ZMM19

  (324) 0x42188a VCVTTPD2DQ	%ZMM19,%YMM20

  (324) 0x421890 VRNDSCALEPD	$0xb,%ZMM19,%ZMM22

  (324) 0x421897 VSUBPD	%ZMM22,%ZMM19,%ZMM19

  (324) 0x42189d VPMOVSXDQ	%YMM20,%ZMM20

  (324) 0x4218a3 VPSLLQ	$0x3,%ZMM20,%ZMM20

  (324) 0x4218aa VPADDQ	%ZMM20,%ZMM11,%ZMM11

  (324) 0x4218b0 KMOVQ	%K1,%K2

  (324) 0x4218b5 VPXORD	%XMM20,%XMM20,%XMM20

  (324) 0x4218bb VGATHERQPD	(,%ZMM11,1),%ZMM20{%K2}

  (324) 0x4218c6 VMOVUPD	0x100(%RSP),%ZMM23

  (324) 0x4218ce VMOVAPD	%ZMM20,%ZMM23{%K1}

  (324) 0x4218d4 KMOVQ	%K1,%K2

  (324) 0x4218d9 VXORPD	%XMM20,%XMM20,%XMM20

  (324) 0x4218df VGATHERQPD	0x8(,%ZMM11,1),%ZMM20{%K2}

  (324) 0x4218ea VMOVUPD	0x140(%RSP),%ZMM22

  (324) 0x4218f2 VMOVAPD	%ZMM20,%ZMM22{%K1}

  (324) 0x4218f8 VFMADD231PD	%ZMM13,%ZMM19,%ZMM12

  (324) 0x4218fe VFMADD213PD	%ZMM15,%ZMM19,%ZMM12

  (324) 0x421904 VFMADD213PD	%ZMM14,%ZMM19,%ZMM12

  (324) 0x42190a VMOVUPD	%ZMM22,0x140(%RSP)

  (324) 0x421912 VMULPD	%ZMM22,%ZMM12,%ZMM12

  (324) 0x421918 KMOVQ	%K1,%K2

  (324) 0x42191d VXORPD	%XMM13,%XMM13,%XMM13

  (324) 0x421922 VGATHERQPD	0x10(,%ZMM11,1),%ZMM13{%K2}

  (324) 0x42192d VMOVAPD	%ZMM13,%ZMM31{%K1}

  (324) 0x421933 VFMADD231PD	%ZMM16,%ZMM19,%ZMM8

  (324) 0x421939 VFMADD213PD	%ZMM18,%ZMM19,%ZMM8

  (324) 0x42193f VFMADD213PD	%ZMM17,%ZMM19,%ZMM8

  (324) 0x421945 KMOVQ	%K1,%K2

  (324) 0x42194a VXORPD	%XMM13,%XMM13,%XMM13

  (324) 0x42194f VGATHERQPD	0x18(,%ZMM11,1),%ZMM13{%K2}

  (324) 0x42195a VMOVAPD	%ZMM13,%ZMM30{%K1}

  (324) 0x421960 VFMADD231PD	%ZMM4,%ZMM19,%ZMM2

  (324) 0x421966 VFMADD213PD	%ZMM6,%ZMM19,%ZMM2

  (324) 0x42196c VFMADD213PD	%ZMM5,%ZMM19,%ZMM2

  (324) 0x421972 VMOVUPD	%ZMM23,0x100(%RSP)

  (324) 0x42197a VFMADD213PD	%ZMM12,%ZMM23,%ZMM2

  (324) 0x421980 VFMADD231PD	%ZMM7,%ZMM19,%ZMM3

  (324) 0x421986 VFMADD213PD	%ZMM10,%ZMM19,%ZMM3

  (324) 0x42198c VFMADD213PD	%ZMM9,%ZMM19,%ZMM3

  (324) 0x421992 VFMADD213PD	%ZMM2,%ZMM31,%ZMM3

  (324) 0x421998 VFMADD231PD	%ZMM8,%ZMM30,%ZMM3{%K1}{z}

  (324) 0x42199e VEXTRACTF64X4	$0x1,%ZMM3,%YMM2

  (324) 0x4219a5 VADDPD	%ZMM2,%ZMM3,%ZMM2

  (324) 0x4219ab VEXTRACTF128	$0x1,%YMM2,%XMM3

  (324) 0x4219b1 VADDPD	%XMM3,%XMM2,%XMM2

  (324) 0x4219b5 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (324) 0x4219ba VADDSD	%XMM3,%XMM2,%XMM2

  (324) 0x4219be VADDSD	%XMM2,%XMM21,%XMM21

  (324) 0x4219c4 JMP	4214b6

0x4219c9 ADD	$0x188,%RSP

0x4219d0 POP	%RBX

0x4219d1 POP	%R12

0x4219d3 POP	%R13

0x4219d5 POP	%R14

0x4219d7 POP	%R15

0x4219d9 POP	%RBP

0x4219da RET

0x4219db VZEROUPPER

0x4219de CALL	421af0 <_ZSt27__throw_bad_optional_accessv>

0x4219e3 NOPW	%CS:(%RAX,%RAX,1)

0x4219ed NOPL	(%RAX)

Coverage (%)	Name	Module
►95.15+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.75+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.27 cycles (13.20x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::__throw_bad_optional_access(): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	33
nb uops	28
loop length	123
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.33	1.33	1.33	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.33	1.33	1.33	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	1.50
Overall L1	3.50

Vectorization ratios

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

1% of peak load performance is reached (4.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 1.50 cycles (2.33x speedup).

ASM code

In the binary file, the address of the function is: 421340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP (%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 4219c9 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x689>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RDI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 4213ea <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xaa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 421af0 <_ZSt27__throw_bad_optional_accessv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

std::__throw_bad_optional_access(): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	33
nb uops	28
loop length	123
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.33	1.33	1.33	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.33	1.33	1.33	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	1.50
Overall L1	3.50

Vectorization ratios

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

1% of peak load performance is reached (4.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 421340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP (%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 4219c9 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x689>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RDI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 4213ea <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xaa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 421af0 <_ZSt27__throw_bad_optional_accessv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	1.11	1.84
▼Loop 323 - - exec–	0.01	0.01
▼Loop 324 - - exec–	0.02	0.03
○Loop 327 - - exec	1.04	1.72
○Loop 325 - - exec	0.04	0.07
○Loop 326 - - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code