OV - exec - Function miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: :0-0	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x41b5a0 PUSH	%RBP

0x41b5a1 PUSH	%R15

0x41b5a3 PUSH	%R14

0x41b5a5 PUSH	%R13

0x41b5a7 PUSH	%R12

0x41b5a9 PUSH	%RBX

0x41b5aa SUB	$0x188,%RSP

0x41b5b1 MOV	%RSI,0x10(%RSP)

0x41b5b6 MOV	%RDI,0x8(%RSP)

0x41b5bb MOV	0x8(%RDX),%RAX

0x41b5bf MOV	%RDX,0x18(%RSP)

0x41b5c4 CMP	(%RDX),%RAX

0x41b5c7 JE	41bd7c

0x41b5cd XOR	%EBX,%EBX

0x41b5cf JMP	41b675

(257) 0x41b5d4 VXORPD	%XMM31,%XMM31,%XMM31

(257) 0x41b5da VMOVUPD	0x140(%RSP),%ZMM26

(257) 0x41b5e2 VMOVUPD	0x100(%RSP),%ZMM27

(257) 0x41b5ea VMOVUPD	0xc0(%RSP),%ZMM28

(257) 0x41b5f2 VMOVUPD	0x80(%RSP),%ZMM29

(257) 0x41b5fa VMOVUPD	0x40(%RSP),%ZMM30

(257) 0x41b602 NOPW	%CS:(%RAX,%RAX,1)

(257) 0x41b610 VMOVUPD	%ZMM30,0x40(%RSP)

(257) 0x41b618 VMOVUPD	%ZMM29,0x80(%RSP)

(257) 0x41b620 VMOVUPD	%ZMM28,0xc0(%RSP)

(257) 0x41b628 VMOVUPD	%ZMM27,0x100(%RSP)

(257) 0x41b630 VMOVUPD	%ZMM26,0x140(%RSP)

(257) 0x41b638 VMOVSD	0x20(%RSP),%XMM0

(257) 0x41b63e VSUBSD	%XMM31,%XMM0,%XMM0

(257) 0x41b644 VZEROUPPER

(257) 0x41b647 CALL	4d3c70 <exp>

(257) 0x41b64c MOV	0x18(%RSP),%RCX

(257) 0x41b651 MOV	(%RCX),%RAX

(257) 0x41b654 MOV	0x28(%RSP),%RBX

(257) 0x41b659 VMOVSD	%XMM0,(%RAX,%RBX,8)

(257) 0x41b65e INC	%RBX

(257) 0x41b661 MOV	0x8(%RCX),%RCX

(257) 0x41b665 SUB	%RAX,%RCX

(257) 0x41b668 SAR	$0x3,%RCX

(257) 0x41b66c CMP	%RBX,%RCX

(257) 0x41b66f JBE	41bd7c

(257) 0x41b675 MOV	0x10(%RSP),%RDI

(257) 0x41b67a MOVSXD	0x2a0(%RDI),%RAX

(257) 0x41b681 MOV	0x8(%RSP),%R15

(257) 0x41b686 MOV	0xf0(%R15),%RCX

(257) 0x41b68d VMOVSD	(%RCX,%RAX,8),%XMM0

(257) 0x41b692 VMOVSD	%XMM0,0x20(%RSP)

(257) 0x41b698 MOV	0xa8(%R15),%ESI

(257) 0x41b69f VZEROUPPER

(257) 0x41b6a2 CALL	461f70 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>

(257) 0x41b6a7 MOV	0x48(%RAX),%RAX

(257) 0x41b6ab MOV	%RBX,0x28(%RSP)

(257) 0x41b6b0 LEA	(%RBX,%RBX,4),%RCX

(257) 0x41b6b4 MOV	0x18(%RAX,%RCX,8),%RAX

(257) 0x41b6b9 MOV	%RAX,(%RSP)

(257) 0x41b6bd MOV	0x98(%R15),%EAX

(257) 0x41b6c4 TEST	%EAX,%EAX

(257) 0x41b6c6 JLE	41bc00

(257) 0x41b6cc MOV	0x1c8(%R15),%RCX

(257) 0x41b6d3 MOV	0xa0(%R15),%R14

(257) 0x41b6da MOV	0x148(%R15),%RSI

(257) 0x41b6e1 DEC	%RAX

(257) 0x41b6e4 VXORPD	%XMM31,%XMM31,%XMM31

(257) 0x41b6ea XOR	%EDI,%EDI

(257) 0x41b6ec VMOVUPD	0x140(%RSP),%ZMM26

(257) 0x41b6f4 VMOVUPD	0x100(%RSP),%ZMM27

(257) 0x41b6fc VMOVUPD	0xc0(%RSP),%ZMM28

(257) 0x41b704 VMOVUPD	0x80(%RSP),%ZMM29

(257) 0x41b70c VMOVUPD	0x40(%RSP),%ZMM30

(257) 0x41b714 JMP	41b878

  (259) 0x41b719 VXORPD	%XMM0,%XMM0,%XMM0

  (259) 0x41b71d XOR	%R8D,%R8D

  (259) 0x41b720 VPBROADCASTQ	%R8,%ZMM20

  (259) 0x41b726 VPSUBQ	%ZMM20,%ZMM18,%ZMM18

  (259) 0x41b72c VPCMPNLEUQ	0xd7c09(%RIP),%ZMM18,%K1

  (259) 0x41b737 VMOVUPD	(%RSI,%R8,8),%ZMM18{%K1}{z}

  (259) 0x41b73e VMOVAPD	%ZMM18,%ZMM30{%K1}

  (259) 0x41b744 VMULPD	%ZMM19,%ZMM30,%ZMM18

  (259) 0x41b74a VCVTTPD2DQ	%ZMM18,%YMM19

  (259) 0x41b750 VRNDSCALEPD	$0xb,%ZMM18,%ZMM20

  (259) 0x41b757 VSUBPD	%ZMM20,%ZMM18,%ZMM18

  (259) 0x41b75d VPMOVSXDQ	%YMM19,%ZMM19

  (259) 0x41b763 VPSLLQ	$0x3,%ZMM19,%ZMM19

  (259) 0x41b76a VPADDQ	%ZMM19,%ZMM10,%ZMM10

  (259) 0x41b770 VPXORD	%XMM19,%XMM19,%XMM19

  (259) 0x41b776 KMOVQ	%K1,%K2

  (259) 0x41b77b VGATHERQPD	(,%ZMM10,1),%ZMM19{%K2}

  (259) 0x41b786 VMOVAPD	%ZMM19,%ZMM29{%K1}

  (259) 0x41b78c VXORPD	%XMM19,%XMM19,%XMM19

  (259) 0x41b792 KMOVQ	%K1,%K2

  (259) 0x41b797 VGATHERQPD	0x8(,%ZMM10,1),%ZMM19{%K2}

  (259) 0x41b7a2 VMOVAPD	%ZMM19,%ZMM28{%K1}

  (259) 0x41b7a8 VFMADD231PD	%ZMM12,%ZMM18,%ZMM11

  (259) 0x41b7ae VFMADD213PD	%ZMM14,%ZMM18,%ZMM11

  (259) 0x41b7b4 VFMADD213PD	%ZMM13,%ZMM18,%ZMM11

  (259) 0x41b7ba VMULPD	%ZMM28,%ZMM11,%ZMM11

  (259) 0x41b7c0 VXORPD	%XMM12,%XMM12,%XMM12

  (259) 0x41b7c5 KMOVQ	%K1,%K2

  (259) 0x41b7ca VGATHERQPD	0x10(,%ZMM10,1),%ZMM12{%K2}

  (259) 0x41b7d5 VMOVAPD	%ZMM12,%ZMM27{%K1}

  (259) 0x41b7db VFMADD231PD	%ZMM15,%ZMM18,%ZMM7

  (259) 0x41b7e1 VFMADD213PD	%ZMM17,%ZMM18,%ZMM7

  (259) 0x41b7e7 VFMADD213PD	%ZMM16,%ZMM18,%ZMM7

  (259) 0x41b7ed VXORPD	%XMM12,%XMM12,%XMM12

  (259) 0x41b7f2 KMOVQ	%K1,%K2

  (259) 0x41b7f7 VGATHERQPD	0x18(,%ZMM10,1),%ZMM12{%K2}

  (259) 0x41b802 VMOVAPD	%ZMM12,%ZMM26{%K1}

  (259) 0x41b808 VFMADD231PD	%ZMM3,%ZMM18,%ZMM1

  (259) 0x41b80e VFMADD213PD	%ZMM5,%ZMM18,%ZMM1

  (259) 0x41b814 VFMADD213PD	%ZMM4,%ZMM18,%ZMM1

  (259) 0x41b81a VFMADD213PD	%ZMM11,%ZMM29,%ZMM1

  (259) 0x41b820 VFMADD231PD	%ZMM6,%ZMM18,%ZMM2

  (259) 0x41b826 VFMADD213PD	%ZMM9,%ZMM18,%ZMM2

  (259) 0x41b82c VFMADD213PD	%ZMM8,%ZMM18,%ZMM2

  (259) 0x41b832 VFMADD213PD	%ZMM1,%ZMM27,%ZMM2

  (259) 0x41b838 VFMADD231PD	%ZMM7,%ZMM26,%ZMM2{%K1}{z}

  (259) 0x41b83e VEXTRACTF64X4	$0x1,%ZMM2,%YMM1

  (259) 0x41b845 VADDPD	%ZMM1,%ZMM2,%ZMM1

  (259) 0x41b84b VEXTRACTF128	$0x1,%YMM1,%XMM2

  (259) 0x41b851 VADDPD	%XMM2,%XMM1,%XMM1

  (259) 0x41b855 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

  (259) 0x41b85a VADDSD	%XMM2,%XMM1,%XMM1

  (259) 0x41b85e VADDSD	%XMM1,%XMM0,%XMM0

  (259) 0x41b862 VADDSD	%XMM31,%XMM0,%XMM31

  (259) 0x41b868 LEA	0x1(%RDI),%RDX

  (259) 0x41b86c CMP	%RAX,%RDI

  (259) 0x41b86f MOV	%RDX,%RDI

  (259) 0x41b872 JE	41b610

  (259) 0x41b878 MOV	(%RCX,%RDI,8),%R8

  (259) 0x41b87c TEST	%R8,%R8

  (259) 0x41b87f JE	41b868

  (259) 0x41b881 MOV	0x268(%R14),%R9

  (259) 0x41b888 MOV	0x18(%R9),%R9

  (259) 0x41b88c MOV	(%R9,%RDI,4),%R11

  (259) 0x41b890 MOV	%R11,%R10

  (259) 0x41b893 SHR	$0x20,%R10

  (259) 0x41b897 SUB	%R11D,%R10D

  (259) 0x41b89a VXORPD	%XMM0,%XMM0,%XMM0

  (259) 0x41b89e TEST	%R10D,%R10D

  (259) 0x41b8a1 JLE	41b862

  (259) 0x41b8a3 VMOVSD	0x8(%R8),%XMM1

  (259) 0x41b8a9 MOV	%R10D,%R10D

  (259) 0x41b8ac MOV	%R10,%R15

  (259) 0x41b8af MOVSXD	%R11D,%RBX

  (259) 0x41b8b2 MOV	$-0x10,%EDX

  (259) 0x41b8b7 AND	%RDX,%R15

  (259) 0x41b8ba JE	41bbab

  (259) 0x41b8c0 VMOVQ	%R11,%XMM2

  (259) 0x41b8c5 VBROADCASTSD	%XMM1,%ZMM3

  (259) 0x41b8cb MOV	(%RSP),%RDX

  (259) 0x41b8cf LEA	(%RDX,%RBX,8),%R12

  (259) 0x41b8d3 XOR	%R9D,%R9D

  (259) 0x41b8d6 XOR	%R13D,%R13D

  (259) 0x41b8d9 VMOVDQU64	0xd7a1d(%RIP),%ZMM7

  (259) 0x41b8e3 NOPW	%CS:(%RAX,%RAX,1)

    (262) 0x41b8f0 VMOVUPD	(%R12,%R13,8),%ZMM4

    (262) 0x41b8f7 VMOVUPD	0x40(%R12,%R13,8),%ZMM5

    (262) 0x41b8ff VMOVD	%R13D,%XMM6

    (262) 0x41b904 VPADDD	%XMM2,%XMM6,%XMM6

    (262) 0x41b908 VPBROADCASTD	%XMM6,%ZMM6

    (262) 0x41b90e VPCMPNEQD	%ZMM7,%ZMM6,%K0

    (262) 0x41b915 VCMPPD	$0x1,%ZMM3,%ZMM4,%K1

    (262) 0x41b91c VCMPPD	$0x1,%ZMM3,%ZMM5,%K2

    (262) 0x41b923 KUNPCKBW	%K1,%K2,%K3

    (262) 0x41b927 KANDW	%K0,%K3,%K3

    (262) 0x41b92b MOVSXD	%R9D,%R9

    (262) 0x41b92e KANDB	%K0,%K1,%K1

    (262) 0x41b932 VCOMPRESSPD	%ZMM4,(%RSI,%R9,8){%K1}

    (262) 0x41b939 LEA	(%RSI,%R9,8),%RBP

    (262) 0x41b93d KSHIFTRW	$0x8,%K0,%K0

    (262) 0x41b943 KANDB	%K0,%K2,%K2

    (262) 0x41b947 KMOVB	%K1,%EDX

    (262) 0x41b94b POPCNT	%EDX,%EDX

    (262) 0x41b94f VCOMPRESSPD	%ZMM5,(%RBP,%RDX,8){%K2}

    (262) 0x41b957 KMOVW	%K3,%EDX

    (262) 0x41b95b POPCNT	%EDX,%EDX

    (262) 0x41b95f ADD	%EDX,%R9D

    (262) 0x41b962 ADD	$0x10,%R13

    (262) 0x41b966 CMP	%R15,%R13

    (262) 0x41b969 JB	41b8f0

  (259) 0x41b96b CMP	%R10,%R15

  (259) 0x41b96e JNE	41bbb1

  (259) 0x41b974 TEST	%R9D,%R9D

  (259) 0x41b977 JLE	41b862

  (259) 0x41b97d VMOVSD	0x238(%R8),%XMM3

  (259) 0x41b986 MOV	0x218(%R8),%R10

  (259) 0x41b98d VMOVSD	0x18(%R8),%XMM17

  (259) 0x41b994 VMOVSD	0x20(%R8),%XMM1

  (259) 0x41b99a VMOVSD	0x28(%R8),%XMM5

  (259) 0x41b9a0 VMOVSD	0x30(%R8),%XMM4

  (259) 0x41b9a6 VMOVSD	0x38(%R8),%XMM12

  (259) 0x41b9ac VMOVSD	0x40(%R8),%XMM11

  (259) 0x41b9b2 VMOVSD	0x48(%R8),%XMM14

  (259) 0x41b9b8 VMOVSD	0x50(%R8),%XMM13

  (259) 0x41b9be VMOVSD	0x58(%R8),%XMM6

  (259) 0x41b9c4 VMOVSD	0x60(%R8),%XMM2

  (259) 0x41b9ca VMOVSD	0x68(%R8),%XMM9

  (259) 0x41b9d0 VMOVSD	0x70(%R8),%XMM8

  (259) 0x41b9d6 VMOVSD	0x78(%R8),%XMM15

  (259) 0x41b9dc VMOVSD	0x80(%R8),%XMM7

  (259) 0x41b9e5 VMOVSD	0x88(%R8),%XMM16

  (259) 0x41b9ec VMOVSD	0x90(%R8),%XMM0

  (259) 0x41b9f5 MOV	%R9D,%R9D

  (259) 0x41b9f8 MOV	%R9,%R8

  (259) 0x41b9fb VPBROADCASTQ	%R9,%ZMM18

  (259) 0x41ba01 VPBROADCASTQ	%R10,%ZMM10

  (259) 0x41ba07 MOV	$-0x8,%EDX

  (259) 0x41ba0c VBROADCASTSD	%XMM3,%ZMM19

  (259) 0x41ba12 VBROADCASTSD	%XMM17,%ZMM3

  (259) 0x41ba18 VBROADCASTSD	%XMM1,%ZMM1

  (259) 0x41ba1e VBROADCASTSD	%XMM5,%ZMM5

  (259) 0x41ba24 VBROADCASTSD	%XMM4,%ZMM4

  (259) 0x41ba2a VBROADCASTSD	%XMM12,%ZMM12

  (259) 0x41ba30 VBROADCASTSD	%XMM11,%ZMM11

  (259) 0x41ba36 VBROADCASTSD	%XMM14,%ZMM14

  (259) 0x41ba3c VBROADCASTSD	%XMM13,%ZMM13

  (259) 0x41ba42 VBROADCASTSD	%XMM6,%ZMM6

  (259) 0x41ba48 VBROADCASTSD	%XMM2,%ZMM2

  (259) 0x41ba4e VBROADCASTSD	%XMM9,%ZMM9

  (259) 0x41ba54 VBROADCASTSD	%XMM8,%ZMM8

  (259) 0x41ba5a VBROADCASTSD	%XMM15,%ZMM15

  (259) 0x41ba60 VBROADCASTSD	%XMM7,%ZMM7

  (259) 0x41ba66 VBROADCASTSD	%XMM16,%ZMM17

  (259) 0x41ba6c VBROADCASTSD	%XMM0,%ZMM16

  (259) 0x41ba72 AND	%RDX,%R8

  (259) 0x41ba75 JE	41b719

  (259) 0x41ba7b VXORPD	%XMM0,%XMM0,%XMM0

  (259) 0x41ba7f XOR	%R11D,%R11D

  (259) 0x41ba82 NOPW	%CS:(%RAX,%RAX,1)

    (260) 0x41ba90 VMULPD	(%RSI,%R11,8),%ZMM19,%ZMM20

    (260) 0x41ba97 VCVTTPD2DQ	%ZMM20,%YMM21

    (260) 0x41ba9d VRNDSCALEPD	$0xb,%ZMM20,%ZMM22

    (260) 0x41baa4 VSUBPD	%ZMM22,%ZMM20,%ZMM20

    (260) 0x41baaa VXORPD	%XMM22,%XMM22,%XMM22

    (260) 0x41bab0 KXNORW	%K0,%K0,%K1

    (260) 0x41bab4 VGATHERDPD	(%R10,%YMM21,8),%ZMM22{%K1}

    (260) 0x41babb VXORPD	%XMM23,%XMM23,%XMM23

    (260) 0x41bac1 KXNORW	%K0,%K0,%K1

    (260) 0x41bac5 VGATHERDPD	0x8(%R10,%YMM21,8),%ZMM23{%K1}

    (260) 0x41bacd VXORPD	%XMM24,%XMM24,%XMM24

    (260) 0x41bad3 KXNORW	%K0,%K0,%K1

    (260) 0x41bad7 VGATHERDPD	0x10(%R10,%YMM21,8),%ZMM24{%K1}

    (260) 0x41badf VXORPD	%XMM25,%XMM25,%XMM25

    (260) 0x41bae5 KXNORW	%K0,%K0,%K1

    (260) 0x41bae9 VGATHERDPD	0x18(%R10,%YMM21,8),%ZMM25{%K1}

    (260) 0x41baf1 VMOVAPD	%ZMM3,%ZMM21

    (260) 0x41baf7 VFMADD213PD	%ZMM1,%ZMM20,%ZMM21

    (260) 0x41bafd VFMADD213PD	%ZMM5,%ZMM20,%ZMM21

    (260) 0x41bb03 VFMADD213PD	%ZMM4,%ZMM20,%ZMM21

    (260) 0x41bb09 VFMADD213PD	%ZMM0,%ZMM22,%ZMM21

    (260) 0x41bb0f VMOVAPD	%ZMM12,%ZMM0

    (260) 0x41bb15 VFMADD213PD	%ZMM11,%ZMM20,%ZMM0

    (260) 0x41bb1b VFMADD213PD	%ZMM14,%ZMM20,%ZMM0

    (260) 0x41bb21 VFMADD213PD	%ZMM13,%ZMM20,%ZMM0

    (260) 0x41bb27 VFMADD213PD	%ZMM21,%ZMM23,%ZMM0

    (260) 0x41bb2d VMOVAPD	%ZMM6,%ZMM21

    (260) 0x41bb33 VFMADD213PD	%ZMM2,%ZMM20,%ZMM21

    (260) 0x41bb39 VFMADD213PD	%ZMM9,%ZMM20,%ZMM21

    (260) 0x41bb3f VFMADD213PD	%ZMM8,%ZMM20,%ZMM21

    (260) 0x41bb45 VFMADD213PD	%ZMM0,%ZMM24,%ZMM21

    (260) 0x41bb4b VMOVAPD	%ZMM15,%ZMM0

    (260) 0x41bb51 VFMADD213PD	%ZMM7,%ZMM20,%ZMM0

    (260) 0x41bb57 VFMADD213PD	%ZMM17,%ZMM20,%ZMM0

    (260) 0x41bb5d VFMADD213PD	%ZMM16,%ZMM20,%ZMM0

    (260) 0x41bb63 VFMADD213PD	%ZMM21,%ZMM25,%ZMM0

    (260) 0x41bb69 ADD	$0x8,%R11

    (260) 0x41bb6d CMP	%R8,%R11

    (260) 0x41bb70 JB	41ba90

  (259) 0x41bb76 VEXTRACTF64X4	$0x1,%ZMM0,%YMM20

  (259) 0x41bb7d VADDPD	%ZMM20,%ZMM0,%ZMM0

  (259) 0x41bb83 VEXTRACTF32X4	$0x1,%YMM0,%XMM20

  (259) 0x41bb8a VADDPD	%XMM20,%XMM0,%XMM0

  (259) 0x41bb90 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM20

  (259) 0x41bb97 VADDSD	%XMM20,%XMM0,%XMM0

  (259) 0x41bb9d CMP	%R9,%R8

  (259) 0x41bba0 JNE	41b720

  (259) 0x41bba6 JMP	41b862

  (259) 0x41bbab XOR	%R15D,%R15D

  (259) 0x41bbae XOR	%R9D,%R9D

  (259) 0x41bbb1 SUB	%R15,%R10

  (259) 0x41bbb4 ADD	%R15D,%R11D

  (259) 0x41bbb7 NOT	%R11D

  (259) 0x41bbba ADD	%R15,%RBX

  (259) 0x41bbbd MOV	(%RSP),%RDX

  (259) 0x41bbc1 LEA	(%RDX,%RBX,8),%RBX

  (259) 0x41bbc5 XOR	%R15D,%R15D

  (259) 0x41bbc8 JMP	41bbdc

0x41bbca NOPW	(%RAX,%RAX,1)

    (261) 0x41bbd0 INC	%R15

    (261) 0x41bbd3 CMP	%R15,%R10

    (261) 0x41bbd6 JE	41b974

    (261) 0x41bbdc VMOVSD	(%RBX,%R15,8),%XMM2

    (261) 0x41bbe2 VUCOMISD	%XMM2,%XMM1

    (261) 0x41bbe6 JBE	41bbd0

    (261) 0x41bbe8 CMP	%R15D,%R11D

    (261) 0x41bbeb JE	41bbd0

    (261) 0x41bbed MOVSXD	%R9D,%R9

    (261) 0x41bbf0 VMOVSD	%XMM2,(%RSI,%R9,8)

    (261) 0x41bbf6 INC	%R9D

    (261) 0x41bbf9 JMP	41bbd0

0x41bbfb NOPL	(%RAX,%RAX,1)

(257) 0x41bc00 MOV	0x90(%R15),%EBX

(257) 0x41bc07 TEST	%EBX,%EBX

(257) 0x41bc09 JLE	41b5d4

(257) 0x41bc0f MOV	0xa0(%R15),%RAX

(257) 0x41bc16 MOV	0x1c8(%R15),%R12

(257) 0x41bc1d MOV	0x18(%RAX),%RBP

(257) 0x41bc21 VXORPD	%XMM31,%XMM31,%XMM31

(257) 0x41bc27 XOR	%R15D,%R15D

(257) 0x41bc2a VMOVUPD	0x140(%RSP),%ZMM26

(257) 0x41bc32 VMOVUPD	0x100(%RSP),%ZMM27

(257) 0x41bc3a VMOVUPD	0xc0(%RSP),%ZMM28

(257) 0x41bc42 VMOVUPD	0x80(%RSP),%ZMM29

(257) 0x41bc4a VMOVUPD	0x40(%RSP),%ZMM30

(257) 0x41bc52 JMP	41bc72

0x41bc54 NOPW	%CS:(%RAX,%RAX,1)

  (258) 0x41bc60 VADDSD	%XMM31,%XMM1,%XMM31

  (258) 0x41bc66 INC	%R15

  (258) 0x41bc69 CMP	%R15,%RBX

  (258) 0x41bc6c JE	41b610

  (258) 0x41bc72 MOVSXD	(%RBP,%R15,4),%RAX

  (258) 0x41bc77 MOV	(%R12,%RAX,8),%R13

  (258) 0x41bc7b TEST	%R13,%R13

  (258) 0x41bc7e JE	41bc66

  (258) 0x41bc80 MOV	(%RSP),%RAX

  (258) 0x41bc84 VMOVSD	(%RAX,%R15,8),%XMM0

  (258) 0x41bc8a VMOVSD	0x8(%R13),%XMM2

  (258) 0x41bc90 VXORPD	%XMM1,%XMM1,%XMM1

  (258) 0x41bc94 VUCOMISD	%XMM0,%XMM2

  (258) 0x41bc98 JBE	41bc60

  (258) 0x41bc9a VMULSD	0x238(%R13),%XMM0,%XMM0

  (258) 0x41bca3 LEA	0x38(%RSP),%RDI

  (258) 0x41bca8 VMOVSD	%XMM31,0x30(%RSP)

  (258) 0x41bcb0 CALL	4d3cf0 <modf>

  (258) 0x41bcb5 VMOVSD	0x30(%RSP),%XMM31

  (258) 0x41bcbd VMOVUPD	0x40(%RSP),%ZMM30

  (258) 0x41bcc5 VMOVUPD	0x80(%RSP),%ZMM29

  (258) 0x41bccd VMOVUPD	0xc0(%RSP),%ZMM28

  (258) 0x41bcd5 VMOVUPD	0x100(%RSP),%ZMM27

  (258) 0x41bcdd VMOVUPD	0x140(%RSP),%ZMM26

  (258) 0x41bce5 VCVTTSD2SI	0x38(%RSP),%EAX

  (258) 0x41bceb CLTQ

  (258) 0x41bced VMOVSD	0x20(%R13),%XMM1

  (258) 0x41bcf3 VFMADD231SD	0x18(%R13),%XMM0,%XMM1

  (258) 0x41bcf9 VFMADD213SD	0x28(%R13),%XMM0,%XMM1

  (258) 0x41bcff VFMADD213SD	0x30(%R13),%XMM0,%XMM1

  (258) 0x41bd05 MOV	0x218(%R13),%RCX

  (258) 0x41bd0c VMULSD	(%RCX,%RAX,8),%XMM1,%XMM1

  (258) 0x41bd11 VMOVSD	0x40(%R13),%XMM2

  (258) 0x41bd17 VFMADD231SD	0x38(%R13),%XMM0,%XMM2

  (258) 0x41bd1d VFMADD213SD	0x48(%R13),%XMM0,%XMM2

  (258) 0x41bd23 VFMADD213SD	0x50(%R13),%XMM0,%XMM2

  (258) 0x41bd29 VFMADD132SD	0x8(%RCX,%RAX,8),%XMM1,%XMM2

  (258) 0x41bd30 VMOVSD	0x60(%R13),%XMM3

  (258) 0x41bd36 VFMADD231SD	0x58(%R13),%XMM0,%XMM3

  (258) 0x41bd3c VFMADD213SD	0x68(%R13),%XMM0,%XMM3

  (258) 0x41bd42 VFMADD213SD	0x70(%R13),%XMM0,%XMM3

  (258) 0x41bd48 VFMADD132SD	0x10(%RCX,%RAX,8),%XMM2,%XMM3

  (258) 0x41bd4f VMOVSD	0x80(%R13),%XMM1

  (258) 0x41bd58 VFMADD231SD	0x78(%R13),%XMM0,%XMM1

  (258) 0x41bd5e VFMADD213SD	0x88(%R13),%XMM0,%XMM1

  (258) 0x41bd67 VFMADD213SD	0x90(%R13),%XMM0,%XMM1

  (258) 0x41bd70 VFMADD132SD	0x18(%RCX,%RAX,8),%XMM3,%XMM1

  (258) 0x41bd77 JMP	41bc60

0x41bd7c ADD	$0x188,%RSP

0x41bd83 POP	%RBX

0x41bd84 POP	%R12

0x41bd86 POP	%R13

0x41bd88 POP	%R14

0x41bd8a POP	%R15

0x41bd8c POP	%RBP

0x41bd8d RET

0x41bd8e XCHG	%AX,%AX

Coverage (%)	Name	Module
►95.12+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►2.67+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.06+	qmcplusplus::WaveFunction::eva[...]	exec
○	qmcplusplus::NonLocalPP<double[...]	exec
○	main.extracted.109	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 2.88 to 0.21 cycles (13.94x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	27
nb uops	23
loop length	95
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Dispatch	1.25
Overall L1	2.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.88 cycles. At this rate:

2% of peak load performance is reached (5.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.35 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.88 to 1.25 cycles (2.30x speedup).

ASM code

In the binary file, the address of the function is: 41b5a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP (%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 41bd7c <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x7dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 41b675 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xd5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	27
nb uops	23
loop length	95
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Dispatch	1.25
Overall L1	2.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.88 cycles. At this rate:

2% of peak load performance is reached (5.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.35 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41b5a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP (%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 41bd7c <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x7dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 41b675 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0xd5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x188,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	0.02	0.04
▼Loop 257 - - exec–	0.00	0.01
▼Loop 259 - - exec–	0.00	0.01
○Loop 262 - - exec	0.01	0.02
○Loop 260 - - exec	0.00	0.00
○Loop 261 - - exec	0.00	0.00
○Loop 258 - - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code