OV - exec - Loop 867

	Loop Id: 867	Module: exec	Source: MultiBsplineRef.hpp:227-262 [...]	Coverage: 0.02%

0x25de40 MOV	0xf8(%RSP),%RCX

0x25de48 MOV	0x118(%RSP),%RDX

0x25de50 INC	%RDX

0x25de53 ADD	%RCX,%R8

0x25de56 ADD	%RCX,%R9

0x25de59 ADD	%RCX,%RSI

0x25de5c ADD	%RCX,%R11

0x25de5f CMP	$0x4,%RDX

0x25de63 JE	25dd60

0x25de69 VMOVSD	0x340(%RSP,%RDX,8),%XMM2

0x25de72 VMOVSD	0x108(%RSP),%XMM0

0x25de7b VMOVSD	0x100(%RSP),%XMM3

0x25de84 CMP	$0x4,%EAX

0x25de87 MOV	%RDX,0x118(%RSP)

0x25de8f VMULSD	0x110(%RSP),%XMM2,%XMM4

0x25de98 SETB	%CL

0x25de9b OR	0x17(%RSP),%CL

0x25de9f VMULSD	%XMM2,%XMM0,%XMM28

0x25dea5 VMULSD	%XMM2,%XMM3,%XMM29

0x25deab VMOVSD	0x280(%RSP,%RDX,8),%XMM2

0x25deb4 VMOVAPD	%XMM4,0x20(%RSP)

0x25deba VMULSD	%XMM0,%XMM2,%XMM0

0x25debe VMULSD	%XMM3,%XMM2,%XMM31

0x25dec4 VMULSD	0x240(%RSP,%RDX,8),%XMM3,%XMM2

0x25decd VMOVAPD	%XMM0,0x80(%RSP)

0x25ded6 VMOVAPD	%XMM2,0x60(%RSP)

0x25dedc TEST	$0x1,%CL

0x25dedf JE	25def0

0x25dee1 MOV	0x50(%RSP),%RDX

0x25dee6 XOR	%ECX,%ECX

0x25dee8 JMP	25e560

0x25def0 CMP	$0x10,%EAX

0x25def3 JAE	25df10

0x25def5 MOV	0x50(%RSP),%RDX

0x25defa XOR	%R10D,%R10D

0x25defd JMP	25e36b

0x25df10 MOV	0xe0(%RSP),%RCX

0x25df18 MOV	0xe8(%RSP),%RAX

0x25df20 VMOVAPD	%ZMM18,%ZMM27

0x25df26 VMOVAPD	%ZMM17,%ZMM18

0x25df2c VMOVAPD	0x440(%RSP),%ZMM17

0x25df34 VMOVAPD	0x400(%RSP),%ZMM16

0x25df3c VMOVAPD	0x580(%RSP),%ZMM13

0x25df44 VBROADCASTSD	%XMM4,%ZMM1

0x25df4a VMOVAPD	%ZMM19,%ZMM30

0x25df50 VBROADCASTSD	%XMM0,%ZMM26

0x25df56 VBROADCASTSD	%XMM28,%ZMM19

0x25df5c VBROADCASTSD	%XMM2,%ZMM25

0x25df62 VBROADCASTSD	%XMM31,%ZMM21

0x25df68 VBROADCASTSD	%XMM29,%ZMM22

0x25df6e XOR	%R10D,%R10D

0x25df71 VMOVAPD	%ZMM1,0x4c0(%RSP)

0x25df79 ADD	%RDX,%RCX

0x25df7c IMUL	0x78(%RSP),%RCX

0x25df82 MOV	0x1f8(%RSP),%RDX

0x25df8a LEA	(%RAX,%RCX,8),%RAX

0x25df8e MOV	0x58(%RSP),%RCX

0x25df93 MOV	%RAX,0x160(%RSP)

0x25df9b LEA	(%RAX,%RCX,8),%RCX

0x25df9f MOV	%RCX,0x180(%RSP)

0x25dfa7 MOV	0x200(%RSP),%RCX

0x25dfaf LEA	(%RAX,%RCX,8),%RCX

0x25dfb3 MOV	%RCX,0x128(%RSP)

0x25dfbb MOV	0x208(%RSP),%RCX

0x25dfc3 LEA	(%RAX,%RCX,8),%RAX

0x25dfc7 MOV	%RAX,0x120(%RSP)

0x25dfcf MOV	0x1f0(%RSP),%RAX

0x25dfd7 NOPW	(%RAX,%RAX,1)

  (865) 0x25dfe0 MOV	0x160(%RSP),%RCX

  (865) 0x25dfe8 VMOVUPD	(%R8,%R10,8),%ZMM14

  (865) 0x25dfef VMOVUPD	0x40(%RCX,%R10,8),%ZMM23

  (865) 0x25dff7 MOV	0x180(%RSP),%RCX

  (865) 0x25dfff VMULPD	%ZMM9,%ZMM14,%ZMM2

  (865) 0x25e005 VMOVUPD	(%RCX,%R10,8),%ZMM3

  (865) 0x25e00c VMOVUPD	0x40(%RCX,%R10,8),%ZMM4

  (865) 0x25e014 MOV	0x128(%RSP),%RCX

  (865) 0x25e01c VMULPD	%ZMM9,%ZMM23,%ZMM8

  (865) 0x25e022 VMOVUPD	(%RCX,%R10,8),%ZMM5

  (865) 0x25e029 VMOVUPD	0x40(%RCX,%R10,8),%ZMM6

  (865) 0x25e031 MOV	0x120(%RSP),%RCX

  (865) 0x25e039 VFMADD231PD	%ZMM10,%ZMM3,%ZMM2

  (865) 0x25e03f VFMADD231PD	%ZMM10,%ZMM4,%ZMM8

  (865) 0x25e045 VMULPD	%ZMM16,%ZMM23,%ZMM10

  (865) 0x25e04b VMULPD	%ZMM17,%ZMM4,%ZMM11

  (865) 0x25e051 VMULPD	%ZMM17,%ZMM3,%ZMM7

  (865) 0x25e057 VMOVUPD	0x40(%RCX,%R10,8),%ZMM1

  (865) 0x25e05f VMOVUPD	(%RCX,%R10,8),%ZMM0

  (865) 0x25e066 LEA	(%R15,%R10,8),%RCX

  (865) 0x25e06a VFMADD231PD	%ZMM18,%ZMM6,%ZMM10

  (865) 0x25e070 VFMADD231PD	%ZMM12,%ZMM6,%ZMM8

  (865) 0x25e076 VFMADD231PD	%ZMM12,%ZMM5,%ZMM2

  (865) 0x25e07c VMOVAPD	%ZMM9,%ZMM12

  (865) 0x25e082 VMULPD	%ZMM16,%ZMM14,%ZMM9

  (865) 0x25e088 VMULPD	%ZMM30,%ZMM14,%ZMM14

  (865) 0x25e08e VFMADD231PD	%ZMM3,%ZMM20,%ZMM14

  (865) 0x25e094 VMOVAPD	0x4c0(%RSP),%ZMM3

  (865) 0x25e09c VFMADD231PD	%ZMM18,%ZMM5,%ZMM9

  (865) 0x25e0a2 VFMADD231PD	%ZMM27,%ZMM1,%ZMM11

  (865) 0x25e0a8 VFMADD231PD	%ZMM1,%ZMM13,%ZMM8

  (865) 0x25e0ae VFMADD231PD	%ZMM0,%ZMM13,%ZMM2

  (865) 0x25e0b4 VFMADD231PD	%ZMM27,%ZMM0,%ZMM7

  (865) 0x25e0ba VFMADD231PD	%ZMM5,%ZMM24,%ZMM14

  (865) 0x25e0c0 VFMADD231PD	%ZMM11,%ZMM15,%ZMM10

  (865) 0x25e0c6 VMULPD	%ZMM30,%ZMM23,%ZMM11

  (865) 0x25e0cc VFMADD231PD	%ZMM7,%ZMM15,%ZMM9

  (865) 0x25e0d2 VFMADD231PD	%ZMM0,%ZMM15,%ZMM14

  (865) 0x25e0d8 VFMADD231PD	%ZMM4,%ZMM20,%ZMM11

  (865) 0x25e0de VMOVUPD	(%R15,%R10,8),%ZMM4

  (865) 0x25e0e5 VFMADD231PD	%ZMM6,%ZMM24,%ZMM11

  (865) 0x25e0eb VFMADD231PD	%ZMM1,%ZMM15,%ZMM11

  (865) 0x25e0f1 VMOVUPD	0x40(%R15,%R10,8),%ZMM1

  (865) 0x25e0f9 VFMADD231PD	%ZMM2,%ZMM3,%ZMM4

  (865) 0x25e0ff VMOVUPD	%ZMM4,(%R15,%R10,8)

  (865) 0x25e106 VFMADD231PD	%ZMM8,%ZMM3,%ZMM1

  (865) 0x25e10c VMOVUPD	%ZMM1,0x40(%R15,%R10,8)

  (865) 0x25e114 VMOVUPD	(%RDI,%RCX,1),%ZMM0

  (865) 0x25e11b VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1

  (865) 0x25e123 VFMADD231PD	%ZMM2,%ZMM26,%ZMM0

  (865) 0x25e129 VFMADD231PD	%ZMM8,%ZMM26,%ZMM1

  (865) 0x25e12f VMOVUPD	%ZMM0,(%RDI,%RCX,1)

  (865) 0x25e136 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)

  (865) 0x25e13e LEA	(%RCX,%RDI,1),%RCX

  (865) 0x25e142 VMOVUPD	(%RDI,%RCX,1),%ZMM0

  (865) 0x25e149 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1

  (865) 0x25e151 VFMADD231PD	%ZMM19,%ZMM9,%ZMM0

  (865) 0x25e157 VFMADD231PD	%ZMM19,%ZMM10,%ZMM1

  (865) 0x25e15d VMOVUPD	%ZMM0,(%RDI,%RCX,1)

  (865) 0x25e164 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)

  (865) 0x25e16c LEA	(%RCX,%RDI,1),%RCX

  (865) 0x25e170 VMOVUPD	(%RDI,%RCX,1),%ZMM0

  (865) 0x25e177 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1

  (865) 0x25e17f VFMADD231PD	%ZMM2,%ZMM25,%ZMM0

  (865) 0x25e185 VFMADD231PD	%ZMM8,%ZMM25,%ZMM1

  (865) 0x25e18b VMOVUPD	%ZMM0,(%RDI,%RCX,1)

  (865) 0x25e192 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)

  (865) 0x25e19a LEA	(%RCX,%RDI,1),%RCX

  (865) 0x25e19e VMOVUPD	(%RDI,%RCX,1),%ZMM0

  (865) 0x25e1a5 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1

  (865) 0x25e1ad VFMADD231PD	%ZMM21,%ZMM9,%ZMM0

  (865) 0x25e1b3 VFMADD231PD	%ZMM21,%ZMM10,%ZMM1

  (865) 0x25e1b9 VMOVUPD	%ZMM0,(%RDI,%RCX,1)

  (865) 0x25e1c0 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)

  (865) 0x25e1c8 LEA	(%RCX,%RDI,1),%RCX

  (865) 0x25e1cc VFMADD213PD	(%RDI,%RCX,1),%ZMM22,%ZMM14

  (865) 0x25e1d3 VFMADD213PD	0x40(%RDI,%RCX,1),%ZMM22,%ZMM11

  (865) 0x25e1db VMOVUPD	%ZMM14,(%RDI,%RCX,1)

  (865) 0x25e1e2 VMOVUPD	%ZMM11,0x40(%RDI,%RCX,1)

  (865) 0x25e1ea VMOVUPD	(%R14,%R10,8),%ZMM0

  (865) 0x25e1f1 VMOVUPD	0x40(%R14,%R10,8),%ZMM1

  (865) 0x25e1f9 VFMADD231PD	%ZMM19,%ZMM2,%ZMM0

  (865) 0x25e1ff VFMADD231PD	%ZMM19,%ZMM8,%ZMM1

  (865) 0x25e205 VMOVUPD	%ZMM0,(%R14,%R10,8)

  (865) 0x25e20c VMOVUPD	%ZMM1,0x40(%R14,%R10,8)

  (865) 0x25e214 VMOVUPD	-0x40(%RDX,%R10,8),%ZMM0

  (865) 0x25e21c VMOVUPD	(%RDX,%R10,8),%ZMM1

  (865) 0x25e223 VFMADD231PD	%ZMM21,%ZMM2,%ZMM0

  (865) 0x25e229 VFMADD231PD	%ZMM21,%ZMM8,%ZMM1

  (865) 0x25e22f VFMADD213PD	(%RBX,%R10,8),%ZMM22,%ZMM2

  (865) 0x25e236 VFMADD213PD	0x40(%RBX,%R10,8),%ZMM22,%ZMM8

  (865) 0x25e23e VMOVUPD	%ZMM0,-0x40(%RDX,%R10,8)

  (865) 0x25e246 VMOVUPD	%ZMM1,(%RDX,%R10,8)

  (865) 0x25e24d VFMADD213PD	-0x40(%RAX,%R10,8),%ZMM22,%ZMM9

  (865) 0x25e255 VFMADD213PD	(%RAX,%R10,8),%ZMM22,%ZMM10

  (865) 0x25e25c VMOVUPD	%ZMM2,(%RBX,%R10,8)

  (865) 0x25e263 VMOVUPD	%ZMM8,0x40(%RBX,%R10,8)

  (865) 0x25e26b VMOVUPD	%ZMM9,-0x40(%RAX,%R10,8)

  (865) 0x25e273 VMOVUPD	%ZMM10,(%RAX,%R10,8)

  (865) 0x25e27a VMOVAPD	%ZMM12,%ZMM9

  (865) 0x25e280 VMOVAPD	0x380(%RSP),%ZMM12

  (865) 0x25e288 VMOVAPD	0x3c0(%RSP),%ZMM10

  (865) 0x25e290 ADD	$0x10,%R10

  (865) 0x25e294 CMP	%R10,0xb8(%RSP)

  (865) 0x25e29c JNE	25dfe0

0x25e2a2 VMOVAPD	%ZMM18,%ZMM17

0x25e2a8 VMOVAPD	%ZMM27,%ZMM18

0x25e2ae VMOVAPD	%ZMM30,%ZMM19

0x25e2b4 VMOVAPD	0x210(%RSP),%XMM11

0x25e2bd VMOVAPD	0x330(%RSP),%XMM14

0x25e2c6 VMOVAPD	0x320(%RSP),%XMM21

0x25e2ce VMOVAPD	0x220(%RSP),%YMM7

0x25e2d7 VMOVAPD	0x150(%RSP),%XMM22

0x25e2df VMOVAPD	0x310(%RSP),%XMM25

0x25e2e7 VMOVAPD	0x300(%RSP),%XMM26

0x25e2ef VMOVAPD	0x2f0(%RSP),%XMM23

0x25e2f7 VMOVAPD	0x560(%RSP),%YMM27

0x25e2ff VMOVAPD	0x540(%RSP),%YMM13

0x25e308 VMOVAPD	0x520(%RSP),%YMM30

0x25e310 VMOVAPD	0x500(%RSP),%YMM8

0x25e319 VMOVAPD	0x140(%RSP),%XMM16

0x25e321 VMOVAPD	0x20(%RSP),%XMM4

0x25e327 VMOVAPD	0x80(%RSP),%XMM0

0x25e330 VMOVAPD	0x60(%RSP),%XMM2

0x25e336 CMPQ	$0,0xb0(%RSP)

0x25e33f MOV	0x50(%RSP),%RDX

0x25e344 MOV	0x138(%RSP),%RAX

0x25e34c JE	25de40

0x25e352 MOV	0xb8(%RSP),%RCX

0x25e35a CMPL	$0x4,0xb0(%RSP)

0x25e362 MOV	%RCX,%R10

0x25e365 JB	25e560

0x25e36b VMOVAPD	%ZMM17,%ZMM18

0x25e371 VMOVAPD	0x440(%RSP),%ZMM17

0x25e379 VMOVAPD	0x400(%RSP),%ZMM16

0x25e381 VBROADCASTSD	%XMM4,%YMM1

0x25e386 VBROADCASTSD	%XMM0,%YMM0

0x25e38b VMOVAPD	%ZMM9,%ZMM12

0x25e391 VBROADCASTSD	%XMM2,%YMM10

0x25e396 VMOVAPD	%ZMM19,%ZMM22

0x25e39c VMOVAPD	%ZMM20,%ZMM2

0x25e3a2 VBROADCASTSD	%XMM28,%YMM9

0x25e3a8 VBROADCASTSD	%XMM31,%YMM19

0x25e3ae VBROADCASTSD	%XMM29,%YMM20

0x25e3b4 VMOVAPD	%YMM1,0x160(%RSP)

0x25e3bd VMOVAPD	%YMM0,0x180(%RSP)

0x25e3c6 NOPW	%CS:(%RAX,%RAX,1)

  (869) 0x25e3d0 VMOVUPD	(%R8,%R10,8),%YMM0

  (869) 0x25e3d6 VMOVUPD	(%R9,%R10,8),%YMM1

  (869) 0x25e3dc VMOVUPD	(%RSI,%R10,8),%YMM3

  (869) 0x25e3e2 VMOVUPD	(%R11,%R10,8),%YMM4

  (869) 0x25e3e8 LEA	(%R15,%R10,8),%RCX

  (869) 0x25e3ec VMULPD	%YMM0,%YMM12,%YMM5

  (869) 0x25e3f0 VMULPD	%YMM16,%YMM0,%YMM6

  (869) 0x25e3f6 VMULPD	%YMM22,%YMM0,%YMM0

  (869) 0x25e3fc VMULPD	%YMM17,%YMM1,%YMM7

  (869) 0x25e402 VFMADD231PD	%YMM27,%YMM1,%YMM5

  (869) 0x25e408 VFMADD231PD	%YMM1,%YMM2,%YMM0

  (869) 0x25e40d VMOVUPD	(%R15,%R10,8),%YMM1

  (869) 0x25e413 VFMADD231PD	%YMM8,%YMM4,%YMM7

  (869) 0x25e418 VFMADD231PD	%YMM18,%YMM3,%YMM6

  (869) 0x25e41e VFMADD231PD	%YMM13,%YMM3,%YMM5

  (869) 0x25e423 VFMADD231PD	%YMM7,%YMM15,%YMM6

  (869) 0x25e428 VFMADD231PD	%YMM3,%YMM24,%YMM0

  (869) 0x25e42e VFMADD231PD	%YMM4,%YMM30,%YMM5

  (869) 0x25e434 VFMADD231PD	0x160(%RSP),%YMM5,%YMM1

  (869) 0x25e43e VFMADD231PD	%YMM4,%YMM15,%YMM0

  (869) 0x25e443 VMOVUPD	%YMM1,(%R15,%R10,8)

  (869) 0x25e449 VMOVUPD	(%RCX,%R12,8),%YMM1

  (869) 0x25e44f VFMADD231PD	0x180(%RSP),%YMM5,%YMM1

  (869) 0x25e459 VMOVUPD	%YMM1,(%RCX,%R12,8)

  (869) 0x25e45f LEA	(%RCX,%R12,8),%RCX

  (869) 0x25e463 VMOVUPD	(%RDI,%RCX,1),%YMM1

  (869) 0x25e468 VFMADD231PD	%YMM9,%YMM6,%YMM1

  (869) 0x25e46d VMOVUPD	%YMM1,(%RDI,%RCX,1)

  (869) 0x25e472 LEA	(%RCX,%RDI,1),%RCX

  (869) 0x25e476 VMOVUPD	(%RDI,%RCX,1),%YMM1

  (869) 0x25e47b VFMADD231PD	%YMM5,%YMM10,%YMM1

  (869) 0x25e480 VMOVUPD	%YMM1,(%RDI,%RCX,1)

  (869) 0x25e485 LEA	(%RCX,%RDI,1),%RCX

  (869) 0x25e489 VMOVUPD	(%RDI,%RCX,1),%YMM1

  (869) 0x25e48e VFMADD231PD	%YMM19,%YMM6,%YMM1

  (869) 0x25e494 VMOVUPD	%YMM1,(%RDI,%RCX,1)

  (869) 0x25e499 LEA	(%RCX,%RDI,1),%RCX

  (869) 0x25e49d VFMADD213PD	(%RDI,%RCX,1),%YMM20,%YMM0

  (869) 0x25e4a4 VMOVUPD	%YMM0,(%RDI,%RCX,1)

  (869) 0x25e4a9 VMOVUPD	(%R14,%R10,8),%YMM0

  (869) 0x25e4af VFMADD231PD	%YMM9,%YMM5,%YMM0

  (869) 0x25e4b4 VMOVUPD	%YMM0,(%R14,%R10,8)

  (869) 0x25e4ba VMOVUPD	(%RDX,%R10,8),%YMM0

  (869) 0x25e4c0 VFMADD231PD	%YMM19,%YMM5,%YMM0

  (869) 0x25e4c6 VFMADD213PD	(%RBX,%R10,8),%YMM20,%YMM5

  (869) 0x25e4cd VMOVUPD	%YMM0,(%RDX,%R10,8)

  (869) 0x25e4d3 VFMADD213PD	(%R13,%R10,8),%YMM20,%YMM6

  (869) 0x25e4db VMOVUPD	%YMM5,(%RBX,%R10,8)

  (869) 0x25e4e1 VMOVUPD	%YMM6,(%R13,%R10,8)

  (869) 0x25e4e8 ADD	$0x4,%R10

  (869) 0x25e4ec CMP	%R10,0x90(%RSP)

  (869) 0x25e4f4 JNE	25e3d0

0x25e4fa VMOVAPD	%ZMM12,%ZMM9

0x25e500 VMOVAPD	%ZMM18,%ZMM17

0x25e506 VMOVAPD	%ZMM22,%ZMM19

0x25e50c VMOVAPD	0x220(%RSP),%YMM7

0x25e515 VMOVAPD	0x3c0(%RSP),%ZMM10

0x25e51d VMOVAPD	0x380(%RSP),%ZMM12

0x25e525 VMOVAPD	0x480(%RSP),%ZMM18

0x25e52d VMOVAPD	0x150(%RSP),%XMM22

0x25e535 VMOVAPD	0x140(%RSP),%XMM16

0x25e53d MOV	0x90(%RSP),%RCX

0x25e545 CMPQ	$0,0xf0(%RSP)

0x25e54e VMOVAPD	%ZMM2,%ZMM20

0x25e554 JE	25de40

0x25e55a NOPW	(%RAX,%RAX,1)

  (868) 0x25e560 VMOVSD	(%R9,%RCX,8),%XMM1

  (868) 0x25e566 VMOVSD	(%R8,%RCX,8),%XMM0

  (868) 0x25e56c VMOVSD	(%RSI,%RCX,8),%XMM2

  (868) 0x25e571 VMOVSD	(%R11,%RCX,8),%XMM3

  (868) 0x25e577 LEA	(%R15,%RCX,8),%R10

  (868) 0x25e57b VUNPCKLPD	%XMM3,%XMM2,%XMM4

  (868) 0x25e57f VUNPCKLPD	%XMM1,%XMM0,%XMM5

  (868) 0x25e583 VMULSD	%XMM22,%XMM1,%XMM6

  (868) 0x25e589 VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

  (868) 0x25e58f VMULPD	%YMM4,%YMM7,%YMM4

  (868) 0x25e593 VFMADD231SD	%XMM16,%XMM3,%XMM6

  (868) 0x25e599 VEXTRACTF128	$0x1,%YMM4,%XMM5

  (868) 0x25e59f VADDPD	%XMM5,%XMM4,%XMM4

  (868) 0x25e5a3 VSHUFPD	$0x1,%XMM4,%XMM4,%XMM5

  (868) 0x25e5a8 VADDSD	%XMM5,%XMM4,%XMM4

  (868) 0x25e5ac VMULSD	%XMM0,%XMM14,%XMM5

  (868) 0x25e5b0 VMULSD	%XMM25,%XMM0,%XMM0

  (868) 0x25e5b6 VFMADD231SD	%XMM1,%XMM26,%XMM0

  (868) 0x25e5bc VMOVSD	(%R15,%RCX,8),%XMM1

  (868) 0x25e5c2 VFMADD231SD	%XMM21,%XMM2,%XMM5

  (868) 0x25e5c8 VFMADD231SD	0x20(%RSP),%XMM4,%XMM1

  (868) 0x25e5cf VFMADD231SD	%XMM6,%XMM11,%XMM5

  (868) 0x25e5d4 VFMADD231SD	%XMM2,%XMM23,%XMM0

  (868) 0x25e5da VFMADD231SD	%XMM3,%XMM11,%XMM0

  (868) 0x25e5df VMOVSD	%XMM1,(%R15,%RCX,8)

  (868) 0x25e5e5 VMOVSD	(%R10,%R12,8),%XMM1

  (868) 0x25e5eb VFMADD231SD	0x80(%RSP),%XMM4,%XMM1

  (868) 0x25e5f5 VMOVSD	%XMM1,(%R10,%R12,8)

  (868) 0x25e5fb LEA	(%R10,%R12,8),%R10

  (868) 0x25e5ff VMOVSD	(%RDI,%R10,1),%XMM1

  (868) 0x25e605 VFMADD231SD	%XMM28,%XMM5,%XMM1

  (868) 0x25e60b VMOVSD	%XMM1,(%RDI,%R10,1)

  (868) 0x25e611 LEA	(%R10,%RDI,1),%R10

  (868) 0x25e615 VMOVSD	(%RDI,%R10,1),%XMM1

  (868) 0x25e61b VFMADD231SD	0x60(%RSP),%XMM4,%XMM1

  (868) 0x25e622 VMOVSD	%XMM1,(%RDI,%R10,1)

  (868) 0x25e628 LEA	(%R10,%RDI,1),%R10

  (868) 0x25e62c VMOVSD	(%RDI,%R10,1),%XMM1

  (868) 0x25e632 VFMADD231SD	%XMM31,%XMM5,%XMM1

  (868) 0x25e638 VMOVSD	%XMM1,(%RDI,%R10,1)

  (868) 0x25e63e LEA	(%R10,%RDI,1),%R10

  (868) 0x25e642 VFMADD213SD	(%RDI,%R10,1),%XMM29,%XMM0

  (868) 0x25e649 VMOVSD	%XMM0,(%RDI,%R10,1)

  (868) 0x25e64f VMOVSD	(%R14,%RCX,8),%XMM0

  (868) 0x25e655 VFMADD231SD	%XMM28,%XMM4,%XMM0

  (868) 0x25e65b VMOVSD	%XMM0,(%R14,%RCX,8)

  (868) 0x25e661 VMOVSD	(%RDX,%RCX,8),%XMM0

  (868) 0x25e666 VFMADD231SD	%XMM31,%XMM4,%XMM0

  (868) 0x25e66c VFMADD213SD	(%RBX,%RCX,8),%XMM29,%XMM4

  (868) 0x25e673 VMOVSD	%XMM0,(%RDX,%RCX,8)

  (868) 0x25e678 VFMADD213SD	(%R13,%RCX,8),%XMM29,%XMM5

  (868) 0x25e680 VMOVSD	%XMM4,(%RBX,%RCX,8)

  (868) 0x25e685 VMOVSD	%XMM5,(%R13,%RCX,8)

  (868) 0x25e68c INC	%RCX

  (868) 0x25e68f CMP	%RCX,%RAX

  (868) 0x25e692 JNE	25e560

0x25e698 JMP	25de40

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 227 - 262

--------------------------------------------------------------------------------

227:     for (int j = 0; j < 4; j++)

[...]

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►80.94+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.50+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.29+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.62+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	1.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.09
CQA cycles if fully vectorized	9.51
Front-end cycles	15.38
P0 cycles	4.83
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	16.00
P7 cycles	16.00
P8 cycles	16.00
P9 cycles	16.00
P10 cycles	3.00
P11 cycles	7.50
P12 cycles	7.50
P13 cycles	0.00
P14 cycles	3.50
P15 cycles	3.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	125.00
Nb uops	123.00
Nb loads	53.00
Nb stores	11.00
Nb stack references	47.00
FLOP/cycle	0.38
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	82.81
Bytes prefetched	0.00
Bytes loaded	1109.00
Bytes stored	216.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	54.65
Vectorization ratio load	77.14
Vectorization ratio store	54.55
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	41.18
Vector-efficiency ratio all	41.35
Vector-efficiency ratio load	43.39
Vector-efficiency ratio store	30.68
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	47.61

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	1.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P6, P7, P8, P9,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.09
CQA cycles if fully vectorized	9.51
Front-end cycles	15.38
P0 cycles	4.83
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	16.00
P7 cycles	16.00
P8 cycles	16.00
P9 cycles	16.00
P10 cycles	3.00
P11 cycles	7.50
P12 cycles	7.50
P13 cycles	0.00
P14 cycles	3.50
P15 cycles	3.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	125.00
Nb uops	123.00
Nb loads	53.00
Nb stores	11.00
Nb stack references	47.00
FLOP/cycle	0.38
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	82.81
Bytes prefetched	0.00
Bytes loaded	1109.00
Bytes stored	216.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	54.65
Vectorization ratio load	77.14
Vectorization ratio store	54.55
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	41.18
Vector-efficiency ratio all	41.35
Vector-efficiency ratio load	43.39
Vector-efficiency ratio store	30.68
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	47.61

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-239,242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 10.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 41% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 9.51 cycles (1.68x speedup).

Details

54% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

77% of SSE/AVX loads are used in vector version.
54% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 1109 bytes (138 double precision FP elements). The binary loop is storing 216 bytes (27 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	125
nb uops	123
loop length	808
used x86 registers	9
used mmx registers	0
used xmm registers	15
used ymm registers	11
used zmm registers	17
nb stack references	47

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	16.00	16.00	16.00	16.00	3.00	7.50	7.50	0.00	3.50	3.50
cycles	4.83	4.83	4.83	4.83	4.83	4.83	16.00	16.00	16.00	16.00	3.00	7.50	7.50	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.38
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	68%
load	81%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

INT+FP

all	54%
load	77%
store	54%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	41%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	48%
load	45%
store	45%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	59%

INT+FP

all	41%
load	43%
store	30%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

27% of peak load performance is reached (69.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 25de69

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 25dd60 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD 0x340(%RSP,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x108(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x100(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD 0x110(%RSP),%XMM2,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0x17(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
VMULSD %XMM2,%XMM0,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM3,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x280(%RSP,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM4,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULSD %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM2,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD 0x240(%RSP,%RDX,8),%XMM3,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM0,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM2,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
TEST $0x1,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 25def0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xc40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 25e560 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x12b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x10,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 25df10 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xc60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 25e36b <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x10bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0xe0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0xe8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
VMOVAPD %ZMM18,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x440(%RSP),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x400(%RSP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x580(%RSP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD %XMM4,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %ZMM19,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VBROADCASTSD %XMM0,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM28,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM31,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM29,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVAPD %ZMM1,0x4c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL 0x78(%RSP),%RCX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.33	N/A
MOV 0x1f8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RAX,%RCX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x200(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RCX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x208(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x1f0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %ZMM18,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM27,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM30,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x210(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x330(%RSP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x320(%RSP),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x220(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x150(%RSP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x310(%RSP),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x300(%RSP),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x2f0(%RSP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x560(%RSP),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x540(%RSP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x520(%RSP),%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x500(%RSP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x140(%RSP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x20(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x80(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x60(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
CMPQ $0,0xb0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x138(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
JE 25de40 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xb8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
CMPL $0x4,0xb0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JB 25e560 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x12b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x440(%RSP),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x400(%RSP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD %XMM4,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VBROADCASTSD %XMM2,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM20,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VBROADCASTSD %XMM28,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM31,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM29,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM1,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %YMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %ZMM12,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM22,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x220(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x3c0(%RSP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x380(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x480(%RSP),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x150(%RSP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x140(%RSP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x90(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
CMPQ $0,0xf0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
VMOVAPD %ZMM2,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
JE 25de40 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 25de40 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

54% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

77% of SSE/AVX loads are used in vector version.
54% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 1109 bytes (138 double precision FP elements). The binary loop is storing 216 bytes (27 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	125
nb uops	123
loop length	808
used x86 registers	9
used mmx registers	0
used xmm registers	15
used ymm registers	11
used zmm registers	17
nb stack references	47

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	16.00	16.00	16.00	16.00	3.00	7.50	7.50	0.00	3.50	3.50
cycles	4.83	4.83	4.83	4.83	4.83	4.83	16.00	16.00	16.00	16.00	3.00	7.50	7.50	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.38
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	68%
load	81%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

INT+FP

all	54%
load	77%
store	54%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	41%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	48%
load	45%
store	45%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	59%

INT+FP

all	41%
load	43%
store	30%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

27% of peak load performance is reached (69.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 25de69

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 25dd60 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD 0x340(%RSP,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x108(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x100(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD 0x110(%RSP),%XMM2,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0x17(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
VMULSD %XMM2,%XMM0,%XMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM2,%XMM3,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x280(%RSP,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM4,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMULSD %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM3,%XMM2,%XMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMULSD 0x240(%RSP,%RDX,8),%XMM3,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVAPD %XMM0,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM2,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
TEST $0x1,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 25def0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xc40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 25e560 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x12b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x10,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 25df10 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xc60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 25e36b <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x10bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0xe0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0xe8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
VMOVAPD %ZMM18,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x440(%RSP),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x400(%RSP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x580(%RSP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD %XMM4,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %ZMM19,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VBROADCASTSD %XMM0,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM28,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM31,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM29,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVAPD %ZMM1,0x4c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL 0x78(%RSP),%RCX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.33	N/A
MOV 0x1f8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RAX,%RCX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x200(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RCX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x208(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x1f0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %ZMM18,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM27,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM30,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x210(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x330(%RSP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x320(%RSP),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x220(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x150(%RSP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x310(%RSP),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x300(%RSP),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x2f0(%RSP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x560(%RSP),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x540(%RSP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x520(%RSP),%YMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x500(%RSP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x140(%RSP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x20(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x80(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x60(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
CMPQ $0,0xb0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x138(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
JE 25de40 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xb8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
CMPL $0x4,0xb0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (6.3%)
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JB 25e560 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x12b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x440(%RSP),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x400(%RSP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD %XMM4,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VBROADCASTSD %XMM2,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %ZMM19,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM20,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VBROADCASTSD %XMM28,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM31,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM29,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM1,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %YMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %ZMM12,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM22,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x220(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD 0x3c0(%RSP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x380(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x480(%RSP),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x150(%RSP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x140(%RSP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x90(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
CMPQ $0,0xf0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
VMOVAPD %ZMM2,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
JE 25de40 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 25de40 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xb90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code