OV - exec - Loop 865

	Loop Id: 865	Module: exec	Source: MultiBsplineRef.hpp:242-262	Coverage: 10.27%

0x25dfe0 MOV	0x160(%RSP),%RCX    [11]

0x25dfe8 VMOVUPD	(%R8,%R10,8),%ZMM14    [10]

0x25dfef VMOVUPD	0x40(%RCX,%R10,8),%ZMM23    [6]

0x25dff7 MOV	0x180(%RSP),%RCX    [11]

0x25dfff VMULPD	%ZMM9,%ZMM14,%ZMM2

0x25e005 VMOVUPD	(%RCX,%R10,8),%ZMM3    [5]

0x25e00c VMOVUPD	0x40(%RCX,%R10,8),%ZMM4    [5]

0x25e014 MOV	0x128(%RSP),%RCX    [11]

0x25e01c VMULPD	%ZMM9,%ZMM23,%ZMM8

0x25e022 VMOVUPD	(%RCX,%R10,8),%ZMM5    [4]

0x25e029 VMOVUPD	0x40(%RCX,%R10,8),%ZMM6    [4]

0x25e031 MOV	0x120(%RSP),%RCX    [11]

0x25e039 VFMADD231PD	%ZMM10,%ZMM3,%ZMM2

0x25e03f VFMADD231PD	%ZMM10,%ZMM4,%ZMM8

0x25e045 VMULPD	%ZMM16,%ZMM23,%ZMM10

0x25e04b VMULPD	%ZMM17,%ZMM4,%ZMM11

0x25e051 VMULPD	%ZMM17,%ZMM3,%ZMM7

0x25e057 VMOVUPD	0x40(%RCX,%R10,8),%ZMM1    [3]

0x25e05f VMOVUPD	(%RCX,%R10,8),%ZMM0    [3]

0x25e066 LEA	(%R15,%R10,8),%RCX

0x25e06a VFMADD231PD	%ZMM18,%ZMM6,%ZMM10

0x25e070 VFMADD231PD	%ZMM12,%ZMM6,%ZMM8

0x25e076 VFMADD231PD	%ZMM12,%ZMM5,%ZMM2

0x25e07c VMOVAPD	%ZMM9,%ZMM12

0x25e082 VMULPD	%ZMM16,%ZMM14,%ZMM9

0x25e088 VMULPD	%ZMM30,%ZMM14,%ZMM14

0x25e08e VFMADD231PD	%ZMM3,%ZMM20,%ZMM14

0x25e094 VMOVAPD	0x4c0(%RSP),%ZMM3    [11]

0x25e09c VFMADD231PD	%ZMM18,%ZMM5,%ZMM9

0x25e0a2 VFMADD231PD	%ZMM27,%ZMM1,%ZMM11

0x25e0a8 VFMADD231PD	%ZMM1,%ZMM13,%ZMM8

0x25e0ae VFMADD231PD	%ZMM0,%ZMM13,%ZMM2

0x25e0b4 VFMADD231PD	%ZMM27,%ZMM0,%ZMM7

0x25e0ba VFMADD231PD	%ZMM5,%ZMM24,%ZMM14

0x25e0c0 VFMADD231PD	%ZMM11,%ZMM15,%ZMM10

0x25e0c6 VMULPD	%ZMM30,%ZMM23,%ZMM11

0x25e0cc VFMADD231PD	%ZMM7,%ZMM15,%ZMM9

0x25e0d2 VFMADD231PD	%ZMM0,%ZMM15,%ZMM14

0x25e0d8 VFMADD231PD	%ZMM4,%ZMM20,%ZMM11

0x25e0de VMOVUPD	(%R15,%R10,8),%ZMM4    [9]

0x25e0e5 VFMADD231PD	%ZMM6,%ZMM24,%ZMM11

0x25e0eb VFMADD231PD	%ZMM1,%ZMM15,%ZMM11

0x25e0f1 VMOVUPD	0x40(%R15,%R10,8),%ZMM1    [9]

0x25e0f9 VFMADD231PD	%ZMM2,%ZMM3,%ZMM4

0x25e0ff VMOVUPD	%ZMM4,(%R15,%R10,8)    [9]

0x25e106 VFMADD231PD	%ZMM8,%ZMM3,%ZMM1

0x25e10c VMOVUPD	%ZMM1,0x40(%R15,%R10,8)    [9]

0x25e114 VMOVUPD	(%RDI,%RCX,1),%ZMM0    [2]

0x25e11b VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1    [2]

0x25e123 VFMADD231PD	%ZMM2,%ZMM26,%ZMM0

0x25e129 VFMADD231PD	%ZMM8,%ZMM26,%ZMM1

0x25e12f VMOVUPD	%ZMM0,(%RDI,%RCX,1)    [2]

0x25e136 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)    [2]

0x25e13e LEA	(%RCX,%RDI,1),%RCX

0x25e142 VMOVUPD	(%RDI,%RCX,1),%ZMM0    [2]

0x25e149 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1    [2]

0x25e151 VFMADD231PD	%ZMM19,%ZMM9,%ZMM0

0x25e157 VFMADD231PD	%ZMM19,%ZMM10,%ZMM1

0x25e15d VMOVUPD	%ZMM0,(%RDI,%RCX,1)    [2]

0x25e164 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)    [2]

0x25e16c LEA	(%RCX,%RDI,1),%RCX

0x25e170 VMOVUPD	(%RDI,%RCX,1),%ZMM0    [2]

0x25e177 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1    [2]

0x25e17f VFMADD231PD	%ZMM2,%ZMM25,%ZMM0

0x25e185 VFMADD231PD	%ZMM8,%ZMM25,%ZMM1

0x25e18b VMOVUPD	%ZMM0,(%RDI,%RCX,1)    [2]

0x25e192 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)    [2]

0x25e19a LEA	(%RCX,%RDI,1),%RCX

0x25e19e VMOVUPD	(%RDI,%RCX,1),%ZMM0    [2]

0x25e1a5 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM1    [2]

0x25e1ad VFMADD231PD	%ZMM21,%ZMM9,%ZMM0

0x25e1b3 VFMADD231PD	%ZMM21,%ZMM10,%ZMM1

0x25e1b9 VMOVUPD	%ZMM0,(%RDI,%RCX,1)    [2]

0x25e1c0 VMOVUPD	%ZMM1,0x40(%RDI,%RCX,1)    [2]

0x25e1c8 LEA	(%RCX,%RDI,1),%RCX

0x25e1cc VFMADD213PD	(%RDI,%RCX,1),%ZMM22,%ZMM14    [2]

0x25e1d3 VFMADD213PD	0x40(%RDI,%RCX,1),%ZMM22,%ZMM11    [2]

0x25e1db VMOVUPD	%ZMM14,(%RDI,%RCX,1)    [2]

0x25e1e2 VMOVUPD	%ZMM11,0x40(%RDI,%RCX,1)    [2]

0x25e1ea VMOVUPD	(%R14,%R10,8),%ZMM0    [8]

0x25e1f1 VMOVUPD	0x40(%R14,%R10,8),%ZMM1    [8]

0x25e1f9 VFMADD231PD	%ZMM19,%ZMM2,%ZMM0

0x25e1ff VFMADD231PD	%ZMM19,%ZMM8,%ZMM1

0x25e205 VMOVUPD	%ZMM0,(%R14,%R10,8)    [8]

0x25e20c VMOVUPD	%ZMM1,0x40(%R14,%R10,8)    [8]

0x25e214 VMOVUPD	-0x40(%RDX,%R10,8),%ZMM0    [7]

0x25e21c VMOVUPD	(%RDX,%R10,8),%ZMM1    [7]

0x25e223 VFMADD231PD	%ZMM21,%ZMM2,%ZMM0

0x25e229 VFMADD231PD	%ZMM21,%ZMM8,%ZMM1

0x25e22f VFMADD213PD	(%RBX,%R10,8),%ZMM22,%ZMM2    [12]

0x25e236 VFMADD213PD	0x40(%RBX,%R10,8),%ZMM22,%ZMM8    [12]

0x25e23e VMOVUPD	%ZMM0,-0x40(%RDX,%R10,8)    [7]

0x25e246 VMOVUPD	%ZMM1,(%RDX,%R10,8)    [7]

0x25e24d VFMADD213PD	-0x40(%RAX,%R10,8),%ZMM22,%ZMM9    [1]

0x25e255 VFMADD213PD	(%RAX,%R10,8),%ZMM22,%ZMM10    [1]

0x25e25c VMOVUPD	%ZMM2,(%RBX,%R10,8)    [12]

0x25e263 VMOVUPD	%ZMM8,0x40(%RBX,%R10,8)    [12]

0x25e26b VMOVUPD	%ZMM9,-0x40(%RAX,%R10,8)    [1]

0x25e273 VMOVUPD	%ZMM10,(%RAX,%R10,8)    [1]

0x25e27a VMOVAPD	%ZMM12,%ZMM9

0x25e280 VMOVAPD	0x380(%RSP),%ZMM12    [11]

0x25e288 VMOVAPD	0x3c0(%RSP),%ZMM10    [11]

0x25e290 ADD	$0x10,%R10

0x25e294 CMP	%R10,0xb8(%RSP)    [11]

0x25e29c JNE	25dfe0

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 242 - 262

--------------------------------------------------------------------------------

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Coverage (%)	Name	Source Location	Module
►81.96+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►7.13+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.83+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	qmcplusplus::SPOSet::evaluate_[...]	OhmmsVector.h:144	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:263	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:238	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.61+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:206	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P10, P11,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	23.00
CQA cycles if no scalar integer	23.00
CQA cycles if FP arith vectorized	23.00
CQA cycles if fully vectorized	23.00
Front-end cycles	13.00
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	14.00
P10 cycles	23.00
P11 cycles	23.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	104.00
Nb loads	36.00
Nb stores	20.00
Nb stack references	8.00
FLOP/cycle	29.22
Nb FLOP add-sub	0.00
Nb FLOP mul	64.00
Nb FLOP fma	304.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	143.65
Bytes prefetched	0.00
Bytes loaded	2024.00
Bytes stored	1280.00
Stride 0	1.00
Stride 1	8.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P10, P11,
Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	23.00
CQA cycles if no scalar integer	23.00
CQA cycles if FP arith vectorized	23.00
CQA cycles if fully vectorized	23.00
Front-end cycles	13.00
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	14.00
P10 cycles	23.00
P11 cycles	23.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	104.00
Nb loads	36.00
Nb stores	20.00
Nb stack references	8.00
FLOP/cycle	29.22
Nb FLOP add-sub	0.00
Nb FLOP mul	64.00
Nb FLOP fma	304.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	143.65
Bytes prefetched	0.00
Bytes loaded	2024.00
Bytes stored	1280.00
Stride 0	1.00
Stride 1	8.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242-262.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 14.00 cycles (1.64x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 304 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 42 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 42 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:244
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:244
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:245
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:245
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:246
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:246
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:247
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:247
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:260
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:260
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:262
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:262
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:261
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:261

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

46 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 672 FP arithmetical operations:

304: addition or subtraction (all inside FMA instructions)
368: multiply (304 inside FMA instructions)

The binary loop is loading 2024 bytes (253 double precision FP elements). The binary loop is storing 1280 bytes (160 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	104
loop length	706
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	29
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	14.00	14.00	14.00	14.00	23.00	23.00	0.00	0.00	10.00	10.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	14.00	14.00	14.00	14.00	23.00	23.00	0.00	0.00	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.00
Dispatch	23.00
Data deps.	1.00
Overall L1	23.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

34% of peak load performance is reached (88.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (55.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 25dfe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x160(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVUPD (%R8,%R10,8),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x180(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMULPD %ZMM9,%ZMM14,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R10,8),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x128(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMULPD %ZMM9,%ZMM23,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R10,8),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x120(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD231PD %ZMM10,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM4,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM23,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM4,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R10,8),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
LEA (%R15,%R10,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD231PD %ZMM18,%ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMULPD %ZMM16,%ZMM14,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM3,%ZMM20,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVAPD 0x4c0(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM5,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM1,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM13,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM13,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM0,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM5,%ZMM24,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM15,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM23,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM20,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD (%R15,%R10,8),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM24,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM15,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD 0x40(%R15,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%R15,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x40(%R15,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM26,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM26,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM9,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM25,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM25,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM9,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RDI,%RCX,1),%ZMM22,%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RDI,%RCX,1),%ZMM22,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM11,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R14,%R10,8),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R14,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%R14,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%R14,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD -0x40(%RDX,%R10,8),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RDX,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD (%RBX,%R10,8),%ZMM22,%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RBX,%R10,8),%ZMM22,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,-0x40(%RDX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD213PD -0x40(%RAX,%R10,8),%ZMM22,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD (%RAX,%R10,8),%ZMM22,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,(%RBX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM8,0x40(%RBX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM9,-0x40(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM10,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVAPD %ZMM12,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x380(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x3c0(%RSP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,0xb8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 25dfe0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xd30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	void miniqmcreference::MultiBsplineEvalRef::evaluate_vgh(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, double, double, unsigned long)
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 304 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 42 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 42 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:244
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:244
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:245
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:245
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:246
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:246
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:247
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:247
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:251
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:253
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:254
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:255
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:260
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:260
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:262
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:262
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:261
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:261

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

46 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 672 FP arithmetical operations:

304: addition or subtraction (all inside FMA instructions)
368: multiply (304 inside FMA instructions)

The binary loop is loading 2024 bytes (253 double precision FP elements). The binary loop is storing 1280 bytes (160 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	104
loop length	706
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	29
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	14.00	14.00	14.00	14.00	23.00	23.00	0.00	0.00	10.00	10.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	14.00	14.00	14.00	14.00	23.00	23.00	0.00	0.00	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.00
Dispatch	23.00
Data deps.	1.00
Overall L1	23.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

34% of peak load performance is reached (88.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (55.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 25dfe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x160(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVUPD (%R8,%R10,8),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x180(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMULPD %ZMM9,%ZMM14,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R10,8),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x128(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMULPD %ZMM9,%ZMM23,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R10,8),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x120(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD231PD %ZMM10,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM10,%ZMM4,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM16,%ZMM23,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM4,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM17,%ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RCX,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RCX,%R10,8),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
LEA (%R15,%R10,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD231PD %ZMM18,%ZMM6,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM6,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM9,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMULPD %ZMM16,%ZMM14,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM3,%ZMM20,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVAPD 0x4c0(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM18,%ZMM5,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM1,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM13,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM13,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM0,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM5,%ZMM24,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM15,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM30,%ZMM23,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM7,%ZMM15,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM0,%ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM4,%ZMM20,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD (%R15,%R10,8),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM6,%ZMM24,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM1,%ZMM15,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD 0x40(%R15,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%R15,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM1,0x40(%R15,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM26,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM26,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM9,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM2,%ZMM25,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM8,%ZMM25,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM9,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM10,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
LEA (%RCX,%RDI,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RDI,%RCX,1),%ZMM22,%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RDI,%RCX,1),%ZMM22,%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM14,(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM11,0x40(%RDI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD (%R14,%R10,8),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R14,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM19,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,(%R14,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%R14,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD -0x40(%RDX,%R10,8),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%RDX,%R10,8),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM21,%ZMM8,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD (%RBX,%R10,8),%ZMM22,%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD 0x40(%RBX,%R10,8),%ZMM22,%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM0,-0x40(%RDX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VFMADD213PD -0x40(%RAX,%R10,8),%ZMM22,%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VFMADD213PD (%RAX,%R10,8),%ZMM22,%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,(%RBX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM8,0x40(%RBX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM9,-0x40(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM10,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVAPD %ZMM12,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD 0x380(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x3c0(%RSP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,0xb8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 25dfe0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xd30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code