OV - exec - Loop 327

	Loop Id: 327	Module: exec	Source: BsplineFunctor.h:246-260 [...]	Coverage: 0.04%

0x23fe20 VMULPD	(%RSI,%RDX,1),%YMM17,%YMM11    [2]

0x23fe27 VMULPD	0x20(%RSI,%RDX,1),%YMM17,%YMM13    [2]

0x23fe2f VMOVAPD	%YMM3,%YMM20

0x23fe35 ADD	$0x40,%RDX

0x23fe39 VCVTTPD2DQ	%YMM11,%XMM1

0x23fe3e VCVTTPD2DQ	%YMM13,%XMM0

0x23fe43 VROUNDPD	$0xb,%YMM11,%YMM12

0x23fe49 VROUNDPD	$0xb,%YMM13,%YMM14

0x23fe4f VPMOVSXDQ	%XMM1,%YMM4

0x23fe54 VPMOVSXDQ	%XMM0,%YMM7

0x23fe59 VSUBPD	%YMM12,%YMM11,%YMM12

0x23fe5e VSUBPD	%YMM14,%YMM13,%YMM11

0x23fe63 VPEXTRQ	$0x1,%XMM4,%RDI

0x23fe69 VMOVQ	%XMM4,%R15

0x23fe6e VEXTRACTI128	$0x1,%YMM4,%XMM4

0x23fe74 VMOVQ	%XMM7,%RCX

0x23fe79 VPEXTRQ	$0x1,%XMM7,%R14

0x23fe7f VMOVQ	%XMM4,%R13

0x23fe84 VPEXTRQ	$0x1,%XMM4,%R8

0x23fe8a VEXTRACTI128	$0x1,%YMM7,%XMM4

0x23fe90 VMOVSD	(%R11,%R15,8),%XMM7    [1]

0x23fe96 VMOVSD	(%R11,%RCX,8),%XMM8    [1]

0x23fe9c VMULPD	%YMM12,%YMM12,%YMM16

0x23fea2 VFMADD213PD	%YMM21,%YMM11,%YMM20

0x23fea8 VMULPD	%YMM11,%YMM11,%YMM15

0x23fead VMOVQ	%XMM4,%R9

0x23feb2 VPEXTRQ	$0x1,%XMM4,%R10

0x23feb8 VMOVSD	(%R11,%R13,8),%XMM4    [1]

0x23febe VMOVHPD	(%R11,%RDI,8),%XMM7,%XMM7    [1]

0x23fec4 VMOVHPD	(%R11,%R14,8),%XMM8,%XMM8    [1]

0x23feca VMOVHPD	(%R11,%R8,8),%XMM4,%XMM4    [1]

0x23fed0 VMULPD	%YMM12,%YMM16,%YMM14

0x23fed6 VMULPD	%YMM11,%YMM15,%YMM13

0x23fedb VFMADD231PD	%YMM19,%YMM15,%YMM20

0x23fee1 VFMADD231PD	%YMM18,%YMM13,%YMM20

0x23fee7 VINSERTF128	$0x1,%XMM4,%YMM7,%YMM4

0x23feed VMOVSD	(%R11,%R9,8),%XMM7    [1]

0x23fef3 VMOVHPD	(%R11,%R10,8),%XMM7,%XMM7    [1]

0x23fef9 VINSERTF128	$0x1,%XMM7,%YMM8,%YMM7

0x23feff VMOVAPD	%YMM3,%YMM8

0x23ff03 VFMADD213PD	%YMM21,%YMM12,%YMM8

0x23ff09 VFMADD213PD	%YMM5,%YMM7,%YMM20

0x23ff0f VMOVAPD	%YMM24,%YMM7

0x23ff15 VFMADD213PD	%YMM25,%YMM11,%YMM7

0x23ff1b VFMADD231PD	%YMM19,%YMM16,%YMM8

0x23ff21 VFMADD231PD	%YMM23,%YMM15,%YMM7

0x23ff27 VFMADD231PD	%YMM18,%YMM14,%YMM8

0x23ff2d VFMADD231PD	%YMM22,%YMM13,%YMM7

0x23ff33 VFMADD213PD	%YMM2,%YMM4,%YMM8

0x23ff38 VPCMPEQD	%XMM4,%XMM4,%XMM4

0x23ff3c VPSUBD	%XMM4,%XMM1,%XMM2

0x23ff40 VPSUBD	%XMM4,%XMM0,%XMM4

0x23ff44 VPMOVSXDQ	%XMM2,%YMM2

0x23ff49 VPMOVSXDQ	%XMM4,%YMM4

0x23ff4e VMOVQ	%XMM2,%RCX

0x23ff53 VPEXTRQ	$0x1,%XMM2,%RDI

0x23ff59 VEXTRACTI128	$0x1,%YMM2,%XMM2

0x23ff5f VMOVQ	%XMM4,%R10

0x23ff64 VPEXTRQ	$0x1,%XMM4,%R14

0x23ff6a VPEXTRQ	$0x1,%XMM2,%R8

0x23ff70 VMOVQ	%XMM2,%R9

0x23ff75 VEXTRACTI128	$0x1,%YMM4,%XMM2

0x23ff7b VMOVSD	(%R11,%RCX,8),%XMM4    [1]

0x23ff81 VMOVSD	(%R11,%R10,8),%XMM5    [1]

0x23ff87 VMOVQ	%XMM2,%R15

0x23ff8c VPEXTRQ	$0x1,%XMM2,%R13

0x23ff92 VMOVSD	(%R11,%R9,8),%XMM2    [1]

0x23ff98 VMOVHPD	(%R11,%RDI,8),%XMM4,%XMM4    [1]

0x23ff9e VMOVHPD	(%R11,%R14,8),%XMM5,%XMM5    [1]

0x23ffa4 VMOVHPD	(%R11,%R8,8),%XMM2,%XMM2    [1]

0x23ffaa VINSERTF128	$0x1,%XMM2,%YMM4,%YMM2

0x23ffb0 VMOVSD	(%R11,%R15,8),%XMM4    [1]

0x23ffb6 VMOVHPD	(%R11,%R13,8),%XMM4,%XMM4    [1]

0x23ffbc VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

0x23ffc2 VMOVAPD	%YMM24,%YMM5

0x23ffc8 VFMADD213PD	%YMM25,%YMM12,%YMM5

0x23ffce VFMADD213PD	%YMM20,%YMM4,%YMM7

0x23ffd4 VMOVAPD	%YMM28,%YMM20

0x23ffda VFMADD213PD	%YMM29,%YMM11,%YMM20

0x23ffe0 VFMADD213PD	%YMM10,%YMM9,%YMM11

0x23ffe5 VFMADD231PD	%YMM23,%YMM16,%YMM5

0x23ffeb VFMADD231PD	%YMM27,%YMM15,%YMM20

0x23fff1 VFMADD231PD	%YMM15,%YMM31,%YMM11

0x23fff7 VFMADD231PD	%YMM22,%YMM14,%YMM5

0x23fffd VFMADD231PD	%YMM26,%YMM13,%YMM20

0x240003 VFMADD231PD	%YMM13,%YMM30,%YMM11

0x240009 VFMADD213PD	%YMM8,%YMM2,%YMM5

0x24000e VPBROADCASTD	-0x3bf47(%RIP),%XMM2    [3]

0x240017 VPADDD	%XMM2,%XMM1,%XMM4

0x24001b VPADDD	%XMM2,%XMM0,%XMM2

0x24001f VPMOVSXDQ	%XMM4,%YMM4

0x240024 VPMOVSXDQ	%XMM2,%YMM2

0x240029 VMOVQ	%XMM4,%RCX

0x24002e VPEXTRQ	$0x1,%XMM4,%RDI

0x240034 VEXTRACTI128	$0x1,%YMM4,%XMM4

0x24003a VMOVQ	%XMM2,%R14

0x24003f VPEXTRQ	$0x1,%XMM2,%R10

0x240045 VEXTRACTI128	$0x1,%YMM2,%XMM2

0x24004b VMOVQ	%XMM4,%R8

0x240050 VPEXTRQ	$0x1,%XMM4,%R9

0x240056 VMOVSD	(%R11,%RCX,8),%XMM4    [1]

0x24005c VMOVQ	%XMM2,%R15

0x240061 VPEXTRQ	$0x1,%XMM2,%R13

0x240067 VMOVSD	(%R11,%R14,8),%XMM8    [1]

0x24006d VMOVSD	(%R11,%R8,8),%XMM2    [1]

0x240073 VMOVHPD	(%R11,%RDI,8),%XMM4,%XMM4    [1]

0x240079 VMOVHPD	(%R11,%R10,8),%XMM8,%XMM8    [1]

0x24007f VMOVHPD	(%R11,%R9,8),%XMM2,%XMM2    [1]

0x240085 VINSERTF128	$0x1,%XMM2,%YMM4,%YMM2

0x24008b VMOVSD	(%R11,%R15,8),%XMM4    [1]

0x240091 VMOVHPD	(%R11,%R13,8),%XMM4,%XMM4    [1]

0x240097 VINSERTF128	$0x1,%XMM4,%YMM8,%YMM4

0x24009d VMOVAPD	%YMM28,%YMM8

0x2400a3 VFMADD213PD	%YMM29,%YMM12,%YMM8

0x2400a9 VFMADD213PD	%YMM10,%YMM9,%YMM12

0x2400ae VFMADD213PD	%YMM7,%YMM4,%YMM20

0x2400b4 VFMADD231PD	%YMM27,%YMM16,%YMM8

0x2400ba VFMADD231PD	%YMM16,%YMM31,%YMM12

0x2400c0 VFMADD231PD	%YMM26,%YMM14,%YMM8

0x2400c6 VFMADD231PD	%YMM14,%YMM30,%YMM12

0x2400cc VFMADD213PD	%YMM5,%YMM2,%YMM8

0x2400d1 VPBROADCASTD	-0x3c006(%RIP),%XMM2    [3]

0x2400da VMOVAPD	%YMM11,%YMM5

0x2400de VPADDD	%XMM2,%XMM1,%XMM1

0x2400e2 VPADDD	%XMM2,%XMM0,%XMM0

0x2400e6 VPMOVSXDQ	%XMM1,%YMM1

0x2400eb VPMOVSXDQ	%XMM0,%YMM0

0x2400f0 VMOVQ	%XMM1,%RCX

0x2400f5 VPEXTRQ	$0x1,%XMM1,%RDI

0x2400fb VEXTRACTI128	$0x1,%YMM1,%XMM1

0x240101 VMOVQ	%XMM0,%R10

0x240106 VPEXTRQ	$0x1,%XMM0,%R14

0x24010c VEXTRACTI128	$0x1,%YMM0,%XMM0

0x240112 VMOVQ	%XMM1,%R9

0x240117 VPEXTRQ	$0x1,%XMM1,%R8

0x24011d VMOVSD	(%R11,%RCX,8),%XMM1    [1]

0x240123 VMOVQ	%XMM0,%R15

0x240128 VPEXTRQ	$0x1,%XMM0,%R13

0x24012e VMOVSD	(%R11,%R10,8),%XMM2    [1]

0x240134 VMOVSD	(%R11,%R9,8),%XMM0    [1]

0x24013a VMOVHPD	(%R11,%RDI,8),%XMM1,%XMM1    [1]

0x240140 VMOVHPD	(%R11,%R14,8),%XMM2,%XMM2    [1]

0x240146 VMOVHPD	(%R11,%R8,8),%XMM0,%XMM0    [1]

0x24014c VINSERTF128	$0x1,%XMM0,%YMM1,%YMM0

0x240152 VMOVSD	(%R11,%R15,8),%XMM1    [1]

0x240158 VMOVHPD	(%R11,%R13,8),%XMM1,%XMM1    [1]

0x24015e VINSERTF128	$0x1,%XMM1,%YMM2,%YMM1

0x240164 VMOVAPD	%YMM12,%YMM2

0x240168 VFMADD213PD	%YMM8,%YMM0,%YMM2

0x24016d VFMADD213PD	%YMM20,%YMM1,%YMM5

0x240173 CMP	%RDX,%R12

0x240176 JNE	23fe20

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1064 - 1064

--------------------------------------------------------------------------------

1064: 	return *(this->_M_impl._M_start + __n);

Coverage (%)	Name	Source Location	Module
►96.76+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.51+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	2.77
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P10, P11, P12, P13,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260,stl_vector.h:1064-1064
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.75
CQA cycles if no scalar integer	27.75
CQA cycles if FP arith vectorized	21.75
CQA cycles if fully vectorized	10.00
Front-end cycles	21.13
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	27.75
P11 cycles	27.75
P12 cycles	27.75
P13 cycles	27.75
P14 cycles	16.00
P15 cycles	16.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	152.00
Nb uops	169.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.38
Nb FLOP add-sub	8.00
Nb FLOP mul	24.00
Nb FLOP fma	128.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.82
Bytes prefetched	0.00
Bytes loaded	328.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	55.70
Vectorization ratio load	5.56
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	52.11
Vector-efficiency ratio all	28.10
Vector-efficiency ratio load	14.24
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.06

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	2.77
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P10, P11, P12, P13,
Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	BsplineFunctor.h:246-260,stl_vector.h:1064-1064
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.75
CQA cycles if no scalar integer	27.75
CQA cycles if FP arith vectorized	21.75
CQA cycles if fully vectorized	10.00
Front-end cycles	21.13
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	27.75
P11 cycles	27.75
P12 cycles	27.75
P13 cycles	27.75
P14 cycles	16.00
P15 cycles	16.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	152.00
Nb uops	169.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.38
Nb FLOP add-sub	8.00
Nb FLOP mul	24.00
Nb FLOP fma	128.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.82
Bytes prefetched	0.00
Bytes loaded	328.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	55.70
Vectorization ratio load	5.56
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	52.11
Vector-efficiency ratio all	28.10
Vector-efficiency ratio load	14.24
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.06

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions).

Details

55% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
52% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 27.75 to 21.13 cycles (1.31x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 128 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
VPEXTRQ: 16 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (128 inside FMA instructions)
152: multiply (128 inside FMA instructions)

The binary loop is loading 328 bytes (41 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.88 FP operations per loaded or stored byte.

General properties

nb instructions	152
nb uops	169
loop length	860
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	31
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.13 cycles
front end	21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	27.75	27.75	27.75	27.75	16.00	16.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	27.75	27.75	27.75	27.75	16.00	16.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	21.13
Dispatch	27.75
Data deps.	16.00
Overall L1	27.75

Vectorization ratios

INT

all	40%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	65%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	55%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

Vector efficiency ratios

INT

all	17%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	34%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	28%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	31%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.75 cycles. At this rate:

4% of peak load performance is reached (11.82 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23fe20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD (%RSI,%RDX,1),%YMM17,%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%RSI,%RDX,1),%YMM17,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTTPD2DQ %YMM11,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67	vect (50.0%)
VCVTTPD2DQ %YMM13,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67	vect (50.0%)
VROUNDPD $0xb,%YMM11,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM1,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM0,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VSUBPD %YMM12,%YMM11,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM14,%YMM13,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPEXTRQ $0x1,%XMM4,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%RCX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULPD %YMM12,%YMM12,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM21,%YMM11,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM11,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R13,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMULPD %YMM12,%YMM16,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM11,%YMM15,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM15,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM18,%YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM4,%YMM7,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R9,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R10,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM7,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM3,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM21,%YMM12,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM7,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM25,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM15,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM18,%YMM14,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM2,%YMM4,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPCMPEQD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSUBD %XMM4,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSUBD %XMM4,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVQ %XMM2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM2,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%RCX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%R10,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM2,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R9,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM24,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM25,%YMM12,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM28,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM29,%YMM11,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM10,%YMM9,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM16,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM15,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM31,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM14,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM30,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM8,%YMM2,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPBROADCASTD -0x3bf47(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
VPADDD %XMM2,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVQ %XMM4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM2,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RCX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM2,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R14,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%R8,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R10,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R9,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM8,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM28,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM29,%YMM12,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM10,%YMM9,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM7,%YMM4,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM16,%YMM31,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM14,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM30,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM2,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPBROADCASTD -0x3c006(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
VMOVAPD %YMM11,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPADDD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVQ %XMM1,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM1,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RCX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM0,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R10,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%R9,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM12,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM8,%YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM1,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
CMP %RDX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 23fe20 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions).

Details

55% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
52% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 27.75 to 21.13 cycles (1.31x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 128 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
VPEXTRQ: 16 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:256
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:257
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:258
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:259

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:250

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (128 inside FMA instructions)
152: multiply (128 inside FMA instructions)

The binary loop is loading 328 bytes (41 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.88 FP operations per loaded or stored byte.

General properties

nb instructions	152
nb uops	169
loop length	860
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	31
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.13 cycles
front end	21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	27.75	27.75	27.75	27.75	16.00	16.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	27.75	27.75	27.75	27.75	16.00	16.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	21.13
Dispatch	27.75
Data deps.	16.00
Overall L1	27.75

Vectorization ratios

INT

all	40%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	65%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	55%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

Vector efficiency ratios

INT

all	17%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	34%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	28%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	31%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.75 cycles. At this rate:

4% of peak load performance is reached (11.82 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23fe20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMULPD (%RSI,%RDX,1),%YMM17,%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD 0x20(%RSI,%RDX,1),%YMM17,%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTTPD2DQ %YMM11,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67	vect (50.0%)
VCVTTPD2DQ %YMM13,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67	vect (50.0%)
VROUNDPD $0xb,%YMM11,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VROUNDPD $0xb,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM1,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM0,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VSUBPD %YMM12,%YMM11,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM14,%YMM13,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPEXTRQ $0x1,%XMM4,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM7,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%RCX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULPD %YMM12,%YMM12,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM21,%YMM11,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM11,%YMM11,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R13,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMULPD %YMM12,%YMM16,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM11,%YMM15,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM15,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM18,%YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM4,%YMM7,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R9,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R10,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM7,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM3,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM21,%YMM12,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM7,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM25,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM19,%YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM15,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM18,%YMM14,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM2,%YMM4,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPCMPEQD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSUBD %XMM4,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSUBD %XMM4,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVQ %XMM2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM2,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%RCX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%R10,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM2,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R9,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM24,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM25,%YMM12,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD %YMM28,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM29,%YMM11,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM10,%YMM9,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM23,%YMM16,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM15,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM15,%YMM31,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM22,%YMM14,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM13,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM30,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM8,%YMM2,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPBROADCASTD -0x3bf47(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
VPADDD %XMM2,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVQ %XMM4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM2,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RCX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM2,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R14,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%R8,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R10,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R9,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM8,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM28,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM29,%YMM12,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM10,%YMM9,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM7,%YMM4,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM27,%YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM16,%YMM31,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM26,%YMM14,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM14,%YMM30,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM5,%YMM2,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPBROADCASTD -0x3c006(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
VMOVAPD %YMM11,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPADDD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVQ %XMM1,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM1,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RCX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM0,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%R10,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11,%R9,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%R15,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM12,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VFMADD213PD %YMM8,%YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM1,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
CMP %RDX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 23fe20 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code