OV - exec - Loop 262

	Loop Id: 262	Module: exec	Source: BsplineFunctor.h:291-297	Coverage: 0.21%

0x23aaa0 VMOVUPD	(%RDX,%R15,8),%ZMM8    [3]

0x23aaa7 VPADDQ	%ZMM2,%ZMM5,%ZMM9

0x23aaad MOVSXD	%R11D,%R11

0x23aab0 VPADDQ	%ZMM6,%ZMM5,%ZMM5

0x23aab6 VPCMPNEQQ	%ZMM3,%ZMM9,%K1

0x23aabd VCMPPD	$0x1,%ZMM1,%ZMM8,%K1{%K1}

0x23aac4 KMOVB	%K1,%R12D

0x23aac8 VPCOMPRESSD	%YMM4,(%RAX,%R11,4){%K1}    [2]

0x23aacf VCOMPRESSPD	%ZMM8,(%R10,%R11,8){%K1}    [1]

0x23aad6 VPADDD	%YMM7,%YMM4,%YMM4

0x23aada POPCNT	%R12D,%R12D

0x23aadf KORTESTB	%K1,%K1

0x23aae3 CMOVE	%R14D,%R12D

0x23aae7 ADD	$0x8,%R15

0x23aaeb ADD	%R12D,%R11D

0x23aaee CMP	%R15,%RCX

0x23aaf1 JNE	23aaa0

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 291 - 297

--------------------------------------------------------------------------------

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

Coverage (%)	Name	Source Location	Module
►60.41+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►28.67+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►6.25+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:422	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.85+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:274	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.16
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:291-297
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.75
CQA cycles if no scalar integer	23.00
CQA cycles if FP arith vectorized	23.75
CQA cycles if fully vectorized	21.04
Front-end cycles	23.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	3.25
P11 cycles	3.25
P12 cycles	3.25
P13 cycles	3.25
P14 cycles	11.00
P15 cycles	11.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	190.00
Nb loads	1.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.74
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	71.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	83.33
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.13

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.16
Bottlenecks	micro-operation queue,
Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source	BsplineFunctor.h:291-297
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.75
CQA cycles if no scalar integer	23.00
CQA cycles if FP arith vectorized	23.75
CQA cycles if fully vectorized	21.04
Front-end cycles	23.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	3.25
P11 cycles	3.25
P12 cycles	3.25
P13 cycles	3.25
P14 cycles	11.00
P15 cycles	11.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	190.00
Nb loads	1.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.74
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	71.25
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	83.33
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:291-297
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291-297.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 71% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 23.75 to 21.04 cycles (1.13x speedup).

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:294
VCOMPRESSPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:297
VPCOMPRESSD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:296

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

General properties

nb instructions	17
nb uops	190
loop length	83
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	7
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	23.75 cycles
front end	23.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.25	3.25	11.00	11.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.25	3.25	11.00	11.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	23.75
Dispatch	11.00
Data deps.	2.00
Overall L1	23.75

Vectorization ratios

INT

all	71%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	58%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	71%
load	100%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.75 cycles. At this rate:

1% of peak load performance is reached (2.69 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.75 to 11.00 cycles (2.16x speedup).

ASM code

In the binary file, the address of the loop is: 23aaa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%RDX,%R15,8),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
MOVSXD %R11D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %ZMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPCMPNEQQ %ZMM3,%ZMM9,%K1																				vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM8,%K1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
KMOVB %K1,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
VPCOMPRESSD %YMM4,(%RAX,%R11,4){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	38-54	54	vect (50.0%)
VCOMPRESSPD %ZMM8,(%R10,%R11,8){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	8	54	vect (100.0%)
VPADDD %YMM7,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
POPCNT %R12D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
KORTESTB %K1,%K1	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
CMOVE %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 23aaa0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const
Source file and lines	BsplineFunctor.h:291-297
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291-297.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KORTESTB: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:294
VCOMPRESSPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:297
VPCOMPRESSD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:296

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:293

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	17
nb uops	190
loop length	83
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	7
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	23.75 cycles
front end	23.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.25	3.25	11.00	11.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.75	0.75	0.75	0.75	3.25	3.25	3.25	3.25	11.00	11.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	23.75
Dispatch	11.00
Data deps.	2.00
Overall L1	23.75

Vectorization ratios

INT

all	71%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	58%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	71%
load	100%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.75 cycles. At this rate:

1% of peak load performance is reached (2.69 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 23aaa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%RDX,%R15,8),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
MOVSXD %R11D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %ZMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPCMPNEQQ %ZMM3,%ZMM9,%K1																				vect (100.0%)
VCMPPD $0x1,%ZMM1,%ZMM8,%K1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
KMOVB %K1,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1	N/A
VPCOMPRESSD %YMM4,(%RAX,%R11,4){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	38-54	54	vect (50.0%)
VCOMPRESSPD %ZMM8,(%R10,%R11,8){%K1}	88	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	1.25	1.25	1.25	5	5	8	54	vect (100.0%)
VPADDD %YMM7,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
POPCNT %R12D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
KORTESTB %K1,%K1	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
CMOVE %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 23aaa0 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code