OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 64ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:221-257 [...]	Coverage (incl. loops): 0.85% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 221 - 257

--------------------------------------------------------------------------------

221:   {

[...]

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x28ae50 PUSH	%RBP

0x28ae51 MOV	%RSP,%RBP

0x28ae54 PUSH	%R15

0x28ae56 PUSH	%R14

0x28ae58 PUSH	%R13

0x28ae5a PUSH	%R12

0x28ae5c PUSH	%RBX

0x28ae5d MOV	0x10(%RBP),%EAX

0x28ae60 MOV	%EAX,%R15D

0x28ae63 SUB	%R9D,%R15D

0x28ae66 JLE	28b340

0x28ae6c VMOVUPD	(%RSI),%XMM0

0x28ae70 VMOVSD	0x10(%RSI),%XMM1

0x28ae75 MOV	0x8(%RDX),%RSI

0x28ae79 MOV	0x18(%RDX),%RDX

0x28ae7d MOV	0x8(%R8),%R11

0x28ae81 MOV	0x18(%R8),%R8

0x28ae85 XOR	%R14D,%R14D

0x28ae88 LEA	(%RDX,%RSI,8),%R10

0x28ae8c SAL	$0x4,%RSI

0x28ae90 LEA	(%R8,%R11,8),%RBX

0x28ae94 SAL	$0x4,%R11

0x28ae98 ADD	%RDX,%RSI

0x28ae9b ADD	%R8,%R11

0x28ae9e CMP	$0x4,%R15D

0x28aea2 JB	28b1db

0x28aea8 LEA	-0x1(%RAX),%R12D

0x28aeac CMP	%R9D,%R12D

0x28aeaf JL	28b1db

0x28aeb5 XOR	%R14D,%R14D

0x28aeb8 CMP	$0x8,%R15D

0x28aebc JB	28b06a

0x28aec2 VBROADCASTSD	-0x86d4c(%RIP),%ZMM3

0x28aecc VPBROADCASTQ	-0x86d26(%RIP),%ZMM5

0x28aed6 VPBROADCASTQ	-0x86db8(%RIP),%ZMM6

0x28aee0 VBROADCASTSD	%XMM0,%ZMM2

0x28aee6 VBROADCASTSD	%XMM1,%ZMM4

0x28aeec MOV	%R15D,%R14D

0x28aeef AND	$-0x8,%R14D

0x28aef3 MOV	%R9D,%R13D

0x28aef6 MOV	%R14D,%R12D

0x28aef9 VPERMPD	%ZMM0,%ZMM3,%ZMM3

0x28aeff NOP

(1321) 0x28af00 MOVSXD	%R13D,%R13

(1321) 0x28af03 VMOVDQA64	%ZMM6,%ZMM12

(1321) 0x28af09 VMOVUPD	(%RDX,%R13,8),%ZMM7

(1321) 0x28af10 VMOVUPD	(%R10,%R13,8),%ZMM8

(1321) 0x28af17 VMOVUPD	(%RSI,%R13,8),%ZMM9

(1321) 0x28af1e VSUBPD	%ZMM2,%ZMM7,%ZMM7

(1321) 0x28af24 VMULPD	0x48(%RDI){1to8},%ZMM7,%ZMM10

(1321) 0x28af2b VMULPD	0x60(%RDI){1to8},%ZMM7,%ZMM11

(1321) 0x28af32 VSUBPD	%ZMM3,%ZMM8,%ZMM8

(1321) 0x28af38 VMULPD	0x78(%RDI){1to8},%ZMM7,%ZMM7

(1321) 0x28af3f VSUBPD	%ZMM4,%ZMM9,%ZMM9

(1321) 0x28af45 VFMADD231PD	0x50(%RDI){1to8},%ZMM8,%ZMM10

(1321) 0x28af4c VFMADD231PD	0x68(%RDI){1to8},%ZMM8,%ZMM11

(1321) 0x28af53 VFMADD231PD	0x80(%RDI){1to8},%ZMM8,%ZMM7

(1321) 0x28af5a VMOVDQA64	%ZMM6,%ZMM8

(1321) 0x28af60 VFMADD231PD	0x58(%RDI){1to8},%ZMM9,%ZMM10

(1321) 0x28af67 VFMADD231PD	0x70(%RDI){1to8},%ZMM9,%ZMM11

(1321) 0x28af6e VFMADD231PD	0x88(%RDI){1to8},%ZMM9,%ZMM7

(1321) 0x28af75 VMOVDQA64	%ZMM6,%ZMM9

(1321) 0x28af7b VPTERNLOGQ	$-0x8,%ZMM5,%ZMM10,%ZMM8

(1321) 0x28af82 VPTERNLOGQ	$-0x8,%ZMM5,%ZMM11,%ZMM9

(1321) 0x28af89 VPTERNLOGQ	$-0x8,%ZMM5,%ZMM7,%ZMM12

(1321) 0x28af90 VADDPD	%ZMM8,%ZMM10,%ZMM8

(1321) 0x28af96 VADDPD	%ZMM9,%ZMM11,%ZMM9

(1321) 0x28af9c VRNDSCALEPD	$0xb,%ZMM8,%ZMM8

(1321) 0x28afa3 VRNDSCALEPD	$0xb,%ZMM9,%ZMM9

(1321) 0x28afaa VSUBPD	%ZMM8,%ZMM10,%ZMM8

(1321) 0x28afb0 VSUBPD	%ZMM9,%ZMM11,%ZMM9

(1321) 0x28afb6 VMULPD	(%RDI){1to8},%ZMM8,%ZMM11

(1321) 0x28afbc VADDPD	%ZMM12,%ZMM7,%ZMM10

(1321) 0x28afc2 VFMADD231PD	0x8(%RDI){1to8},%ZMM9,%ZMM11

(1321) 0x28afc9 VRNDSCALEPD	$0xb,%ZMM10,%ZMM10

(1321) 0x28afd0 VSUBPD	%ZMM10,%ZMM7,%ZMM7

(1321) 0x28afd6 VFMADD231PD	0x10(%RDI){1to8},%ZMM7,%ZMM11

(1321) 0x28afdd VMOVUPD	%ZMM11,(%R8,%R13,8)

(1321) 0x28afe4 VMULPD	0x18(%RDI){1to8},%ZMM8,%ZMM10

(1321) 0x28afeb VFMADD231PD	0x20(%RDI){1to8},%ZMM9,%ZMM10

(1321) 0x28aff2 VFMADD231PD	0x28(%RDI){1to8},%ZMM7,%ZMM10

(1321) 0x28aff9 VMOVUPD	%ZMM10,(%RBX,%R13,8)

(1321) 0x28b000 VMULPD	0x30(%RDI){1to8},%ZMM8,%ZMM8

(1321) 0x28b007 VFMADD231PD	0x38(%RDI){1to8},%ZMM9,%ZMM8

(1321) 0x28b00e VFMADD231PD	0x40(%RDI){1to8},%ZMM7,%ZMM8

(1321) 0x28b015 VMOVUPD	%ZMM8,(%R11,%R13,8)

(1321) 0x28b01c VMOVUPD	(%R8,%R13,8),%ZMM7

(1321) 0x28b023 VMOVUPD	(%RBX,%R13,8),%ZMM9

(1321) 0x28b02a VMULPD	%ZMM7,%ZMM7,%ZMM7

(1321) 0x28b030 VFMADD231PD	%ZMM8,%ZMM8,%ZMM7

(1321) 0x28b036 VFMADD231PD	%ZMM9,%ZMM9,%ZMM7

(1321) 0x28b03c VSQRTPD	%ZMM7,%ZMM7

(1321) 0x28b042 VMOVUPD	%ZMM7,(%RCX,%R13,8)

(1321) 0x28b049 ADD	$0x8,%R13D

(1321) 0x28b04d ADD	$-0x8,%R12D

(1321) 0x28b051 JNE	28af00

0x28b057 CMP	%R14D,%R15D

0x28b05a JE	28b340

0x28b060 TEST	$0x4,%R15B

0x28b064 JE	28b1db

0x28b06a VPBROADCASTQ	-0x86ec3(%RIP),%YMM5

0x28b073 VPBROADCASTQ	-0x86f54(%RIP),%YMM6

0x28b07c MOV	%R14D,%R12D

0x28b07f MOV	%R15D,%R14D

0x28b082 AND	$-0x4,%R14D

0x28b086 VBROADCASTSD	%XMM0,%YMM2

0x28b08b VPERMPD	$0x55,%YMM0,%YMM3

0x28b091 VBROADCASTSD	%XMM1,%YMM4

0x28b096 LEA	(%R12,%R9,1),%R13D

0x28b09a SUB	%R14D,%R12D

0x28b09d NOPL	(%RAX)

(1320) 0x28b0a0 MOVSXD	%R13D,%R13

(1320) 0x28b0a3 VMOVUPD	(%RDX,%R13,8),%YMM7

(1320) 0x28b0a9 VMOVUPD	(%R10,%R13,8),%YMM8

(1320) 0x28b0af VMOVUPD	(%RSI,%R13,8),%YMM9

(1320) 0x28b0b5 VSUBPD	%YMM2,%YMM7,%YMM7

(1320) 0x28b0b9 VMULPD	0x48(%RDI){1to4},%YMM7,%YMM10

(1320) 0x28b0c0 VSUBPD	%YMM3,%YMM8,%YMM8

(1320) 0x28b0c4 VMULPD	0x60(%RDI){1to4},%YMM7,%YMM11

(1320) 0x28b0cb VMULPD	0x78(%RDI){1to4},%YMM7,%YMM7

(1320) 0x28b0d2 VSUBPD	%YMM4,%YMM9,%YMM9

(1320) 0x28b0d6 VFMADD231PD	0x50(%RDI){1to4},%YMM8,%YMM10

(1320) 0x28b0dd VFMADD231PD	0x80(%RDI){1to4},%YMM8,%YMM7

(1320) 0x28b0e4 VFMADD231PD	0x68(%RDI){1to4},%YMM8,%YMM11

(1320) 0x28b0eb VMOVDQA	%YMM6,%YMM8

(1320) 0x28b0ef VFMADD231PD	0x58(%RDI){1to4},%YMM9,%YMM10

(1320) 0x28b0f6 VFMADD231PD	0x88(%RDI){1to4},%YMM9,%YMM7

(1320) 0x28b0fd VFMADD231PD	0x70(%RDI){1to4},%YMM9,%YMM11

(1320) 0x28b104 VMOVDQA	%YMM6,%YMM9

(1320) 0x28b108 VPTERNLOGQ	$-0x8,%YMM5,%YMM10,%YMM8

(1320) 0x28b10f VPTERNLOGQ	$-0x8,%YMM5,%YMM11,%YMM9

(1320) 0x28b116 VADDPD	%YMM8,%YMM10,%YMM8

(1320) 0x28b11b VADDPD	%YMM9,%YMM11,%YMM9

(1320) 0x28b120 VROUNDPD	$0xb,%YMM8,%YMM8

(1320) 0x28b126 VROUNDPD	$0xb,%YMM9,%YMM9

(1320) 0x28b12c VSUBPD	%YMM8,%YMM10,%YMM8

(1320) 0x28b131 VMOVDQA	%YMM6,%YMM10

(1320) 0x28b135 VPTERNLOGQ	$-0x8,%YMM5,%YMM7,%YMM10

(1320) 0x28b13c VSUBPD	%YMM9,%YMM11,%YMM9

(1320) 0x28b141 VADDPD	%YMM7,%YMM10,%YMM10

(1320) 0x28b145 VROUNDPD	$0xb,%YMM10,%YMM10

(1320) 0x28b14b VSUBPD	%YMM10,%YMM7,%YMM7

(1320) 0x28b150 VMULPD	(%RDI){1to4},%YMM8,%YMM10

(1320) 0x28b156 VFMADD231PD	0x8(%RDI){1to4},%YMM9,%YMM10

(1320) 0x28b15d VFMADD231PD	0x10(%RDI){1to4},%YMM7,%YMM10

(1320) 0x28b164 VMOVUPD	%YMM10,(%R8,%R13,8)

(1320) 0x28b16a VMULPD	0x18(%RDI){1to4},%YMM8,%YMM10

(1320) 0x28b171 VFMADD231PD	0x20(%RDI){1to4},%YMM9,%YMM10

(1320) 0x28b178 VFMADD231PD	0x28(%RDI){1to4},%YMM7,%YMM10

(1320) 0x28b17f VMOVUPD	%YMM10,(%RBX,%R13,8)

(1320) 0x28b185 VMULPD	0x30(%RDI){1to4},%YMM8,%YMM8

(1320) 0x28b18c VFMADD231PD	0x38(%RDI){1to4},%YMM9,%YMM8

(1320) 0x28b193 VFMADD231PD	0x40(%RDI){1to4},%YMM7,%YMM8

(1320) 0x28b19a VMOVUPD	%YMM8,(%R11,%R13,8)

(1320) 0x28b1a0 VMOVUPD	(%R8,%R13,8),%YMM7

(1320) 0x28b1a6 VMOVUPD	(%RBX,%R13,8),%YMM9

(1320) 0x28b1ac VMULPD	%YMM7,%YMM7,%YMM7

(1320) 0x28b1b0 VFMADD231PD	%YMM8,%YMM8,%YMM7

(1320) 0x28b1b5 VFMADD231PD	%YMM9,%YMM9,%YMM7

(1320) 0x28b1ba VSQRTPD	%YMM7,%YMM7

(1320) 0x28b1be VMOVUPD	%YMM7,(%RCX,%R13,8)

(1320) 0x28b1c4 ADD	$0x4,%R13D

(1320) 0x28b1c8 ADD	$0x4,%R12D

(1320) 0x28b1cc JNE	28b0a0

0x28b1d2 CMP	%R14D,%R15D

0x28b1d5 JE	28b340

0x28b1db VMOVQ	-0x870bb(%RIP),%XMM2

0x28b1e3 VPBROADCASTQ	-0x8705c(%RIP),%XMM3

0x28b1ec VPBROADCASTQ	-0x870cd(%RIP),%XMM4

0x28b1f5 VPBROADCASTQ	-0x8704e(%RIP),%XMM5

0x28b1fe ADD	%R9D,%R14D

0x28b201 NOPW	%CS:(%RAX,%RAX,1)

(1319) 0x28b210 MOVSXD	%R14D,%R14

(1319) 0x28b213 VMOVUPD	0x48(%RDI),%XMM7

(1319) 0x28b218 VMOVUPD	0x68(%RDI),%XMM9

(1319) 0x28b21d VMOVUPD	0x60(%RDI),%XMM8

(1319) 0x28b222 VMOVUPD	0x70(%RDI),%XMM10

(1319) 0x28b227 VMOVSD	(%RDX,%R14,8),%XMM11

(1319) 0x28b22d VMOVHPD	0x50(%RDI),%XMM7,%XMM7

(1319) 0x28b232 VMOVSD	(%RSI,%R14,8),%XMM6

(1319) 0x28b238 VMOVHPD	0x78(%RDI),%XMM9,%XMM9

(1319) 0x28b23d VMOVHPD	0x80(%RDI),%XMM8,%XMM8

(1319) 0x28b245 VMOVHPD	(%R10,%R14,8),%XMM11,%XMM11

(1319) 0x28b24b VSUBSD	%XMM1,%XMM6,%XMM6

(1319) 0x28b24f VSUBPD	%XMM0,%XMM11,%XMM11

(1319) 0x28b253 VMULPD	%XMM7,%XMM11,%XMM7

(1319) 0x28b257 VSHUFPD	$0x1,%XMM11,%XMM11,%XMM13

(1319) 0x28b25d VMULPD	%XMM13,%XMM9,%XMM9

(1319) 0x28b262 VSHUFPD	$0x1,%XMM7,%XMM7,%XMM12

(1319) 0x28b267 VADDSD	%XMM7,%XMM12,%XMM7

(1319) 0x28b26b VFMADD231SD	0x58(%RDI),%XMM6,%XMM7

(1319) 0x28b271 VFMADD213PD	%XMM9,%XMM11,%XMM8

(1319) 0x28b276 VMOVHPD	0x88(%RDI),%XMM10,%XMM9

(1319) 0x28b27e VMOVDDUP	%XMM6,%XMM6

(1319) 0x28b282 VFMADD213PD	%XMM8,%XMM9,%XMM6

(1319) 0x28b287 VMOVAPD	%XMM7,%XMM8

(1319) 0x28b28b VPTERNLOGQ	$-0x28,%XMM3,%XMM2,%XMM8

(1319) 0x28b292 VADDSD	%XMM7,%XMM8,%XMM8

(1319) 0x28b296 VROUNDSD	$0xb,%XMM8,%XMM8,%XMM8

(1319) 0x28b29c VSUBSD	%XMM8,%XMM7,%XMM7

(1319) 0x28b2a1 VMOVDQA	%XMM4,%XMM8

(1319) 0x28b2a5 VPTERNLOGQ	$-0x8,%XMM5,%XMM6,%XMM8

(1319) 0x28b2ac VADDPD	%XMM6,%XMM8,%XMM8

(1319) 0x28b2b0 VROUNDPD	$0xb,%XMM8,%XMM8

(1319) 0x28b2b6 VSUBPD	%XMM8,%XMM6,%XMM6

(1319) 0x28b2bb VMULSD	(%RDI),%XMM7,%XMM8

(1319) 0x28b2bf VFMADD231SD	0x8(%RDI),%XMM6,%XMM8

(1319) 0x28b2c5 VSHUFPD	$0x1,%XMM6,%XMM6,%XMM9

(1319) 0x28b2ca VFMADD231SD	0x10(%RDI),%XMM9,%XMM8

(1319) 0x28b2d0 VMOVSD	%XMM8,(%R8,%R14,8)

(1319) 0x28b2d6 VMULSD	0x18(%RDI),%XMM7,%XMM8

(1319) 0x28b2db VFMADD231SD	0x20(%RDI),%XMM6,%XMM8

(1319) 0x28b2e1 VFMADD231SD	0x28(%RDI),%XMM9,%XMM8

(1319) 0x28b2e7 VMOVSD	%XMM8,(%RBX,%R14,8)

(1319) 0x28b2ed VMOVUPD	0x38(%RDI),%XMM8

(1319) 0x28b2f2 VMOVHPD	0x40(%RDI),%XMM8,%XMM8

(1319) 0x28b2f7 VMULPD	%XMM6,%XMM8,%XMM6

(1319) 0x28b2fb VSHUFPD	$0x1,%XMM6,%XMM6,%XMM8

(1319) 0x28b300 VFMADD231SD	0x30(%RDI),%XMM7,%XMM6

(1319) 0x28b306 VADDSD	%XMM6,%XMM8,%XMM6

(1319) 0x28b30a VMOVSD	%XMM6,(%R11,%R14,8)

(1319) 0x28b310 VMOVSD	(%R8,%R14,8),%XMM7

(1319) 0x28b316 VMOVSD	(%RBX,%R14,8),%XMM8

(1319) 0x28b31c VMULSD	%XMM7,%XMM7,%XMM7

(1319) 0x28b320 VFMADD231SD	%XMM6,%XMM6,%XMM7

(1319) 0x28b325 VFMADD231SD	%XMM8,%XMM8,%XMM7

(1319) 0x28b32a VSQRTSD	%XMM7,%XMM7,%XMM6

(1319) 0x28b32e VMOVSD	%XMM6,(%RCX,%R14,8)

(1319) 0x28b334 INC	%R14D

(1319) 0x28b337 CMP	%R14D,%EAX

(1319) 0x28b33a JNE	28b210

0x28b340 POP	%RBX

0x28b341 POP	%R12

0x28b343 POP	%R13

0x28b345 POP	%R14

0x28b347 POP	%R15

0x28b349 POP	%RBP

0x28b34a VZEROUPPER

0x28b34d RET

0x28b34e INT	$0x3

0x28b34f INT	$0x3

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221,234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.88 to 5.00 cycles (1.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.88 to 6.55 cycles (1.35x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 132 bytes.

General properties

nb instructions	76
nb uops	71
loop length	327
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	6
used zmm registers	6
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	4.00	4.00	4.00	4.00	1.50	5.00	5.00	1.50	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	4.00	4.00	4.00	4.00	1.50	5.00	5.00	1.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.88
Dispatch	5.00
Overall L1	8.88

Vectorization ratios

INT

all	5%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	15%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	27%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	16%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.88 cycles. At this rate:

5% of peak load performance is reached (14.87 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.88 to 5.00 cycles (1.77x speedup).

ASM code

In the binary file, the address of the function is: 28ae50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %R9D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 28b340 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RDX,%RSI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 28b1db <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x38b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 28b1db <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x38b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x8,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 28b06a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x21a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x86d4c(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ -0x86d26(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VPBROADCASTQ -0x86db8(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPERMPD %ZMM0,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 28b340 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x4,%R15B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 28b1db <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x38b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ -0x86ec3(%RIP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x86f54(%RIP),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA (%R12,%R9,1),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 28b340 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ -0x870bb(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x8705c(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x870cd(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x8704e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD %R9D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ParticleBConds3DSoa.h:221-257
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:221,234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.88 to 5.00 cycles (1.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 132 bytes.

General properties

nb instructions	76
nb uops	71
loop length	327
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	6
used zmm registers	6
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	4.00	4.00	4.00	4.00	1.50	5.00	5.00	1.50	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	4.00	4.00	4.00	4.00	1.50	5.00	5.00	1.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.88
Dispatch	5.00
Overall L1	8.88

Vectorization ratios

INT

all	5%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	15%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	27%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	16%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.88 cycles. At this rate:

5% of peak load performance is reached (14.87 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 28ae50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x10(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %R9D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 28b340 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%RSI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD 0x10(%RSI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RDX,%RSI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%R11,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x4,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 28b1db <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x38b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 28b1db <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x38b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x8,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 28b06a <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x21a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x86d4c(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ -0x86d26(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VPBROADCASTQ -0x86db8(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VBROADCASTSD %XMM0,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPERMPD %ZMM0,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 28b340 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x4,%R15B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 28b1db <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x38b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ -0x86ec3(%RIP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x86f54(%RIP),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPERMPD $0x55,%YMM0,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD %XMM1,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA (%R12,%R9,1),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 28b340 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ -0x870bb(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x8705c(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x870cd(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x8704e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD %R9D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	0.85	1.42
○Loop 1321 - ParticleBConds3DSoa.h:234-255 - exec	0.85	1.41
○Loop 1319 - ParticleBConds3DSoa.h:234-255 - exec	0.00	0.01
○Loop 1320 - ParticleBConds3DSoa.h:234-255 - exec	0.00	0.00

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Vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code