OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGrad(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGr ...	Module: exec	Source: DiracDeterminantRef.cpp:83-91 [...]	Coverage (incl. loops): 0.37% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 83 - 91

--------------------------------------------------------------------------------

83: {

84:   const int WorkingIndex = iat - FirstIndex;

85:   RatioTimer->start();

86:   invRow_id = WorkingIndex;

87:   updateEng.getInvRow(psiM, WorkingIndex, invRow);

88:   GradType g = simd::dot(invRow.data(), dpsiM[WorkingIndex], invRow.size());

89:   RatioTimer->stop();

90:   return g;

91: }

0x274370 PUSH	%RBP

0x274371 MOV	%RSP,%RBP

0x274374 PUSH	%R15

0x274376 PUSH	%R14

0x274378 PUSH	%RBX

0x274379 PUSH	%RAX

0x27437a MOV	%RDI,%RBX

0x27437d MOV	0x448(%RSI),%RDI

0x274384 MOVSXD	0x478(%RSI),%RAX

0x27438b MOVSXD	%ECX,%R15

0x27438e MOV	%RSI,%R14

0x274391 SUB	%RAX,%R15

0x274394 CALL	2a2310 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x274399 LEA	0x208(%R14),%RDI

0x2743a0 LEA	0xd0(%R14),%RSI

0x2743a7 LEA	0x408(%R14),%RCX

0x2743ae MOV	%R15D,%EDX

0x2743b1 MOV	%R15D,0x430(%R14)

0x2743b8 CALL	271b90 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>

0x2743bd MOV	0x420(%R14),%RAX

0x2743c4 MOV	0x118(%R14),%RCX

0x2743cb MOV	0x140(%R14),%RDX

0x2743d2 MOV	0x410(%R14),%RSI

0x2743d9 VPXOR	%XMM0,%XMM0,%XMM0

0x2743dd MOVQ	$0,0x10(%RBX)

0x2743e5 VMOVDQU	%XMM0,(%RBX)

0x2743e9 TEST	%ESI,%ESI

0x2743eb JLE	274805

0x2743f1 VMOVQ	0x8(%RBX),%XMM3

0x2743f6 VMOVQ	0x10(%RBX),%XMM1

0x2743fb IMUL	%R15,%RCX

0x2743ff LEA	(%RCX,%RCX,2),%RDI

0x274403 MOV	%ESI,%ECX

0x274405 CMP	$0x4,%ECX

0x274408 JAE	274415

0x27440a XOR	%ESI,%ESI

0x27440c VPUNPCKLQDQ	%XMM3,%XMM0,%XMM2

0x274410 JMP	2747c4

0x274415 CMP	$0x20,%ECX

0x274418 JAE	274425

0x27441a XOR	%ESI,%ESI

0x27441c VPUNPCKLQDQ	%XMM1,%XMM0,%XMM4

0x274420 JMP	2746ef

0x274425 VMOVAPD	-0x696ef(%RIP),%ZMM6

0x27442f VMOVAPD	-0x696b9(%RIP),%ZMM7

0x274439 VMOVAPD	-0x69683(%RIP),%ZMM8

0x274443 VMOVAPD	-0x6964d(%RIP),%ZMM9

0x27444d VMOVAPD	-0x69617(%RIP),%ZMM10

0x274457 VMOVAPD	-0x695e1(%RIP),%ZMM11

0x274461 LEA	(%RDX,%RDI,8),%R9

0x274465 MOV	%ECX,%R8D

0x274468 MOV	%ECX,%ESI

0x27446a AND	$0x1f,%R8D

0x27446e AND	$-0x20,%ESI

0x274471 VMOVQ	%XMM1,%XMM1

0x274475 VMOVQ	%XMM3,%XMM3

0x274479 VXORPD	%XMM2,%XMM2,%XMM2

0x27447d VXORPD	%XMM4,%XMM4,%XMM4

0x274481 VXORPD	%XMM5,%XMM5,%XMM5

0x274485 VXORPD	%XMM12,%XMM12,%XMM12

0x27448a VXORPD	%XMM13,%XMM13,%XMM13

0x27448f VXORPD	%XMM14,%XMM14,%XMM14

0x274494 VXORPD	%XMM15,%XMM15,%XMM15

0x274499 VXORPD	%XMM16,%XMM16,%XMM16

0x27449f VXORPD	%XMM17,%XMM17,%XMM17

0x2744a5 VXORPD	%XMM18,%XMM18,%XMM18

0x2744ab XOR	%R10D,%R10D

0x2744ae XCHG	%AX,%AX

(1056) 0x2744b0 VMOVUPD	(%R9),%ZMM20

(1056) 0x2744b6 VMOVUPD	0x40(%R9),%ZMM19

(1056) 0x2744bd VMOVUPD	0x80(%R9),%ZMM24

(1056) 0x2744c4 VMOVUPD	(%RAX,%R10,8),%ZMM23

(1056) 0x2744cb VMOVUPD	0x40(%RAX,%R10,8),%ZMM25

(1056) 0x2744d3 VMOVAPD	%ZMM20,%ZMM21

(1056) 0x2744d9 VPERMT2PD	%ZMM19,%ZMM6,%ZMM21

(1056) 0x2744df VMOVAPD	%ZMM20,%ZMM22

(1056) 0x2744e5 VPERMT2PD	%ZMM19,%ZMM8,%ZMM22

(1056) 0x2744eb VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

(1056) 0x2744f1 VPERMT2PD	%ZMM24,%ZMM7,%ZMM21

(1056) 0x2744f7 VPERMT2PD	%ZMM24,%ZMM9,%ZMM22

(1056) 0x2744fd VPERMT2PD	%ZMM24,%ZMM11,%ZMM19

(1056) 0x274503 VMOVUPD	0xc0(%R9),%ZMM24

(1056) 0x27450a VFMADD231PD	%ZMM21,%ZMM23,%ZMM15

(1056) 0x274510 VMOVUPD	0x100(%R9),%ZMM21

(1056) 0x274517 VFMADD231PD	%ZMM19,%ZMM23,%ZMM1

(1056) 0x27451d VFMADD231PD	%ZMM22,%ZMM23,%ZMM3

(1056) 0x274523 VMOVUPD	0x140(%R9),%ZMM23

(1056) 0x27452a VMOVAPD	%ZMM24,%ZMM19

(1056) 0x274530 VMOVAPD	%ZMM24,%ZMM20

(1056) 0x274536 VPERMT2PD	%ZMM21,%ZMM6,%ZMM19

(1056) 0x27453c VPERMT2PD	%ZMM21,%ZMM8,%ZMM20

(1056) 0x274542 VPERMT2PD	%ZMM24,%ZMM10,%ZMM21

(1056) 0x274548 VMOVUPD	0x180(%R9),%ZMM24

(1056) 0x27454f VPERMT2PD	%ZMM23,%ZMM7,%ZMM19

(1056) 0x274555 VPERMT2PD	%ZMM23,%ZMM11,%ZMM21

(1056) 0x27455b VPERMT2PD	%ZMM23,%ZMM9,%ZMM20

(1056) 0x274561 VMOVUPD	0x200(%R9),%ZMM23

(1056) 0x274568 VMOVAPD	%ZMM24,%ZMM22

(1056) 0x27456e VFMADD231PD	%ZMM19,%ZMM25,%ZMM16

(1056) 0x274574 VMOVUPD	0x1c0(%R9),%ZMM19

(1056) 0x27457b VFMADD231PD	%ZMM21,%ZMM25,%ZMM2

(1056) 0x274581 VMOVAPD	%ZMM24,%ZMM21

(1056) 0x274587 VFMADD231PD	%ZMM20,%ZMM25,%ZMM12

(1056) 0x27458d VPERMT2PD	%ZMM19,%ZMM6,%ZMM21

(1056) 0x274593 VPERMT2PD	%ZMM19,%ZMM8,%ZMM22

(1056) 0x274599 VPERMT2PD	%ZMM24,%ZMM10,%ZMM19

(1056) 0x27459f VMOVUPD	0x80(%RAX,%R10,8),%ZMM24

(1056) 0x2745a7 VPERMT2PD	%ZMM23,%ZMM7,%ZMM21

(1056) 0x2745ad VPERMT2PD	%ZMM23,%ZMM9,%ZMM22

(1056) 0x2745b3 VPERMT2PD	%ZMM23,%ZMM11,%ZMM19

(1056) 0x2745b9 VMOVUPD	0x240(%R9),%ZMM23

(1056) 0x2745c0 VFMADD231PD	%ZMM21,%ZMM24,%ZMM17

(1056) 0x2745c6 VMOVUPD	0x280(%R9),%ZMM21

(1056) 0x2745cd VFMADD231PD	%ZMM19,%ZMM24,%ZMM4

(1056) 0x2745d3 VFMADD231PD	%ZMM22,%ZMM24,%ZMM13

(1056) 0x2745d9 VMOVUPD	0x2c0(%R9),%ZMM24

(1056) 0x2745e0 ADD	$0x300,%R9

(1056) 0x2745e7 VMOVAPD	%ZMM23,%ZMM19

(1056) 0x2745ed VMOVAPD	%ZMM23,%ZMM20

(1056) 0x2745f3 VPERMT2PD	%ZMM21,%ZMM6,%ZMM19

(1056) 0x2745f9 VPERMT2PD	%ZMM21,%ZMM8,%ZMM20

(1056) 0x2745ff VPERMT2PD	%ZMM23,%ZMM10,%ZMM21

(1056) 0x274605 VMOVUPD	0xc0(%RAX,%R10,8),%ZMM23

(1056) 0x27460d ADD	$0x20,%R10

(1056) 0x274611 VPERMT2PD	%ZMM24,%ZMM7,%ZMM19

(1056) 0x274617 VPERMT2PD	%ZMM24,%ZMM9,%ZMM20

(1056) 0x27461d VPERMT2PD	%ZMM24,%ZMM11,%ZMM21

(1056) 0x274623 VFMADD231PD	%ZMM19,%ZMM23,%ZMM18

(1056) 0x274629 VFMADD231PD	%ZMM20,%ZMM23,%ZMM14

(1056) 0x27462f VFMADD231PD	%ZMM21,%ZMM23,%ZMM5

(1056) 0x274635 CMP	%R10,%RSI

(1056) 0x274638 JNE	2744b0

0x27463e VADDPD	%ZMM15,%ZMM16,%ZMM6

0x274644 VADDPD	%ZMM17,%ZMM18,%ZMM7

0x27464a VADDPD	%ZMM3,%ZMM12,%ZMM3

0x274650 VADDPD	%ZMM13,%ZMM14,%ZMM8

0x274656 VADDPD	%ZMM1,%ZMM2,%ZMM1

0x27465c VADDPD	%ZMM4,%ZMM5,%ZMM2

0x274662 VADDPD	%ZMM6,%ZMM7,%ZMM6

0x274668 VADDPD	%ZMM3,%ZMM8,%ZMM3

0x27466e VADDPD	%ZMM1,%ZMM2,%ZMM1

0x274674 VEXTRACTF64X4	$0x1,%ZMM6,%YMM7

0x27467b VEXTRACTF64X4	$0x1,%ZMM1,%YMM2

0x274682 VADDPD	%ZMM7,%ZMM6,%ZMM6

0x274688 VADDPD	%ZMM2,%ZMM1,%ZMM1

0x27468e VEXTRACTF128	$0x1,%YMM6,%XMM7

0x274694 VEXTRACTF128	$0x1,%YMM1,%XMM2

0x27469a VADDPD	%XMM7,%XMM6,%XMM6

0x27469e VADDPD	%XMM2,%XMM1,%XMM1

0x2746a2 VSHUFPD	$0x1,%XMM6,%XMM6,%XMM7

0x2746a7 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x2746ac VADDSD	%XMM7,%XMM6,%XMM6

0x2746b0 VEXTRACTF64X4	$0x1,%ZMM3,%YMM7

0x2746b7 VADDSD	%XMM2,%XMM1,%XMM1

0x2746bb VADDPD	%ZMM7,%ZMM3,%ZMM3

0x2746c1 VEXTRACTF128	$0x1,%YMM3,%XMM7

0x2746c7 VADDPD	%XMM7,%XMM3,%XMM3

0x2746cb VSHUFPD	$0x1,%XMM3,%XMM3,%XMM7

0x2746d0 VADDSD	%XMM7,%XMM3,%XMM3

0x2746d4 VUNPCKLPD	%XMM3,%XMM6,%XMM2

0x2746d8 TEST	%R8,%R8

0x2746db JE	2747fc

0x2746e1 CMP	$0x4,%R8D

0x2746e5 JB	2747c4

0x2746eb VUNPCKLPD	%XMM1,%XMM6,%XMM4

0x2746ef VPUNPCKHQDQ	%XMM0,%XMM4,%XMM1

0x2746f3 VMOVQ	%XMM3,%XMM2

0x2746f7 VMOVQ	%XMM4,%XMM0

0x2746fb VMOVAPD	-0x700e3(%RIP),%YMM3

0x274703 VMOVAPD	-0x7006b(%RIP),%YMM4

0x27470b VMOVAPD	-0x70113(%RIP),%YMM5

0x274713 MOV	%RSI,%R9

0x274716 LEA	(%R9,%R9,2),%R10

0x27471a MOV	%ECX,%R8D

0x27471d MOV	%ECX,%ESI

0x27471f AND	$0x3,%R8D

0x274723 AND	$-0x4,%ESI

0x274726 SAL	$0x3,%R10

0x27472a LEA	(%R10,%RDI,8),%R10

0x27472e ADD	%RDX,%R10

0x274731 NOPW	%CS:(%RAX,%RAX,1)

(1058) 0x274740 VMOVUPD	(%R10),%ZMM7

(1058) 0x274746 VMOVUPD	0x40(%R10),%YMM8

(1058) 0x27474c VMOVUPD	(%RAX,%R9,8),%YMM6

(1058) 0x274752 ADD	$0x4,%R9

(1058) 0x274756 ADD	$0x60,%R10

(1058) 0x27475a VMOVAPD	%ZMM7,%ZMM9

(1058) 0x274760 VMOVAPD	%ZMM7,%ZMM10

(1058) 0x274766 VPERMT2PD	%ZMM8,%ZMM3,%ZMM9

(1058) 0x27476c VPERMT2PD	%ZMM8,%ZMM4,%ZMM10

(1058) 0x274772 VPERMT2PD	%ZMM8,%ZMM5,%ZMM7

(1058) 0x274778 VFMADD231PD	%YMM9,%YMM6,%YMM0

(1058) 0x27477d VFMADD231PD	%YMM10,%YMM6,%YMM2

(1058) 0x274782 VFMADD231PD	%YMM7,%YMM6,%YMM1

(1058) 0x274787 CMP	%R9,%RSI

(1058) 0x27478a JNE	274740

0x27478c VEXTRACTF128	$0x1,%YMM1,%XMM3

0x274792 VADDPD	%XMM3,%XMM1,%XMM1

0x274796 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

0x27479b VADDSD	%XMM3,%XMM1,%XMM1

0x27479f VEXTRACTF128	$0x1,%YMM2,%XMM3

0x2747a5 VADDPD	%XMM3,%XMM2,%XMM2

0x2747a9 VEXTRACTF128	$0x1,%YMM0,%XMM3

0x2747af VADDPD	%XMM3,%XMM0,%XMM0

0x2747b3 VUNPCKHPD	%XMM2,%XMM0,%XMM3

0x2747b7 VUNPCKLPD	%XMM2,%XMM0,%XMM0

0x2747bb VADDPD	%XMM3,%XMM0,%XMM2

0x2747bf TEST	%R8,%R8

0x2747c2 JE	2747fc

0x2747c4 LEA	(%RSI,%RSI,2),%R8

0x2747c8 SAL	$0x3,%R8

0x2747cc LEA	(%R8,%RDI,8),%RDI

0x2747d0 LEA	0x10(%RDX,%RDI,1),%RDX

0x2747d5 NOPW	%CS:(%RAX,%RAX,1)

(1057) 0x2747e0 VMOVDDUP	(%RAX,%RSI,8),%XMM0

(1057) 0x2747e5 INC	%RSI

(1057) 0x2747e8 VFMADD231PD	-0x10(%RDX),%XMM0,%XMM2

(1057) 0x2747ee VFMADD231SD	(%RDX),%XMM0,%XMM1

(1057) 0x2747f3 ADD	$0x18,%RDX

(1057) 0x2747f7 CMP	%RSI,%RCX

(1057) 0x2747fa JNE	2747e0

0x2747fc VMOVUPD	%XMM2,(%RBX)

0x274800 VMOVSD	%XMM1,0x10(%RBX)

0x274805 MOV	0x448(%R14),%RDI

0x27480c VZEROUPPER

0x27480f CALL	2a2400 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x274814 MOV	%RBX,%RAX

0x274817 ADD	$0x8,%RSP

0x27481b POP	%RBX

0x27481c POP	%R14

0x27481e POP	%R15

0x274820 POP	%RBP

0x274821 RET

0x274822 INT	$0x3

0x274823 INT	$0x3

0x274824 INT	$0x3

0x274825 INT	$0x3

0x274826 INT	$0x3

0x274827 INT	$0x3

0x274828 INT	$0x3

0x274829 INT	$0x3

0x27482a INT	$0x3

0x27482b INT	$0x3

0x27482c INT	$0x3

0x27482d INT	$0x3

0x27482e INT	$0x3

0x27482f INT	$0x3

Coverage (%)	Name	Source Location	Module
►96.14+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.05+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	main.omp_outlined.64	stl_vector.h:1046	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	DiracDeterminantRef.cpp:83-91
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:83-91

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.50 to 11.75 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 18.50 to 14.08 cycles (1.31x speedup).

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

81% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
79% of SSE/AVX addition or subtraction instructions are used in vector version.
56% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:85
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:89
void qmcplusplus::DelayedUpdate
::getInvRow
> >(qmcplusplus::Matrix
> const&, int, qmcplusplus::Vector
>&): 1 occurrences►
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:87

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155

Vector unaligned load/store instructions

Detected 9 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
VEXTRACTF64X4: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 114 FP arithmetical operations:

114: addition or subtraction

The binary function is loading 548 bytes (68 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	161
nb uops	148
loop length	714
used x86 registers	13
used mmx registers	0
used xmm registers	15
used ymm registers	8
used zmm registers	18
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	6.75	6.75	6.75	6.75	11.75	11.75	11.75	11.75	1.50	1.50
cycles	6.67	6.67	6.67	6.67	6.67	6.67	6.75	6.75	6.75	6.75	11.75	11.75	11.75	11.75	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.50
Dispatch	11.75
Overall L1	18.50

Vectorization ratios

INT

all	13%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	85%
load	100%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	82%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	65%
load	81%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	79%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	47%
load	83%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	61%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	38%
load	70%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.50 cycles. At this rate:

11% of peak load performance is reached (29.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.50 to 11.75 cycles (1.57x speedup).

ASM code

In the binary file, the address of the function is: 274370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x448(%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD 0x478(%RSI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD %ECX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 2a2310 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x208(%R14),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xd0(%R14),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x408(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,0x430(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 271b90 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x420(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x410(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOVQ $0,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVDQU %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 274805 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x495>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ 0x8(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
IMUL %R15,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RCX,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 274415 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0xa5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VPUNPCKLQDQ %XMM3,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 2747c4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x454>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 274425 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0xb5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VPUNPCKLQDQ %XMM1,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 2746ef <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x37f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPD -0x696ef(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x696b9(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69683(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x6964d(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69617(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x695e1(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
LEA (%RDX,%RDI,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x1f,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVQ %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VADDPD %ZMM15,%ZMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM17,%ZMM18,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM12,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM14,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM6,%ZMM7,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM7,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM7,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM6,%XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM7,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM3,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDPD %ZMM7,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM7,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM3,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM7,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUNPCKLPD %XMM3,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
TEST %R8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2747fc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x48c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 2747c4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x454>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VUNPCKLPD %XMM1,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VPUNPCKHQDQ %XMM0,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVQ %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD -0x700e3(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x7006b(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x70113(%RIP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x3,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R10,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKHPD %XMM2,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VUNPCKLPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM3,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
TEST %R8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2747fc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x48c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RSI,%RSI,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%RDI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(%RDX,%RDI,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVUPD %XMM2,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM1,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x448(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2a2400 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	DiracDeterminantRef.cpp:83-91
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:83-91

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

81% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
79% of SSE/AVX addition or subtraction instructions are used in vector version.
56% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

qmcplusplus::TimerType
::start(): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:85
qmcplusplus::TimerType
::stop(): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:89
void qmcplusplus::DelayedUpdate
::getInvRow
> >(qmcplusplus::Matrix
> const&, int, qmcplusplus::Vector
>&): 1 occurrences►
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:87

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155

Vector unaligned load/store instructions

Detected 9 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:94
VEXTRACTF64X4: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 114 FP arithmetical operations:

114: addition or subtraction

The binary function is loading 548 bytes (68 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	161
nb uops	148
loop length	714
used x86 registers	13
used mmx registers	0
used xmm registers	15
used ymm registers	8
used zmm registers	18
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	6.75	6.75	6.75	6.75	11.75	11.75	11.75	11.75	1.50	1.50
cycles	6.67	6.67	6.67	6.67	6.67	6.67	6.75	6.75	6.75	6.75	11.75	11.75	11.75	11.75	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.50
Dispatch	11.75
Overall L1	18.50

Vectorization ratios

INT

all	13%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	85%
load	100%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	82%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	65%
load	81%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	79%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	47%
load	83%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	61%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	38%
load	70%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.50 cycles. At this rate:

11% of peak load performance is reached (29.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 274370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x448(%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD 0x478(%RSI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVSXD %ECX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 2a2310 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x208(%R14),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xd0(%R14),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x408(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,0x430(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 271b90 <_ZN11qmcplusplus13DelayedUpdateIddE9getInvRowINS_6VectorIdSaIdEEEEEvRKNS_6MatrixIdS4_EEiRT_>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x420(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x410(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOVQ $0,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMOVDQU %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 274805 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x495>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ 0x8(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
IMUL %R15,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RCX,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 274415 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0xa5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VPUNPCKLQDQ %XMM3,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 2747c4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x454>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 274425 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0xb5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VPUNPCKLQDQ %XMM1,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 2746ef <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x37f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPD -0x696ef(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x696b9(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69683(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x6964d(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69617(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x695e1(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
LEA (%RDX,%RDI,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x1f,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVQ %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VADDPD %ZMM15,%ZMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM17,%ZMM18,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM12,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM13,%ZMM14,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM4,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM6,%ZMM7,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM3,%ZMM8,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM1,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM7,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM7,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM6,%XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM7,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM3,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDPD %ZMM7,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM7,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM3,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM7,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUNPCKLPD %XMM3,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
TEST %R8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2747fc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x48c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 2747c4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x454>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VUNPCKLPD %XMM1,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VPUNPCKHQDQ %XMM0,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVQ %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMOVAPD -0x700e3(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x7006b(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x70113(%RIP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x3,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R10,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKHPD %XMM2,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VUNPCKLPD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM3,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
TEST %R8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2747fc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x48c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RSI,%RSI,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%RDI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(%RDX,%RDI,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVUPD %XMM2,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSD %XMM1,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x448(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2a2400 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)–	0.37	0.62
○Loop 1056 - inner_product.hpp:155-155 - exec	0.37	0.62
○Loop 1058 - inner_product.hpp:155-155 - exec	0.00	0.00
○Loop 1057 - inner_product.hpp:155-155 - exec	0.00	0.00

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