OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: DiracDeterminantRef.cpp:235-255 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 129 - 131

--------------------------------------------------------------------------------

129:     Type_t res = lhs[0] * rhs[0];

130:     for (unsigned d = 1; d < D; ++d)

131:       res += lhs[d] * rhs[d];

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 155

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 235 - 255

--------------------------------------------------------------------------------

235: {

236:   recompute(P);

237:

238:   if (NumPtcls == 1)

239:   {

240:     ValueType y = psiM(0, 0);

241:     GradType rv = y * dpsiM(0, 0);

242:     G[FirstIndex] += rv;

243:     L[FirstIndex] += y * d2psiM(0, 0) - dot(rv, rv);

244:   }

245:   else

246:   {

247:     for (int i = 0, iat = FirstIndex; i < NumPtcls; i++, iat++)

248:     {

249:       mGradType rv   = simd::dot(psiM[i], dpsiM[i], NumOrbitals);

250:       mValueType lap = simd::dot(psiM[i], d2psiM[i], NumOrbitals);

251:       G[iat] += rv;

252:       L[iat] += lap - dot(rv, rv);

253:     }

254:   }

255:   return LogValue;

0x273c10 PUSH	%RBP

0x273c11 MOV	%RSP,%RBP

0x273c14 PUSH	%R15

0x273c16 PUSH	%R14

0x273c18 PUSH	%R13

0x273c1a PUSH	%R12

0x273c1c PUSH	%RBX

0x273c1d SUB	$0x38,%RSP

0x273c21 MOV	%RCX,%R14

0x273c24 MOV	%RDX,%R15

0x273c27 MOV	%RDI,%RBX

0x273c2a CALL	276450 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9recomputeERNS1_11ParticleSetE>

0x273c2f MOV	0x484(%RBX),%EDX

0x273c35 CMP	$0x1,%RDX

0x273c39 JNE	273cac

0x273c3b MOV	0x100(%RBX),%RAX

0x273c42 MOV	0x140(%RBX),%RCX

0x273c49 MOV	0x18(%R15),%RDX

0x273c4d VMOVDDUP	(%RAX),%XMM0

0x273c51 MOVSXD	0x478(%RBX),%RAX

0x273c58 VMULPD	(%RCX),%XMM0,%XMM2

0x273c5c VMULSD	0x10(%RCX),%XMM0,%XMM1

0x273c61 LEA	(%RAX,%RAX,2),%RSI

0x273c65 VADDPD	(%RDX,%RSI,8),%XMM2,%XMM3

0x273c6a VMULPD	%XMM2,%XMM2,%XMM2

0x273c6e VMOVUPD	%XMM3,(%RDX,%RSI,8)

0x273c73 VADDSD	0x10(%RDX,%RSI,8),%XMM1,%XMM3

0x273c79 VMOVSD	%XMM3,0x10(%RDX,%RSI,8)

0x273c7f VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0x273c84 MOV	0x180(%RBX),%RCX

0x273c8b VADDSD	%XMM2,%XMM3,%XMM2

0x273c8f MOV	0x18(%R14),%RDX

0x273c93 VFMADD231SD	%XMM1,%XMM1,%XMM2

0x273c98 VFMSUB231SD	(%RCX),%XMM0,%XMM2

0x273c9d VADDSD	(%RDX,%RAX,8),%XMM2,%XMM0

0x273ca2 VMOVSD	%XMM0,(%RDX,%RAX,8)

0x273ca7 JMP	274359

0x273cac TEST	%EDX,%EDX

0x273cae JLE	274359

0x273cb4 MOV	0x480(%RBX),%ECX

0x273cba TEST	%ECX,%ECX

0x273cbc JLE	274359

0x273cc2 MOV	0x118(%RBX),%RAX

0x273cc9 MOV	0x18(%R14),%R14

0x273ccd VMOVAPD	-0x6f6b5(%RIP),%YMM1

0x273cd5 VMOVAPD	-0x6f63d(%RIP),%YMM2

0x273cdd VMOVAPD	-0x6f6e5(%RIP),%YMM3

0x273ce5 VMOVAPD	-0x6912f(%RIP),%ZMM4

0x273cef VMOVAPD	-0x690f9(%RIP),%ZMM5

0x273cf9 VMOVAPD	-0x690c3(%RIP),%ZMM6

0x273d03 VMOVAPD	-0x6908d(%RIP),%ZMM7

0x273d0d VMOVAPD	-0x69057(%RIP),%ZMM8

0x273d17 VMOVAPD	-0x69021(%RIP),%ZMM9

0x273d21 MOV	0x158(%RBX),%R11

0x273d28 MOV	0xd8(%RBX),%RDI

0x273d2f MOV	0x100(%RBX),%RSI

0x273d36 MOV	0x180(%RBX),%R8

0x273d3d MOV	0x18(%R15),%R10

0x273d41 MOV	0x140(%RBX),%R9

0x273d48 MOV	%ECX,%R15D

0x273d4b MOV	%ECX,%R12D

0x273d4e AND	$-0x20,%R15D

0x273d52 AND	$-0x4,%R12D

0x273d56 VXORPD	%XMM0,%XMM0,%XMM0

0x273d5a MOV	%RDX,-0x58(%RBP)

0x273d5e MOV	%R15,-0x30(%RBP)

0x273d62 XOR	%R15D,%R15D

0x273d65 SAL	$0x3,%RAX

0x273d69 MOV	%R14,-0x40(%RBP)

0x273d6d MOVSXD	0x478(%RBX),%R14

0x273d74 SAL	$0x3,%R11

0x273d78 SAL	$0x3,%RDI

0x273d7c LEA	0xc0(%RSI),%R13

0x273d83 LEA	(%RAX,%RAX,2),%RAX

0x273d87 MOV	%R11,-0x48(%RBP)

0x273d8b LEA	0xc0(%R8),%R11

0x273d92 MOV	%RDI,-0x50(%RBP)

0x273d96 MOV	%RAX,-0x38(%RBP)

0x273d9a MOV	%ECX,%EAX

0x273d9c SHR	$0x5,%EAX

0x273d9f SAL	$0x8,%RAX

0x273da3 JMP	273e26

0x273da8 NOPL	(%RAX,%RAX,1)

(1051) 0x273db0 LEA	(%R14,%R14,2),%RDX

(1051) 0x273db4 MOV	-0x48(%RBP),%RDI

(1051) 0x273db8 ADD	-0x38(%RBP),%R9

(1051) 0x273dbc INC	%R15

(1051) 0x273dbf VADDPD	(%R10,%RDX,8),%XMM10,%XMM13

(1051) 0x273dc5 ADD	%RDI,%R11

(1051) 0x273dc8 ADD	%RDI,%R8

(1051) 0x273dcb VMOVUPD	%XMM13,(%R10,%RDX,8)

(1051) 0x273dd1 VADDSD	0x10(%R10,%RDX,8),%XMM11,%XMM13

(1051) 0x273dd8 VBLENDPD	$0x1,%XMM11,%XMM10,%XMM11

(1051) 0x273dde VMULPD	%XMM11,%XMM11,%XMM11

(1051) 0x273de3 VMOVSD	%XMM13,0x10(%R10,%RDX,8)

(1051) 0x273dea VSHUFPD	$0x1,%XMM11,%XMM11,%XMM13

(1051) 0x273df0 MOV	-0x40(%RBP),%RDX

(1051) 0x273df4 VFMADD231SD	%XMM10,%XMM10,%XMM13

(1051) 0x273df9 VADDSD	%XMM13,%XMM11,%XMM10

(1051) 0x273dfe VSUBSD	%XMM10,%XMM12,%XMM10

(1051) 0x273e03 VADDSD	(%RDX,%R14,8),%XMM10,%XMM10

(1051) 0x273e09 VMOVSD	%XMM10,(%RDX,%R14,8)

(1051) 0x273e0f MOV	-0x50(%RBP),%RDX

(1051) 0x273e13 INC	%R14

(1051) 0x273e16 ADD	%RDX,%R13

(1051) 0x273e19 ADD	%RDX,%RSI

(1051) 0x273e1c CMP	%R15,-0x58(%RBP)

(1051) 0x273e20 JE	274359

(1051) 0x273e26 CMP	$0x4,%ECX

(1051) 0x273e29 JAE	273e40

(1051) 0x273e2b VXORPD	%XMM10,%XMM10,%XMM10

(1051) 0x273e30 XOR	%EDI,%EDI

(1051) 0x273e32 JMP	2741ca

0x273e37 NOPW	(%RAX,%RAX,1)

(1051) 0x273e40 CMP	$0x20,%ECX

(1051) 0x273e43 JAE	273e60

(1051) 0x273e45 VXORPD	%XMM10,%XMM10,%XMM10

(1051) 0x273e4a XOR	%EDX,%EDX

(1051) 0x273e4c JMP	274113

0x273e51 NOPW	%CS:(%RAX,%RAX,1)

(1051) 0x273e60 VXORPD	%XMM10,%XMM10,%XMM10

(1051) 0x273e65 VXORPD	%XMM12,%XMM12,%XMM12

(1051) 0x273e6a VXORPD	%XMM13,%XMM13,%XMM13

(1051) 0x273e6f VXORPD	%XMM14,%XMM14,%XMM14

(1051) 0x273e74 VXORPD	%XMM15,%XMM15,%XMM15

(1051) 0x273e79 VXORPD	%XMM16,%XMM16,%XMM16

(1051) 0x273e7f VXORPD	%XMM17,%XMM17,%XMM17

(1051) 0x273e85 VXORPD	%XMM18,%XMM18,%XMM18

(1051) 0x273e8b VXORPD	%XMM11,%XMM11,%XMM11

(1051) 0x273e90 VXORPD	%XMM19,%XMM19,%XMM19

(1051) 0x273e96 VXORPD	%XMM20,%XMM20,%XMM20

(1051) 0x273e9c VXORPD	%XMM21,%XMM21,%XMM21

(1051) 0x273ea2 XOR	%EDX,%EDX

(1051) 0x273ea4 MOV	%R9,%RDI

(1051) 0x273ea7 NOPW	(%RAX,%RAX,1)

  (1049) 0x273eb0 VMOVUPD	(%RDI),%ZMM23

  (1049) 0x273eb6 VMOVUPD	0x40(%RDI),%ZMM22

  (1049) 0x273ebd VMOVUPD	0x80(%RDI),%ZMM27

  (1049) 0x273ec4 VMOVUPD	-0xc0(%R13,%RDX,1),%ZMM26

  (1049) 0x273ecc VMOVUPD	-0x80(%R13,%RDX,1),%ZMM28

  (1049) 0x273ed4 VMOVAPD	%ZMM23,%ZMM24

  (1049) 0x273eda VPERMT2PD	%ZMM22,%ZMM4,%ZMM24

  (1049) 0x273ee0 VMOVAPD	%ZMM23,%ZMM25

  (1049) 0x273ee6 VPERMT2PD	%ZMM22,%ZMM6,%ZMM25

  (1049) 0x273eec VPERMT2PD	%ZMM23,%ZMM8,%ZMM22

  (1049) 0x273ef2 VPERMT2PD	%ZMM27,%ZMM5,%ZMM24

  (1049) 0x273ef8 VPERMT2PD	%ZMM27,%ZMM7,%ZMM25

  (1049) 0x273efe VPERMT2PD	%ZMM27,%ZMM9,%ZMM22

  (1049) 0x273f04 VMOVUPD	0xc0(%RDI),%ZMM27

  (1049) 0x273f0b VFMADD231PD	%ZMM24,%ZMM26,%ZMM10

  (1049) 0x273f11 VMOVUPD	0x100(%RDI),%ZMM24

  (1049) 0x273f18 VFMADD231PD	%ZMM22,%ZMM26,%ZMM11

  (1049) 0x273f1e VFMADD231PD	%ZMM25,%ZMM26,%ZMM15

  (1049) 0x273f24 VMOVUPD	0x140(%RDI),%ZMM26

  (1049) 0x273f2b VMOVAPD	%ZMM27,%ZMM22

  (1049) 0x273f31 VMOVAPD	%ZMM27,%ZMM23

  (1049) 0x273f37 VPERMT2PD	%ZMM24,%ZMM4,%ZMM22

  (1049) 0x273f3d VPERMT2PD	%ZMM24,%ZMM6,%ZMM23

  (1049) 0x273f43 VPERMT2PD	%ZMM27,%ZMM8,%ZMM24

  (1049) 0x273f49 VMOVUPD	0x180(%RDI),%ZMM27

  (1049) 0x273f50 VPERMT2PD	%ZMM26,%ZMM5,%ZMM22

  (1049) 0x273f56 VPERMT2PD	%ZMM26,%ZMM9,%ZMM24

  (1049) 0x273f5c VPERMT2PD	%ZMM26,%ZMM7,%ZMM23

  (1049) 0x273f62 VMOVUPD	0x200(%RDI),%ZMM26

  (1049) 0x273f69 VMOVAPD	%ZMM27,%ZMM25

  (1049) 0x273f6f VFMADD231PD	%ZMM22,%ZMM28,%ZMM12

  (1049) 0x273f75 VMOVUPD	0x1c0(%RDI),%ZMM22

  (1049) 0x273f7c VFMADD231PD	%ZMM24,%ZMM28,%ZMM19

  (1049) 0x273f82 VMOVAPD	%ZMM27,%ZMM24

  (1049) 0x273f88 VFMADD231PD	%ZMM23,%ZMM28,%ZMM16

  (1049) 0x273f8e VPERMT2PD	%ZMM22,%ZMM4,%ZMM24

  (1049) 0x273f94 VPERMT2PD	%ZMM22,%ZMM6,%ZMM25

  (1049) 0x273f9a VPERMT2PD	%ZMM27,%ZMM8,%ZMM22

  (1049) 0x273fa0 VMOVUPD	-0x40(%R13,%RDX,1),%ZMM27

  (1049) 0x273fa8 VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (1049) 0x273fae VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (1049) 0x273fb4 VPERMT2PD	%ZMM26,%ZMM9,%ZMM22

  (1049) 0x273fba VMOVUPD	0x240(%RDI),%ZMM26

  (1049) 0x273fc1 VFMADD231PD	%ZMM24,%ZMM27,%ZMM13

  (1049) 0x273fc7 VMOVUPD	0x280(%RDI),%ZMM24

  (1049) 0x273fce VFMADD231PD	%ZMM22,%ZMM27,%ZMM20

  (1049) 0x273fd4 VFMADD231PD	%ZMM25,%ZMM27,%ZMM17

  (1049) 0x273fda VMOVUPD	0x2c0(%RDI),%ZMM27

  (1049) 0x273fe1 ADD	$0x300,%RDI

  (1049) 0x273fe8 VMOVAPD	%ZMM26,%ZMM22

  (1049) 0x273fee VMOVAPD	%ZMM26,%ZMM23

  (1049) 0x273ff4 VPERMT2PD	%ZMM24,%ZMM4,%ZMM22

  (1049) 0x273ffa VPERMT2PD	%ZMM24,%ZMM6,%ZMM23

  (1049) 0x274000 VPERMT2PD	%ZMM26,%ZMM8,%ZMM24

  (1049) 0x274006 VMOVUPD	(%R13,%RDX,1),%ZMM26

  (1049) 0x27400e ADD	$0x100,%RDX

  (1049) 0x274015 VPERMT2PD	%ZMM27,%ZMM5,%ZMM22

  (1049) 0x27401b VPERMT2PD	%ZMM27,%ZMM7,%ZMM23

  (1049) 0x274021 VPERMT2PD	%ZMM27,%ZMM9,%ZMM24

  (1049) 0x274027 VFMADD231PD	%ZMM22,%ZMM26,%ZMM14

  (1049) 0x27402d VFMADD231PD	%ZMM23,%ZMM26,%ZMM18

  (1049) 0x274033 VFMADD231PD	%ZMM24,%ZMM26,%ZMM21

  (1049) 0x274039 CMP	%RDX,%RAX

  (1049) 0x27403c JNE	273eb0

(1051) 0x274042 VADDPD	%ZMM15,%ZMM16,%ZMM15

(1051) 0x274048 VADDPD	%ZMM17,%ZMM18,%ZMM16

(1051) 0x27404e VADDPD	%ZMM10,%ZMM12,%ZMM10

(1051) 0x274054 VADDPD	%ZMM13,%ZMM14,%ZMM13

(1051) 0x27405a VADDPD	%ZMM11,%ZMM19,%ZMM11

(1051) 0x274060 VADDPD	%ZMM20,%ZMM21,%ZMM19

(1051) 0x274066 MOV	-0x30(%RBP),%RDI

(1051) 0x27406a VADDPD	%ZMM15,%ZMM16,%ZMM15

(1051) 0x274070 VADDPD	%ZMM10,%ZMM13,%ZMM10

(1051) 0x274076 VADDPD	%ZMM11,%ZMM19,%ZMM11

(1051) 0x27407c VEXTRACTF64X4	$0x1,%ZMM15,%YMM16

(1051) 0x274083 VEXTRACTF64X4	$0x1,%ZMM10,%YMM12

(1051) 0x27408a VEXTRACTF64X4	$0x1,%ZMM11,%YMM19

(1051) 0x274091 VADDPD	%ZMM16,%ZMM15,%ZMM15

(1051) 0x274097 VADDPD	%ZMM12,%ZMM10,%ZMM10

(1051) 0x27409d VADDPD	%ZMM19,%ZMM11,%ZMM11

(1051) 0x2740a3 VEXTRACTF32X4	$0x1,%YMM15,%XMM16

(1051) 0x2740aa VEXTRACTF128	$0x1,%YMM10,%XMM12

(1051) 0x2740b0 VEXTRACTF32X4	$0x1,%YMM11,%XMM19

(1051) 0x2740b7 VADDPD	%XMM16,%XMM15,%XMM15

(1051) 0x2740bd VADDPD	%XMM12,%XMM10,%XMM10

(1051) 0x2740c2 VADDPD	%XMM19,%XMM11,%XMM11

(1051) 0x2740c8 VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(1051) 0x2740cf VSHUFPD	$0x1,%XMM10,%XMM10,%XMM12

(1051) 0x2740d5 VSHUFPD	$0x1,%XMM11,%XMM11,%XMM19

(1051) 0x2740dc VADDSD	%XMM16,%XMM15,%XMM15

(1051) 0x2740e2 VADDSD	%XMM12,%XMM10,%XMM10

(1051) 0x2740e7 VADDSD	%XMM19,%XMM11,%XMM11

(1051) 0x2740ed VUNPCKLPD	%XMM15,%XMM10,%XMM10

(1051) 0x2740f2 CMP	%RCX,%RDI

(1051) 0x2740f5 JE	274203

(1051) 0x2740fb VINSERTF128	$0x1,%XMM11,%YMM10,%YMM10

(1051) 0x274101 MOV	%RDI,%RDX

(1051) 0x274104 VSHUFPD	$0x2,%YMM10,%YMM10,%YMM10

(1051) 0x27410a TEST	$0x1c,%CL

(1051) 0x27410d JE	2741ca

(1051) 0x274113 LEA	(%RDX,%RDX,2),%RDI

(1051) 0x274117 VMOVQ	%XMM10,%XMM12

(1051) 0x27411c VUNPCKHPD	%XMM0,%XMM10,%XMM13

(1051) 0x274120 VEXTRACTI128	$0x1,%YMM10,%XMM10

(1051) 0x274126 LEA	(%R9,%RDI,8),%RDI

(1051) 0x27412a VMOVQ	%XMM10,%XMM10

(1051) 0x27412f NOP

  (1055) 0x274130 VMOVUPD	(%RDI),%ZMM14

  (1055) 0x274136 VMOVUPD	0x40(%RDI),%YMM15

  (1055) 0x27413b VMOVUPD	(%RSI,%RDX,8),%YMM11

  (1055) 0x274140 ADD	$0x4,%RDX

  (1055) 0x274144 ADD	$0x60,%RDI

  (1055) 0x274148 VMOVAPD	%ZMM14,%ZMM16

  (1055) 0x27414e VMOVAPD	%ZMM14,%ZMM17

  (1055) 0x274154 VPERMT2PD	%ZMM15,%ZMM1,%ZMM16

  (1055) 0x27415a VPERMT2PD	%ZMM15,%ZMM2,%ZMM17

  (1055) 0x274160 VPERMT2PD	%ZMM15,%ZMM3,%ZMM14

  (1055) 0x274166 VFMADD231PD	%YMM16,%YMM11,%YMM12

  (1055) 0x27416c VFMADD231PD	%YMM17,%YMM11,%YMM13

  (1055) 0x274172 VFMADD231PD	%YMM14,%YMM11,%YMM10

  (1055) 0x274177 CMP	%RDX,%R12

  (1055) 0x27417a JNE	274130

(1051) 0x27417c VEXTRACTF128	$0x1,%YMM10,%XMM11

(1051) 0x274182 VADDPD	%YMM11,%YMM10,%YMM10

(1051) 0x274187 VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

(1051) 0x27418d VADDPD	%YMM11,%YMM10,%YMM11

(1051) 0x274192 VEXTRACTF128	$0x1,%YMM13,%XMM10

(1051) 0x274198 VADDPD	%XMM10,%XMM13,%XMM10

(1051) 0x27419d VEXTRACTF128	$0x1,%YMM12,%XMM13

(1051) 0x2741a3 VADDPD	%XMM13,%XMM12,%XMM12

(1051) 0x2741a8 VUNPCKHPD	%XMM10,%XMM12,%XMM13

(1051) 0x2741ad VUNPCKLPD	%XMM10,%XMM12,%XMM10

(1051) 0x2741b2 VADDPD	%XMM13,%XMM10,%XMM10

(1051) 0x2741b7 CMP	%RCX,%R12

(1051) 0x2741ba JE	2741ff

(1051) 0x2741bc VBROADCASTSD	%XMM11,%YMM11

(1051) 0x2741c1 MOV	%R12,%RDI

(1051) 0x2741c4 VBLENDPD	$0xc,%YMM11,%YMM10,%YMM10

(1051) 0x2741ca LEA	(%RDI,%RDI,2),%RDX

(1051) 0x2741ce LEA	(%R9,%RDX,8),%RDX

(1051) 0x2741d2 NOPW	%CS:(%RAX,%RAX,1)

  (1054) 0x2741e0 VPERMILPD	$0x2,(%RDX),%YMM11

  (1054) 0x2741e6 ADD	$0x18,%RDX

  (1054) 0x2741ea VFMADD231PD	(%RSI,%RDI,8){1to4},%YMM11,%YMM10

  (1054) 0x2741f1 INC	%RDI

  (1054) 0x2741f4 CMP	%RDI,%RCX

  (1054) 0x2741f7 JNE	2741e0

(1051) 0x2741f9 VEXTRACTF128	$0x1,%YMM10,%XMM11

(1051) 0x2741ff MOV	-0x30(%RBP),%RDI

(1051) 0x274203 CMP	$0x4,%ECX

(1051) 0x274206 JAE	274220

(1051) 0x274208 VXORPD	%XMM12,%XMM12,%XMM12

(1051) 0x27420d XOR	%EDX,%EDX

(1051) 0x27420f JMP	274340

0x274214 NOPW	%CS:(%RAX,%RAX,1)

(1051) 0x274220 CMP	$0x20,%ECX

(1051) 0x274223 JAE	274240

(1051) 0x274225 VXORPD	%XMM12,%XMM12,%XMM12

(1051) 0x27422a XOR	%EDI,%EDI

(1051) 0x27422c JMP	2742f1

0x274231 NOPW	%CS:(%RAX,%RAX,1)

(1051) 0x274240 VXORPD	%XMM12,%XMM12,%XMM12

(1051) 0x274245 VXORPD	%XMM13,%XMM13,%XMM13

(1051) 0x27424a VXORPD	%XMM14,%XMM14,%XMM14

(1051) 0x27424f VXORPD	%XMM15,%XMM15,%XMM15

(1051) 0x274254 XOR	%EDX,%EDX

(1051) 0x274256 NOPW	%CS:(%RAX,%RAX,1)

  (1050) 0x274260 VMOVUPD	-0xc0(%R11,%RDX,1),%ZMM16

  (1050) 0x274268 VMOVUPD	-0x80(%R11,%RDX,1),%ZMM17

  (1050) 0x274270 VMOVUPD	-0x40(%R11,%RDX,1),%ZMM18

  (1050) 0x274278 VMOVUPD	(%R11,%RDX,1),%ZMM19

  (1050) 0x27427f VFMADD231PD	-0xc0(%R13,%RDX,1),%ZMM16,%ZMM12

  (1050) 0x274287 VFMADD231PD	-0x80(%R13,%RDX,1),%ZMM17,%ZMM13

  (1050) 0x27428f VFMADD231PD	-0x40(%R13,%RDX,1),%ZMM18,%ZMM14

  (1050) 0x274297 VFMADD231PD	(%R13,%RDX,1),%ZMM19,%ZMM15

  (1050) 0x27429f ADD	$0x100,%RDX

  (1050) 0x2742a6 CMP	%RDX,%RAX

  (1050) 0x2742a9 JNE	274260

(1051) 0x2742ab VADDPD	%ZMM12,%ZMM13,%ZMM12

(1051) 0x2742b1 VADDPD	%ZMM14,%ZMM15,%ZMM14

(1051) 0x2742b7 VADDPD	%ZMM12,%ZMM14,%ZMM12

(1051) 0x2742bd VEXTRACTF64X4	$0x1,%ZMM12,%YMM13

(1051) 0x2742c4 VADDPD	%ZMM13,%ZMM12,%ZMM12

(1051) 0x2742ca VEXTRACTF128	$0x1,%YMM12,%XMM13

(1051) 0x2742d0 VADDPD	%XMM13,%XMM12,%XMM12

(1051) 0x2742d5 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

(1051) 0x2742db VADDSD	%XMM13,%XMM12,%XMM12

(1051) 0x2742e0 CMP	%RCX,%RDI

(1051) 0x2742e3 JE	273db0

(1051) 0x2742e9 MOV	%RDI,%RDX

(1051) 0x2742ec TEST	$0x1c,%CL

(1051) 0x2742ef JE	274340

(1051) 0x2742f1 VMOVQ	%XMM12,%XMM12

(1051) 0x2742f6 NOPW	%CS:(%RAX,%RAX,1)

  (1053) 0x274300 VMOVUPD	(%R8,%RDI,8),%YMM13

  (1053) 0x274306 VFMADD231PD	(%RSI,%RDI,8),%YMM13,%YMM12

  (1053) 0x27430c ADD	$0x4,%RDI

  (1053) 0x274310 CMP	%RDI,%R12

  (1053) 0x274313 JNE	274300

(1051) 0x274315 VEXTRACTF128	$0x1,%YMM12,%XMM13

(1051) 0x27431b MOV	%R12,%RDX

(1051) 0x27431e VADDPD	%XMM13,%XMM12,%XMM12

(1051) 0x274323 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

(1051) 0x274329 VADDSD	%XMM13,%XMM12,%XMM12

(1051) 0x27432e CMP	%RCX,%R12

(1051) 0x274331 JE	273db0

(1051) 0x274337 NOPW	(%RAX,%RAX,1)

  (1052) 0x274340 VMOVSD	(%R8,%RDX,8),%XMM13

  (1052) 0x274346 VFMADD231SD	(%RSI,%RDX,8),%XMM13,%XMM12

  (1052) 0x27434c INC	%RDX

  (1052) 0x27434f CMP	%RDX,%RCX

  (1052) 0x274352 JNE	274340

(1051) 0x274354 JMP	273db0

0x274359 VMOVSD	0x10(%RBX),%XMM0

0x27435e ADD	$0x38,%RSP

0x274362 POP	%RBX

0x274363 POP	%R12

0x274365 POP	%R13

0x274367 POP	%R14

0x274369 POP	%R15

0x27436b POP	%RBP

0x27436c VZEROUPPER

0x27436f RET

Coverage (%)	Name	Source Location	Module
►67.09+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►30.11+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.87+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:170	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:378	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	DiracDeterminantRef.cpp:235-255
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:129-131
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:235-255

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.63 to 5.50 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.63 to 8.16 cycles (1.43x speedup).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

52% of SSE/AVX loads are used in vector version.
11% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

miniqmcreference::DiracDeterminantRef
>::recompute(qmcplusplus::ParticleSet&): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:236

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 680 bytes (85 double precision FP elements). The binary function is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	93
loop length	490
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	3
used zmm registers	6
nb stack references	6
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	11.00	11.00	11.00	11.00	2.75	2.75	2.75	2.75	1.50	1.50
cycles	4.17	4.17	4.17	4.17	4.17	4.17	11.00	11.00	11.00	11.00	2.75	2.75	2.75	2.75	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.63
Dispatch	11.00
Overall L1	11.63

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	60%
load	64%
store	33%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	37%
load	52%
store	11%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	41%
load	51%
store	16%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	44%
store	13%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.63 cycles. At this rate:

22% of peak load performance is reached (58.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.88 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.63 to 11.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the function is: 273c10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 276450 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9recomputeERNS1_11ParticleSetE>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x484(%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 273cac <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x9c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x100(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDDUP (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOVSXD 0x478(%RBX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RCX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMULSD 0x10(%RCX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
LEA (%RAX,%RAX,2),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD (%RDX,%RSI,8),%XMM2,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM3,(%RDX,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VADDSD 0x10(%RDX,%RSI,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM3,0x10(%RDX,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV 0x180(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDSD %XMM2,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231SD %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB231SD (%RCX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD (%RDX,%RAX,8),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 274359 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x749>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
TEST %EDX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 274359 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x749>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x480(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 274359 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x749>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x118(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD -0x6f6b5(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x6f63d(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x6f6e5(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x6912f(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x690f9(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x690c3(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x6908d(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69057(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69021(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x158(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xd8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x100(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x180(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x140(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %ECX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x20,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R14,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x478(%RBX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA 0xc0(%RSI),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RAX,2),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0xc0(%R8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x5,%EAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x8,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 273e26 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x216>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD 0x10(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	DiracDeterminantRef.cpp:235-255
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:129-131
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:235-255

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.63 to 5.50 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

52% of SSE/AVX loads are used in vector version.
11% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

miniqmcreference::DiracDeterminantRef
>::recompute(qmcplusplus::ParticleSet&): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:236

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction (2 inside FMA instructions)
7: multiply (2 inside FMA instructions)

The binary function is loading 680 bytes (85 double precision FP elements). The binary function is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	93
loop length	490
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	3
used zmm registers	6
nb stack references	6
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	11.00	11.00	11.00	11.00	2.75	2.75	2.75	2.75	1.50	1.50
cycles	4.17	4.17	4.17	4.17	4.17	4.17	11.00	11.00	11.00	11.00	2.75	2.75	2.75	2.75	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.63
Dispatch	11.00
Overall L1	11.63

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	60%
load	64%
store	33%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	37%
load	52%
store	11%
mul	66%
add-sub	25%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	41%
load	51%
store	16%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	28%
load	44%
store	13%
mul	20%
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.63 cycles. At this rate:

22% of peak load performance is reached (58.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.88 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 273c10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 276450 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9recomputeERNS1_11ParticleSetE>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x484(%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 273cac <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x9c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x100(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDDUP (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOVSXD 0x478(%RBX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RCX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMULSD 0x10(%RCX),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
LEA (%RAX,%RAX,2),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD (%RDX,%RSI,8),%XMM2,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM3,(%RDX,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VADDSD 0x10(%RDX,%RSI,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM3,0x10(%RDX,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV 0x180(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDSD %XMM2,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231SD %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMSUB231SD (%RCX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDSD (%RDX,%RAX,8),%XMM2,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 274359 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x749>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
TEST %EDX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 274359 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x749>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x480(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 274359 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x749>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x118(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD -0x6f6b5(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x6f63d(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x6f6e5(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x6912f(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x690f9(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x690c3(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x6908d(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69057(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD -0x69021(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x158(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xd8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x100(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x180(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x140(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %ECX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x20,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R14,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVSXD 0x478(%RBX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x3,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA 0xc0(%RSI),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RAX,2),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0xc0(%R8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x5,%EAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x8,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 273e26 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x216>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD 0x10(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus...–	0.07	0.12
▼Loop 1051 - inner_product.hpp:82-155 - exec–	0.00	0.01
○Loop 1049 - inner_product.hpp:155-155 - exec	0.06	0.10
○Loop 1050 - inner_product.hpp:82-83 - exec	0.02	0.03
○Loop 1052 - inner_product.hpp:82-83 - exec	0.00	0.00
○Loop 1054 - inner_product.hpp:155-155 - exec	0.00	0.00
○Loop 1055 - inner_product.hpp:155-155 - exec	0.00	0.00
○Loop 1053 - inner_product.hpp:82-83 - exec	0.00	0.00

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FMA

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CALL instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code