OV - exec - Function void miniqmcreference::MultiBsplineEvalRef::evaluate_v<double>(qmcplusplus::bspline_traits<double, 3u>::SplineType const*, double, double, double, double*, unsigned long)

	Function: void miniqmcreference::MultiBsplineEvalRef::evaluate_v<double>(qmcplusplus::bspline_traits ...	Module: exec	Source: MultiBsplineRef.hpp:41-73 [...]	Coverage (incl. loops): 25.30% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 41 - 73

--------------------------------------------------------------------------------

41: {

42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

57:   const intptr_t ys = spline_m->y_stride;

[...]

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

72:     }

73: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 924

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 63

--------------------------------------------------------------------------------

53:   if (x < 0)

[...]

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

--------------------------------------------------------------------------------

54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

0x25c5d0 PUSH	%RBP

0x25c5d1 MOV	%RSP,%RBP

0x25c5d4 PUSH	%R15

0x25c5d6 PUSH	%R14

0x25c5d8 PUSH	%R13

0x25c5da PUSH	%R12

0x25c5dc PUSH	%RBX

0x25c5dd AND	$-0x40,%RSP

0x25c5e1 SUB	$0x1c0,%RSP

0x25c5e8 VSUBSD	0x28(%RDI),%XMM0,%XMM0

0x25c5ed VSUBSD	0x50(%RDI),%XMM1,%XMM3

0x25c5f2 MOV	%RDX,%R8

0x25c5f5 MOV	%RSI,%R14

0x25c5f8 VMULSD	0x48(%RDI),%XMM0,%XMM1

0x25c5fd VXORPD	%XMM0,%XMM0,%XMM0

0x25c601 VUCOMISD	%XMM0,%XMM1

0x25c605 JAE	25c6a3

0x25c60b XOR	%R15D,%R15D

0x25c60e VXORPD	%XMM1,%XMM1,%XMM1

0x25c612 VMULSD	0x70(%RDI),%XMM3,%XMM3

0x25c617 VSUBSD	0x78(%RDI),%XMM2,%XMM2

0x25c61c VUCOMISD	%XMM0,%XMM3

0x25c620 JB	25c6e8

0x25c626 VROUNDSD	$0xb,%XMM3,%XMM3,%XMM0

0x25c62c MOV	0x60(%RDI),%EAX

0x25c62f VCVTTSD2SI	%XMM3,%EDX

0x25c633 VSUBSD	%XMM0,%XMM3,%XMM3

0x25c637 VMOVSD	-0x58507(%RIP),%XMM0

0x25c63f CMP	%EDX,%EAX

0x25c641 LEA	-0x1(%RAX),%ECX

0x25c644 SETG	%AL

0x25c647 CMOVG	%EDX,%ECX

0x25c64a KMOVD	%EAX,%K1

0x25c64e MOVSXD	%ECX,%R13

0x25c651 VMOVSD	%XMM3,%XMM0,%XMM0{%K1}

0x25c657 VMULSD	0x98(%RDI),%XMM2,%XMM3

0x25c65f VXORPD	%XMM2,%XMM2,%XMM2

0x25c663 VUCOMISD	%XMM2,%XMM3

0x25c667 JB	25c701

0x25c66d VROUNDSD	$0xb,%XMM3,%XMM3,%XMM2

0x25c673 MOV	0x88(%RDI),%EAX

0x25c679 VCVTTSD2SI	%XMM3,%EDX

0x25c67d VSUBSD	%XMM2,%XMM3,%XMM3

0x25c681 VMOVSD	-0x58551(%RIP),%XMM2

0x25c689 CMP	%EDX,%EAX

0x25c68b LEA	-0x1(%RAX),%ECX

0x25c68e SETG	%AL

0x25c691 CMOVG	%EDX,%ECX

0x25c694 KMOVD	%EAX,%K1

0x25c698 MOVSXD	%ECX,%RAX

0x25c69b VMOVSD	%XMM3,%XMM2,%XMM2{%K1}

0x25c6a1 JMP	25c703

0x25c6a3 VROUNDSD	$0xb,%XMM1,%XMM1,%XMM4

0x25c6a9 MOV	0x38(%RDI),%EAX

0x25c6ac VCVTTSD2SI	%XMM1,%EDX

0x25c6b0 VSUBSD	%XMM4,%XMM1,%XMM4

0x25c6b4 VMOVSD	-0x58584(%RIP),%XMM1

0x25c6bc CMP	%EDX,%EAX

0x25c6be LEA	-0x1(%RAX),%ECX

0x25c6c1 SETG	%AL

0x25c6c4 CMOVG	%EDX,%ECX

0x25c6c7 KMOVD	%EAX,%K1

0x25c6cb MOVSXD	%ECX,%R15

0x25c6ce VMOVSD	%XMM4,%XMM1,%XMM1{%K1}

0x25c6d4 VMULSD	0x70(%RDI),%XMM3,%XMM3

0x25c6d9 VSUBSD	0x78(%RDI),%XMM2,%XMM2

0x25c6de VUCOMISD	%XMM0,%XMM3

0x25c6e2 JAE	25c626

0x25c6e8 XOR	%R13D,%R13D

0x25c6eb VMULSD	0x98(%RDI),%XMM2,%XMM3

0x25c6f3 VXORPD	%XMM2,%XMM2,%XMM2

0x25c6f7 VUCOMISD	%XMM2,%XMM3

0x25c6fb JAE	25c66d

0x25c701 XOR	%EAX,%EAX

0x25c703 VMOVSD	-0x5847b(%RIP),%XMM4

0x25c70b VMOVSD	-0x58543(%RIP),%XMM3

0x25c713 VMOVDDUP	-0x5854b(%RIP),%XMM6

0x25c71b VMOVDDUP	%XMM1,%XMM9

0x25c71f VMULSD	%XMM1,%XMM1,%XMM8

0x25c723 VMULSD	%XMM4,%XMM1,%XMM7

0x25c727 VSUBSD	%XMM7,%XMM3,%XMM5

0x25c72b VBLENDPD	$0x1,%XMM5,%XMM6,%XMM5

0x25c731 VMULPD	%XMM5,%XMM9,%XMM10

0x25c735 VMOVAPD	-0x57efd(%RIP),%XMM5

0x25c73d VUNPCKLPD	%XMM8,%XMM9,%XMM9

0x25c742 VADDPD	%XMM5,%XMM10,%XMM11

0x25c746 VFMADD213PD	-0x57fdf(%RIP),%XMM11,%XMM9

0x25c74f VMOVAPD	%XMM9,0xa0(%RSP)

0x25c758 VSHUFPD	$0x1,%XMM10,%XMM10,%XMM9

0x25c75e VSUBSD	%XMM9,%XMM3,%XMM9

0x25c763 VFMADD213SD	%XMM3,%XMM1,%XMM9

0x25c768 VFMADD213SD	%XMM4,%XMM1,%XMM9

0x25c76d VMULSD	%XMM7,%XMM8,%XMM1

0x25c771 VMOVSD	%XMM9,0xb0(%RSP)

0x25c77a VMOVSD	%XMM1,0xb8(%RSP)

0x25c783 TEST	%R8,%R8

0x25c786 JE	25d112

0x25c78c VMULSD	%XMM4,%XMM0,%XMM1

0x25c790 VMULSD	%XMM0,%XMM0,%XMM8

0x25c794 MOV	0x20(%RDI),%RCX

0x25c798 MOV	0x10(%RDI),%R12

0x25c79c MOV	0x18(%RDI),%RBX

0x25c7a0 LEA	(,%R8,8),%RDX

0x25c7a8 MOV	%RDI,0x10(%RSP)

0x25c7ad MOV	%R14,%RDI

0x25c7b0 XOR	%ESI,%ESI

0x25c7b2 MOV	%R8,0x8(%RSP)

0x25c7b7 MOV	%RAX,0x18(%RSP)

0x25c7bc VSUBSD	%XMM1,%XMM3,%XMM7

0x25c7c0 VFMADD213SD	-0x58629(%RIP),%XMM0,%XMM7

0x25c7c9 MOV	%RCX,0x20(%RSP)

0x25c7ce VFMADD213SD	%XMM4,%XMM0,%XMM7

0x25c7d3 VMOVSD	%XMM7,0x88(%RSP)

0x25c7dc VMULSD	%XMM3,%XMM0,%XMM7

0x25c7e0 VADDSD	-0x586d8(%RIP),%XMM7,%XMM9

0x25c7e8 VSUBSD	%XMM7,%XMM3,%XMM7

0x25c7ec VFMADD213SD	-0x5868d(%RIP),%XMM8,%XMM9

0x25c7f5 VFMADD213SD	%XMM3,%XMM0,%XMM7

0x25c7fa VFMADD213SD	%XMM4,%XMM0,%XMM7

0x25c7ff VMULSD	%XMM1,%XMM8,%XMM0

0x25c803 VMULSD	%XMM4,%XMM2,%XMM1

0x25c807 VMOVDDUP	%XMM2,%XMM8

0x25c80b VSUBSD	%XMM1,%XMM3,%XMM4

0x25c80f VMOVSD	%XMM0,0x78(%RSP)

0x25c815 VMULSD	%XMM2,%XMM2,%XMM0

0x25c819 VBROADCASTSD	%XMM1,%YMM1

0x25c81e VMOVSD	%XMM7,0x90(%RSP)

0x25c827 VMOVSD	%XMM9,0x80(%RSP)

0x25c830 VBLENDPD	$0x1,%XMM4,%XMM6,%XMM4

0x25c836 VMULPD	%XMM4,%XMM8,%XMM4

0x25c83a VSHUFPD	$0x1,%XMM4,%XMM4,%XMM7

0x25c83f VSUBSD	%XMM7,%XMM3,%XMM7

0x25c843 VFMADD213SD	%XMM3,%XMM2,%XMM7

0x25c848 VADDPD	%XMM5,%XMM4,%XMM3

0x25c84c VUNPCKLPD	%XMM0,%XMM8,%XMM4

0x25c850 VMULPD	%XMM4,%XMM3,%XMM3

0x25c854 VMULSD	%XMM2,%XMM7,%XMM2

0x25c858 VBROADCASTSD	%XMM2,%YMM2

0x25c85d VBLENDPD	$0x4,%YMM2,%YMM3,%YMM2

0x25c863 VBROADCASTF128	-0x580fc(%RIP),%YMM3

0x25c86c VBLENDPD	$0x8,%YMM1,%YMM2,%YMM1

0x25c872 VPERM2F128	$0x20,%YMM0,%YMM3,%YMM0

0x25c878 VSHUFPD	$0x2,%YMM0,%YMM3,%YMM0

0x25c87d VADDPD	%YMM0,%YMM1,%YMM2

0x25c881 VMULPD	%YMM0,%YMM1,%YMM0

0x25c885 VMOVAPD	%ZMM0,0xc0(%RSP)

0x25c88d VBLENDPD	$0x8,%YMM0,%YMM2,%YMM0

0x25c893 VMOVAPD	%ZMM2,0x100(%RSP)

0x25c89b VMOVAPD	%YMM0,0x160(%RSP)

0x25c8a4 VZEROUPPER

0x25c8a7 CALL	2f6df0 <@plt_start@+0x1b0>

0x25c8ac LEA	0x1(%R13),%R8

0x25c8b0 LEA	0x2(%R13),%R10

0x25c8b4 LEA	0x3(%R13),%RSI

0x25c8b8 IMUL	%RBX,%R13

0x25c8bc IMUL	%R12,%R15

0x25c8c0 VMOVAPD	0x100(%RSP),%ZMM5

0x25c8c8 VBROADCASTSD	-0x58752(%RIP),%ZMM1

0x25c8d2 VBROADCASTSD	-0x58694(%RIP),%ZMM3

0x25c8dc VMOVAPD	0xc0(%RSP),%ZMM6

0x25c8e4 VMOVAPD	0x160(%RSP),%YMM14

0x25c8ed VMOVSD	0x78(%RSP),%XMM13

0x25c8f3 VMOVSD	0x80(%RSP),%XMM12

0x25c8fc VMOVSD	0x88(%RSP),%XMM11

0x25c905 MOV	0x8(%RSP),%RDI

0x25c90a SAL	$0x3,%R12

0x25c90e IMUL	%RBX,%R8

0x25c912 IMUL	%RBX,%R10

0x25c916 IMUL	%RBX,%RSI

0x25c91a LEA	(,%R13,8),%RAX

0x25c922 LEA	(%RAX,%R15,8),%R9

0x25c926 MOV	0x18(%RSP),%RAX

0x25c92b VPERMPD	%ZMM6,%ZMM3,%ZMM3

0x25c931 VPERMPD	%ZMM5,%ZMM1,%ZMM1

0x25c937 VEXTRACTF128	$0x1,%YMM5,%XMM2

0x25c93d VBROADCASTSD	%XMM5,%ZMM0

0x25c943 VPERMPD	$0x55,%YMM5,%YMM4

0x25c949 VPERMPD	$-0x56,%YMM5,%YMM5

0x25c94f VPERMPD	$-0x1,%YMM6,%YMM6

0x25c955 MOV	%RAX,%RCX

0x25c958 IMUL	0x20(%RSP),%RCX

0x25c95e LEA	0x8(,%RAX,8),%RDX

0x25c966 VBROADCASTSD	%XMM2,%ZMM2

0x25c96c LEA	(%R9,%RCX,8),%R11

0x25c970 SAL	$0x3,%RCX

0x25c974 LEA	(%RCX,%R13,8),%RAX

0x25c978 LEA	(%RAX,%R15,8),%RAX

0x25c97c MOV	%RAX,0x68(%RSP)

0x25c981 LEA	(%RCX,%R15,8),%RAX

0x25c985 LEA	(%RAX,%R10,8),%RBX

0x25c989 LEA	(%RAX,%R8,8),%RCX

0x25c98d LEA	(%RAX,%RSI,8),%RAX

0x25c991 SAL	$0x3,%R8

0x25c995 SAL	$0x3,%R10

0x25c999 SAL	$0x3,%RSI

0x25c99d LEA	(%R8,%R15,8),%R13

0x25c9a1 MOV	%RCX,%R8

0x25c9a4 MOV	0x10(%RSP),%RCX

0x25c9a9 MOV	%RBX,0x28(%RSP)

0x25c9ae LEA	(%R10,%R15,8),%RBX

0x25c9b2 MOV	%RAX,0x10(%RSP)

0x25c9b7 LEA	(%RSI,%R15,8),%RAX

0x25c9bb MOV	0x18(%RSP),%R15

0x25c9c0 MOV	0x20(%RSP),%RSI

0x25c9c5 MOV	%R13,%R10

0x25c9c8 MOV	0x8(%RCX),%RCX

0x25c9cc LEA	0x10(,%R15,8),%R13

0x25c9d4 LEA	0x18(,%R15,8),%R15

0x25c9dc IMUL	%RSI,%RDX

0x25c9e0 IMUL	%RSI,%R13

0x25c9e4 IMUL	%RSI,%R15

0x25c9e8 ADD	%RCX,%R13

0x25c9eb ADD	%RCX,%R15

0x25c9ee ADD	%RCX,%RDX

0x25c9f1 ADD	%RCX,0x68(%RSP)

0x25c9f6 ADD	%RCX,0x28(%RSP)

0x25c9fb ADD	%RCX,0x10(%RSP)

0x25ca00 ADD	%RCX,%R11

0x25ca03 ADD	%RCX,%R8

0x25ca06 LEA	(%R13,%R9,1),%RSI

0x25ca0b MOV	%RSI,0x48(%RSP)

0x25ca10 LEA	(%R15,%R9,1),%RSI

0x25ca14 ADD	%RDX,%R9

0x25ca17 MOV	%RSI,0x40(%RSP)

0x25ca1c LEA	(%RDX,%R10,1),%RSI

0x25ca20 MOV	%RSI,0x60(%RSP)

0x25ca25 LEA	(%R13,%R10,1),%RSI

0x25ca2a ADD	%R15,%R10

0x25ca2d MOV	%RSI,0x38(%RSP)

0x25ca32 LEA	(%RDX,%RBX,1),%RSI

0x25ca36 ADD	%RAX,%RDX

0x25ca39 MOV	%RSI,0x58(%RSP)

0x25ca3e LEA	(%R13,%RBX,1),%RSI

0x25ca43 ADD	%R15,%RBX

0x25ca46 ADD	%RAX,%R13

0x25ca49 ADD	%RAX,%R15

0x25ca4c XOR	%EAX,%EAX

0x25ca4e MOV	%RSI,0x30(%RSP)

0x25ca53 MOV	%RDI,%RSI

0x25ca56 MOV	%RBX,0x50(%RSP)

0x25ca5b MOV	%RDI,%RBX

0x25ca5e AND	$-0x8,%RBX

0x25ca62 AND	$-0x4,%RSI

0x25ca66 JMP	25caeb

0x25ca6b NOPL	(%RAX,%RAX,1)

(852) 0x25ca70 MOV	0x98(%RSP),%RAX

(852) 0x25ca78 MOV	0x70(%RSP),%R11

(852) 0x25ca7d MOV	0x100(%RSP),%R9

(852) 0x25ca85 MOV	0x18(%RSP),%R8

(852) 0x25ca8a MOV	0xc0(%RSP),%R10

(852) 0x25ca92 ADD	%R12,0x48(%RSP)

(852) 0x25ca97 ADD	%R12,0x40(%RSP)

(852) 0x25ca9c ADD	%R12,0x68(%RSP)

(852) 0x25caa1 ADD	%R12,0x60(%RSP)

(852) 0x25caa6 ADD	%R12,0x38(%RSP)

(852) 0x25caab ADD	%R12,0x28(%RSP)

(852) 0x25cab0 ADD	%R12,0x58(%RSP)

(852) 0x25cab5 ADD	%R12,0x30(%RSP)

(852) 0x25caba ADD	%R12,0x50(%RSP)

(852) 0x25cabf ADD	%R12,0x10(%RSP)

(852) 0x25cac4 MOV	0x8(%RSP),%RDI

(852) 0x25cac9 ADD	%R12,%RDX

(852) 0x25cacc ADD	%R12,%R13

(852) 0x25cacf ADD	%R12,%R15

(852) 0x25cad2 INC	%RAX

(852) 0x25cad5 ADD	%R12,%R11

(852) 0x25cad8 ADD	%R12,%R9

(852) 0x25cadb ADD	%R12,%R8

(852) 0x25cade ADD	%R12,%R10

(852) 0x25cae1 CMP	$0x4,%RAX

(852) 0x25cae5 JE	25d112

(852) 0x25caeb VMOVSD	0xa0(%RSP,%RAX,8),%XMM7

(852) 0x25caf4 MOV	%R10,0xc0(%RSP)

(852) 0x25cafc MOV	%R8,0x18(%RSP)

(852) 0x25cb01 MOV	%R9,0x100(%RSP)

(852) 0x25cb09 MOV	%R11,0x70(%RSP)

(852) 0x25cb0e MOV	%RAX,0x98(%RSP)

(852) 0x25cb16 VMULSD	%XMM7,%XMM11,%XMM8

(852) 0x25cb1a CMP	$0x4,%RDI

(852) 0x25cb1e JAE	25cb30

(852) 0x25cb20 XOR	%EAX,%EAX

(852) 0x25cb22 JMP	25cc0a

0x25cb27 NOPW	(%RAX,%RAX,1)

(852) 0x25cb30 CMP	$0x8,%RDI

(852) 0x25cb34 JAE	25cb40

(852) 0x25cb36 XOR	%ECX,%ECX

(852) 0x25cb38 JMP	25cbb0

0x25cb3a NOPW	(%RAX,%RAX,1)

(852) 0x25cb40 MOV	0x48(%RSP),%RCX

(852) 0x25cb45 MOV	0x40(%RSP),%R8

(852) 0x25cb4a VBROADCASTSD	%XMM8,%ZMM9

(852) 0x25cb50 XOR	%EAX,%EAX

(852) 0x25cb52 NOPW	%CS:(%RAX,%RAX,1)

  (848) 0x25cb60 VMULPD	(%R11,%RAX,8),%ZMM0,%ZMM10

  (848) 0x25cb67 VFMADD231PD	(%R9,%RAX,8),%ZMM1,%ZMM10

  (848) 0x25cb6e VFMADD231PD	(%RCX,%RAX,8),%ZMM2,%ZMM10

  (848) 0x25cb75 VFMADD231PD	(%R8,%RAX,8),%ZMM3,%ZMM10

  (848) 0x25cb7c VFMADD213PD	(%R14,%RAX,8),%ZMM9,%ZMM10

  (848) 0x25cb83 VMOVUPD	%ZMM10,(%R14,%RAX,8)

  (848) 0x25cb8a ADD	$0x8,%RAX

  (848) 0x25cb8e CMP	%RAX,%RBX

  (848) 0x25cb91 JNE	25cb60

(852) 0x25cb93 CMP	%RDI,%RBX

(852) 0x25cb96 JE	25cc8d

(852) 0x25cb9c TESTB	$0x4,0x8(%RSP)

(852) 0x25cba1 MOV	%RBX,%RCX

(852) 0x25cba4 MOV	%RBX,%RAX

(852) 0x25cba7 JE	25cc0a

(852) 0x25cba9 NOPL	(%RAX)

(852) 0x25cbb0 MOV	0x100(%RSP),%RAX

(852) 0x25cbb8 MOV	0x70(%RSP),%RDI

(852) 0x25cbbd MOV	0x48(%RSP),%R8

(852) 0x25cbc2 MOV	0x40(%RSP),%R9

(852) 0x25cbc7 VBROADCASTSD	%XMM8,%YMM9

(852) 0x25cbcc NOPL	(%RAX)

  (860) 0x25cbd0 VMULPD	(%RDI,%RCX,8),%YMM0,%YMM10

  (860) 0x25cbd5 VFMADD231PD	(%RAX,%RCX,8),%YMM4,%YMM10

  (860) 0x25cbdb VFMADD231PD	(%R8,%RCX,8),%YMM5,%YMM10

  (860) 0x25cbe1 VFMADD231PD	(%R9,%RCX,8),%YMM6,%YMM10

  (860) 0x25cbe7 VFMADD213PD	(%R14,%RCX,8),%YMM9,%YMM10

  (860) 0x25cbed VMOVUPD	%YMM10,(%R14,%RCX,8)

  (860) 0x25cbf3 ADD	$0x4,%RCX

  (860) 0x25cbf7 CMP	%RCX,%RSI

  (860) 0x25cbfa JNE	25cbd0

(852) 0x25cbfc MOV	%RSI,%RAX

(852) 0x25cbff CMP	%RSI,0x8(%RSP)

(852) 0x25cc04 JE	25cc8d

(852) 0x25cc0a MOV	0x40(%RSP),%R8

(852) 0x25cc0f MOV	0x100(%RSP),%R10

(852) 0x25cc17 MOV	0x8(%RSP),%RCX

(852) 0x25cc1c MOV	0x48(%RSP),%R11

(852) 0x25cc21 LEA	(%R14,%RAX,8),%RDI

(852) 0x25cc25 LEA	(%R8,%RAX,8),%R9

(852) 0x25cc29 LEA	(%R10,%RAX,8),%R8

(852) 0x25cc2d MOV	0x68(%RSP),%R10

(852) 0x25cc32 LEA	(%R11,%RAX,8),%R11

(852) 0x25cc36 SUB	%RAX,%RCX

(852) 0x25cc39 LEA	(%R10,%RAX,8),%RAX

(852) 0x25cc3d XOR	%R10D,%R10D

  (859) 0x25cc40 VMOVSD	(%R11,%R10,8),%XMM9

  (859) 0x25cc46 VMOVSD	(%RAX,%R10,8),%XMM10

  (859) 0x25cc4c VMOVHPD	(%R9,%R10,8),%XMM9,%XMM9

  (859) 0x25cc52 VMOVHPD	(%R8,%R10,8),%XMM10,%XMM10

  (859) 0x25cc58 VINSERTF128	$0x1,%XMM9,%YMM10,%YMM9

  (859) 0x25cc5e VMULPD	%YMM9,%YMM14,%YMM9

  (859) 0x25cc63 VEXTRACTF128	$0x1,%YMM9,%XMM10

  (859) 0x25cc69 VADDPD	%XMM10,%XMM9,%XMM9

  (859) 0x25cc6e VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

  (859) 0x25cc74 VADDSD	%XMM10,%XMM9,%XMM9

  (859) 0x25cc79 VFMADD213SD	(%RDI,%R10,8),%XMM8,%XMM9

  (859) 0x25cc7f VMOVSD	%XMM9,(%RDI,%R10,8)

  (859) 0x25cc85 INC	%R10

  (859) 0x25cc88 CMP	%R10,%RCX

  (859) 0x25cc8b JNE	25cc40

(852) 0x25cc8d MOV	0x8(%RSP),%RCX

(852) 0x25cc92 VMULSD	%XMM7,%XMM12,%XMM8

(852) 0x25cc96 CMP	$0x4,%RCX

(852) 0x25cc9a JAE	25ccb0

(852) 0x25cc9c XOR	%EAX,%EAX

(852) 0x25cc9e JMP	25cd8a

0x25cca3 NOPW	%CS:(%RAX,%RAX,1)

(852) 0x25ccb0 CMP	$0x8,%RCX

(852) 0x25ccb4 JAE	25ccc0

(852) 0x25ccb6 XOR	%ECX,%ECX

(852) 0x25ccb8 JMP	25cd30

0x25ccba NOPW	(%RAX,%RAX,1)

(852) 0x25ccc0 MOV	0x18(%RSP),%RDI

(852) 0x25ccc5 MOV	0xc0(%RSP),%R8

(852) 0x25cccd MOV	0x60(%RSP),%R9

(852) 0x25ccd2 MOV	0x38(%RSP),%R10

(852) 0x25ccd7 VBROADCASTSD	%XMM8,%ZMM9

(852) 0x25ccdd XOR	%EAX,%EAX

(852) 0x25ccdf NOP

  (849) 0x25cce0 VMULPD	(%RDI,%RAX,8),%ZMM0,%ZMM10

  (849) 0x25cce7 VFMADD231PD	(%R9,%RAX,8),%ZMM1,%ZMM10

  (849) 0x25ccee VFMADD231PD	(%R10,%RAX,8),%ZMM2,%ZMM10

  (849) 0x25ccf5 VFMADD231PD	(%R8,%RAX,8),%ZMM3,%ZMM10

  (849) 0x25ccfc VFMADD213PD	(%R14,%RAX,8),%ZMM9,%ZMM10

  (849) 0x25cd03 VMOVUPD	%ZMM10,(%R14,%RAX,8)

  (849) 0x25cd0a ADD	$0x8,%RAX

  (849) 0x25cd0e CMP	%RAX,%RBX

  (849) 0x25cd11 JNE	25cce0

(852) 0x25cd13 CMP	%RCX,%RBX

(852) 0x25cd16 JE	25ce1d

(852) 0x25cd1c TESTB	$0x4,0x8(%RSP)

(852) 0x25cd21 MOV	%RBX,%RCX

(852) 0x25cd24 MOV	%RBX,%RAX

(852) 0x25cd27 JE	25cd8a

(852) 0x25cd29 NOPL	(%RAX)

(852) 0x25cd30 MOV	0x18(%RSP),%RAX

(852) 0x25cd35 MOV	0xc0(%RSP),%RDI

(852) 0x25cd3d MOV	0x60(%RSP),%R8

(852) 0x25cd42 MOV	0x38(%RSP),%R9

(852) 0x25cd47 VBROADCASTSD	%XMM8,%YMM9

(852) 0x25cd4c NOPL	(%RAX)

  (858) 0x25cd50 VMULPD	(%RAX,%RCX,8),%YMM0,%YMM10

  (858) 0x25cd55 VFMADD231PD	(%R8,%RCX,8),%YMM4,%YMM10

  (858) 0x25cd5b VFMADD231PD	(%R9,%RCX,8),%YMM5,%YMM10

  (858) 0x25cd61 VFMADD231PD	(%RDI,%RCX,8),%YMM6,%YMM10

  (858) 0x25cd67 VFMADD213PD	(%R14,%RCX,8),%YMM9,%YMM10

  (858) 0x25cd6d VMOVUPD	%YMM10,(%R14,%RCX,8)

  (858) 0x25cd73 ADD	$0x4,%RCX

  (858) 0x25cd77 CMP	%RCX,%RSI

  (858) 0x25cd7a JNE	25cd50

(852) 0x25cd7c MOV	%RSI,%RAX

(852) 0x25cd7f CMP	%RSI,0x8(%RSP)

(852) 0x25cd84 JE	25ce1d

(852) 0x25cd8a MOV	0xc0(%RSP),%R8

(852) 0x25cd92 MOV	0x20(%RSP),%R10

(852) 0x25cd97 MOV	0x8(%RSP),%RCX

(852) 0x25cd9c MOV	0x38(%RSP),%R11

(852) 0x25cda1 LEA	(%R14,%RAX,8),%RDI

(852) 0x25cda5 LEA	(%R8,%RAX,8),%R9

(852) 0x25cda9 LEA	(%R10,%RAX,1),%R8

(852) 0x25cdad MOV	0x18(%RSP),%R10

(852) 0x25cdb2 SUB	%RAX,%RCX

(852) 0x25cdb5 LEA	(%R11,%RAX,8),%R11

(852) 0x25cdb9 LEA	(%R10,%R8,8),%R8

(852) 0x25cdbd LEA	(%R10,%RAX,8),%RAX

(852) 0x25cdc1 XOR	%R10D,%R10D

(852) 0x25cdc4 NOPW	%CS:(%RAX,%RAX,1)

  (857) 0x25cdd0 VMOVSD	(%R11,%R10,8),%XMM9

  (857) 0x25cdd6 VMOVSD	(%RAX,%R10,8),%XMM10

  (857) 0x25cddc VMOVHPD	(%R9,%R10,8),%XMM9,%XMM9

  (857) 0x25cde2 VMOVHPD	(%R8,%R10,8),%XMM10,%XMM10

  (857) 0x25cde8 VINSERTF128	$0x1,%XMM9,%YMM10,%YMM9

  (857) 0x25cdee VMULPD	%YMM9,%YMM14,%YMM9

  (857) 0x25cdf3 VEXTRACTF128	$0x1,%YMM9,%XMM10

  (857) 0x25cdf9 VADDPD	%XMM10,%XMM9,%XMM9

  (857) 0x25cdfe VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

  (857) 0x25ce04 VADDSD	%XMM10,%XMM9,%XMM9

  (857) 0x25ce09 VFMADD213SD	(%RDI,%R10,8),%XMM8,%XMM9

  (857) 0x25ce0f VMOVSD	%XMM9,(%RDI,%R10,8)

  (857) 0x25ce15 INC	%R10

  (857) 0x25ce18 CMP	%R10,%RCX

  (857) 0x25ce1b JNE	25cdd0

(852) 0x25ce1d VMULSD	0x90(%RSP),%XMM7,%XMM8

(852) 0x25ce26 MOV	0x8(%RSP),%RCX

(852) 0x25ce2b CMP	$0x4,%RCX

(852) 0x25ce2f JAE	25ce40

(852) 0x25ce31 XOR	%EAX,%EAX

(852) 0x25ce33 JMP	25cf1a

0x25ce38 NOPL	(%RAX,%RAX,1)

(852) 0x25ce40 CMP	$0x8,%RCX

(852) 0x25ce44 JAE	25ce50

(852) 0x25ce46 XOR	%ECX,%ECX

(852) 0x25ce48 JMP	25cec0

0x25ce4a NOPW	(%RAX,%RAX,1)

(852) 0x25ce50 MOV	0x28(%RSP),%RDI

(852) 0x25ce55 MOV	0x50(%RSP),%R8

(852) 0x25ce5a MOV	0x58(%RSP),%R9

(852) 0x25ce5f MOV	0x30(%RSP),%R10

(852) 0x25ce64 VBROADCASTSD	%XMM8,%ZMM9

(852) 0x25ce6a XOR	%EAX,%EAX

(852) 0x25ce6c NOPL	(%RAX)

  (850) 0x25ce70 VMULPD	(%RDI,%RAX,8),%ZMM0,%ZMM10

  (850) 0x25ce77 VFMADD231PD	(%R9,%RAX,8),%ZMM1,%ZMM10

  (850) 0x25ce7e VFMADD231PD	(%R10,%RAX,8),%ZMM2,%ZMM10

  (850) 0x25ce85 VFMADD231PD	(%R8,%RAX,8),%ZMM3,%ZMM10

  (850) 0x25ce8c VFMADD213PD	(%R14,%RAX,8),%ZMM9,%ZMM10

  (850) 0x25ce93 VMOVUPD	%ZMM10,(%R14,%RAX,8)

  (850) 0x25ce9a ADD	$0x8,%RAX

  (850) 0x25ce9e CMP	%RAX,%RBX

  (850) 0x25cea1 JNE	25ce70

(852) 0x25cea3 CMP	%RCX,%RBX

(852) 0x25cea6 JE	25cfad

(852) 0x25ceac TESTB	$0x4,0x8(%RSP)

(852) 0x25ceb1 MOV	%RBX,%RCX

(852) 0x25ceb4 MOV	%RBX,%RAX

(852) 0x25ceb7 JE	25cf1a

(852) 0x25ceb9 NOPL	(%RAX)

(852) 0x25cec0 MOV	0x28(%RSP),%RAX

(852) 0x25cec5 MOV	0x50(%RSP),%RDI

(852) 0x25ceca MOV	0x58(%RSP),%R8

(852) 0x25cecf MOV	0x30(%RSP),%R9

(852) 0x25ced4 VBROADCASTSD	%XMM8,%YMM9

(852) 0x25ced9 NOPL	(%RAX)

  (856) 0x25cee0 VMULPD	(%RAX,%RCX,8),%YMM0,%YMM10

  (856) 0x25cee5 VFMADD231PD	(%R8,%RCX,8),%YMM4,%YMM10

  (856) 0x25ceeb VFMADD231PD	(%R9,%RCX,8),%YMM5,%YMM10

  (856) 0x25cef1 VFMADD231PD	(%RDI,%RCX,8),%YMM6,%YMM10

  (856) 0x25cef7 VFMADD213PD	(%R14,%RCX,8),%YMM9,%YMM10

  (856) 0x25cefd VMOVUPD	%YMM10,(%R14,%RCX,8)

  (856) 0x25cf03 ADD	$0x4,%RCX

  (856) 0x25cf07 CMP	%RCX,%RSI

  (856) 0x25cf0a JNE	25cee0

(852) 0x25cf0c MOV	%RSI,%RAX

(852) 0x25cf0f CMP	%RSI,0x8(%RSP)

(852) 0x25cf14 JE	25cfad

(852) 0x25cf1a MOV	0x50(%RSP),%R8

(852) 0x25cf1f MOV	0x20(%RSP),%R10

(852) 0x25cf24 MOV	0x8(%RSP),%RCX

(852) 0x25cf29 MOV	0x30(%RSP),%R11

(852) 0x25cf2e LEA	(%R14,%RAX,8),%RDI

(852) 0x25cf32 LEA	(%R8,%RAX,8),%R9

(852) 0x25cf36 LEA	(%R10,%RAX,1),%R8

(852) 0x25cf3a MOV	0x28(%RSP),%R10

(852) 0x25cf3f SUB	%RAX,%RCX

(852) 0x25cf42 LEA	(%R11,%RAX,8),%R11

(852) 0x25cf46 LEA	(%R10,%R8,8),%R8

(852) 0x25cf4a LEA	(%R10,%RAX,8),%RAX

(852) 0x25cf4e XOR	%R10D,%R10D

(852) 0x25cf51 NOPW	%CS:(%RAX,%RAX,1)

  (855) 0x25cf60 VMOVSD	(%R11,%R10,8),%XMM9

  (855) 0x25cf66 VMOVSD	(%RAX,%R10,8),%XMM10

  (855) 0x25cf6c VMOVHPD	(%R9,%R10,8),%XMM9,%XMM9

  (855) 0x25cf72 VMOVHPD	(%R8,%R10,8),%XMM10,%XMM10

  (855) 0x25cf78 VINSERTF128	$0x1,%XMM9,%YMM10,%YMM9

  (855) 0x25cf7e VMULPD	%YMM9,%YMM14,%YMM9

  (855) 0x25cf83 VEXTRACTF128	$0x1,%YMM9,%XMM10

  (855) 0x25cf89 VADDPD	%XMM10,%XMM9,%XMM9

  (855) 0x25cf8e VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

  (855) 0x25cf94 VADDSD	%XMM10,%XMM9,%XMM9

  (855) 0x25cf99 VFMADD213SD	(%RDI,%R10,8),%XMM8,%XMM9

  (855) 0x25cf9f VMOVSD	%XMM9,(%RDI,%R10,8)

  (855) 0x25cfa5 INC	%R10

  (855) 0x25cfa8 CMP	%R10,%RCX

  (855) 0x25cfab JNE	25cf60

(852) 0x25cfad MOV	0x8(%RSP),%RCX

(852) 0x25cfb2 VMULSD	%XMM7,%XMM13,%XMM7

(852) 0x25cfb6 CMP	$0x4,%RCX

(852) 0x25cfba JAE	25cfd0

(852) 0x25cfbc XOR	%EAX,%EAX

(852) 0x25cfbe JMP	25d08b

0x25cfc3 NOPW	%CS:(%RAX,%RAX,1)

(852) 0x25cfd0 CMP	$0x8,%RCX

(852) 0x25cfd4 JAE	25cfe0

(852) 0x25cfd6 XOR	%ECX,%ECX

(852) 0x25cfd8 JMP	25d040

0x25cfda NOPW	(%RAX,%RAX,1)

(852) 0x25cfe0 MOV	0x10(%RSP),%RDI

(852) 0x25cfe5 VBROADCASTSD	%XMM7,%ZMM8

(852) 0x25cfeb XOR	%EAX,%EAX

(852) 0x25cfed NOPL	(%RAX)

  (851) 0x25cff0 VMULPD	(%RDI,%RAX,8),%ZMM0,%ZMM9

  (851) 0x25cff7 VFMADD231PD	(%RDX,%RAX,8),%ZMM1,%ZMM9

  (851) 0x25cffe VFMADD231PD	(%R13,%RAX,8),%ZMM2,%ZMM9

  (851) 0x25d006 VFMADD231PD	(%R15,%RAX,8),%ZMM3,%ZMM9

  (851) 0x25d00d VFMADD213PD	(%R14,%RAX,8),%ZMM8,%ZMM9

  (851) 0x25d014 VMOVUPD	%ZMM9,(%R14,%RAX,8)

  (851) 0x25d01b ADD	$0x8,%RAX

  (851) 0x25d01f CMP	%RAX,%RBX

  (851) 0x25d022 JNE	25cff0

(852) 0x25d024 CMP	%RCX,%RBX

(852) 0x25d027 JE	25ca70

(852) 0x25d02d TESTB	$0x4,0x8(%RSP)

(852) 0x25d032 MOV	%RBX,%RCX

(852) 0x25d035 MOV	%RBX,%RAX

(852) 0x25d038 JE	25d08b

(852) 0x25d03a NOPW	(%RAX,%RAX,1)

(852) 0x25d040 MOV	0x10(%RSP),%RAX

(852) 0x25d045 VBROADCASTSD	%XMM7,%YMM8

(852) 0x25d04a NOPW	(%RAX,%RAX,1)

  (854) 0x25d050 VMULPD	(%RAX,%RCX,8),%YMM0,%YMM9

  (854) 0x25d055 VFMADD231PD	(%RDX,%RCX,8),%YMM4,%YMM9

  (854) 0x25d05b VFMADD231PD	(%R13,%RCX,8),%YMM5,%YMM9

  (854) 0x25d062 VFMADD231PD	(%R15,%RCX,8),%YMM6,%YMM9

  (854) 0x25d068 VFMADD213PD	(%R14,%RCX,8),%YMM8,%YMM9

  (854) 0x25d06e VMOVUPD	%YMM9,(%R14,%RCX,8)

  (854) 0x25d074 ADD	$0x4,%RCX

  (854) 0x25d078 CMP	%RCX,%RSI

  (854) 0x25d07b JNE	25d050

(852) 0x25d07d MOV	%RSI,%RAX

(852) 0x25d080 CMP	%RSI,0x8(%RSP)

(852) 0x25d085 JE	25ca70

(852) 0x25d08b MOV	0x20(%RSP),%R8

(852) 0x25d090 MOV	0x8(%RSP),%RCX

(852) 0x25d095 MOV	0x10(%RSP),%R10

(852) 0x25d09a LEA	(%R14,%RAX,8),%RDI

(852) 0x25d09e LEA	(%R15,%RAX,8),%R9

(852) 0x25d0a2 LEA	(%R13,%RAX,8),%R11

(852) 0x25d0a7 ADD	%RAX,%R8

(852) 0x25d0aa SUB	%RAX,%RCX

(852) 0x25d0ad LEA	(%R10,%RAX,8),%RAX

(852) 0x25d0b1 LEA	(%R10,%R8,8),%R8

(852) 0x25d0b5 XOR	%R10D,%R10D

(852) 0x25d0b8 NOPL	(%RAX,%RAX,1)

  (853) 0x25d0c0 VMOVSD	(%R11,%R10,8),%XMM8

  (853) 0x25d0c6 VMOVSD	(%RAX,%R10,8),%XMM9

  (853) 0x25d0cc VMOVHPD	(%R9,%R10,8),%XMM8,%XMM8

  (853) 0x25d0d2 VMOVHPD	(%R8,%R10,8),%XMM9,%XMM9

  (853) 0x25d0d8 VINSERTF128	$0x1,%XMM8,%YMM9,%YMM8

  (853) 0x25d0de VMULPD	%YMM8,%YMM14,%YMM8

  (853) 0x25d0e3 VEXTRACTF128	$0x1,%YMM8,%XMM9

  (853) 0x25d0e9 VADDPD	%XMM9,%XMM8,%XMM8

  (853) 0x25d0ee VSHUFPD	$0x1,%XMM8,%XMM8,%XMM9

  (853) 0x25d0f4 VADDSD	%XMM9,%XMM8,%XMM8

  (853) 0x25d0f9 VFMADD213SD	(%RDI,%R10,8),%XMM7,%XMM8

  (853) 0x25d0ff VMOVSD	%XMM8,(%RDI,%R10,8)

  (853) 0x25d105 INC	%R10

  (853) 0x25d108 CMP	%R10,%RCX

  (853) 0x25d10b JNE	25d0c0

(852) 0x25d10d JMP	25ca70

0x25d112 LEA	-0x28(%RBP),%RSP

0x25d116 POP	%RBX

0x25d117 POP	%R12

0x25d119 POP	%R13

0x25d11b POP	%R14

0x25d11d POP	%R15

0x25d11f POP	%RBP

0x25d120 VZEROUPPER

0x25d123 RET

0x25d124 INT	$0x3

0x25d125 INT	$0x3

0x25d126 INT	$0x3

0x25d127 INT	$0x3

0x25d128 INT	$0x3

0x25d129 INT	$0x3

0x25d12a INT	$0x3

0x25d12b INT	$0x3

0x25d12c INT	$0x3

0x25d12d INT	$0x3

0x25d12e INT	$0x3

0x25d12f INT	$0x3

Coverage (%)	Name	Source Location	Module
►96.05+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:175	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	qmcplusplus::SPOSet::evaluateD[...]	OhmmsVector.h:178	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.06+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:175	exec
○	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	qmcplusplus::SPOSet::evaluateD[...]	OhmmsVector.h:178	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	MultiBsplineRef.hpp:41-73
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:41-49,57,63-73
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 33.75 to 20.75 cycles (1.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 33.75 to 21.24 cycles (1.59x speedup).

Details

27% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

18% of SSE/AVX loads are used in vector version.
14% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
21% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX fused multiply-add instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
KMOVD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
VMOVAPD: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
VUCOMISD: 5 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:63

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

45 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 67 FP arithmetical operations:

32: addition or subtraction (10 inside FMA instructions)
35: multiply (10 inside FMA instructions)

The binary function is loading 508 bytes (63 double precision FP elements). The binary function is storing 360 bytes (45 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	274
nb uops	270
loop length	1281
used x86 registers	16
used mmx registers	0
used xmm registers	14
used ymm registers	8
used zmm registers	6
nb stack references	24
ADD-SUB / MUL ratio	0.89

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.75 cycles
front end	33.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.50	14.50	14.50	14.50	14.50	14.50	17.50	17.50	17.50	17.50	21.50	21.50	21.50	21.50	10.00	10.00
cycles	14.50	14.50	14.50	14.50	14.50	14.50	17.50	17.50	17.50	17.50	21.50	21.50	21.50	21.50	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	33.75
Dispatch	21.50
Overall L1	33.75

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	32%
load	20%
store	40%
mul	21%
add-sub	17%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	27%
load	18%
store	14%
mul	21%
add-sub	16%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	22%
load	21%
store	35%
mul	16%
add-sub	16%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	20%
load	20%
store	20%
mul	16%
add-sub	15%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 33.75 cycles. At this rate:

5% of peak load performance is reached (15.05 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 33.75 to 21.50 cycles (1.57x speedup).

ASM code

In the binary file, the address of the function is: 25c5d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBSD 0x28(%RDI),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x50(%RDI),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMULSD 0x48(%RDI),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 25c6a3 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0xd3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMULSD 0x70(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD 0x78(%RDI),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 25c6e8 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VROUNDSD $0xb,%XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x60(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTTSD2SI %XMM3,%EDX	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	4	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD -0x58507(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SETG %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %EDX,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
MOVSXD %ECX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,%XMM0,%XMM0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD 0x98(%RDI),%XMM2,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM2,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 25c701 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x131>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VROUNDSD $0xb,%XMM3,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x88(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTTSD2SI %XMM3,%EDX	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD -0x58551(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SETG %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %EDX,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
MOVSXD %ECX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 25c703 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x133>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VROUNDSD $0xb,%XMM1,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTTSD2SI %XMM1,%EDX	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	4	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD -0x58584(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SETG %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %EDX,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
MOVSXD %ECX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM4,%XMM1,%XMM1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD 0x70(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD 0x78(%RDI),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 25c626 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x56>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMULSD 0x98(%RDI),%XMM2,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM2,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 25c66d <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSD -0x5847b(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x58543(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x5854b(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VBLENDPD $0x1,%XMM5,%XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (25.0%)
VMULPD %XMM5,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x57efd(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VUNPCKLPD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM5,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VFMADD213PD -0x57fdf(%RIP),%XMM11,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVAPD %XMM9,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM9,%XMM3,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM3,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM7,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM9,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
TEST %R8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 25d112 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0xb42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD %XMM4,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x20(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R8,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R8,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD -0x58629(%RIP),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM3,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD -0x586d8(%RIP),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD -0x5868d(%RIP),%XMM8,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM3,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM1,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM9,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBLENDPD $0x1,%XMM4,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (25.0%)
VMULPD %XMM4,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM4,%XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM7,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM3,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDPD %XMM5,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM0,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULPD %XMM4,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMULSD %XMM2,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBLENDPD $0x4,%YMM2,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (50.0%)
VBROADCASTF128 -0x580fc(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	vect (25.0%)
VBLENDPD $0x8,%YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (50.0%)
VPERM2F128 $0x20,%YMM0,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x2,%YMM0,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %ZMM0,0xc0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VBLENDPD $0x8,%YMM0,%YMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (50.0%)
VMOVAPD %ZMM2,0x100(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPD %YMM0,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2f6df0 <@plt_start@+0x1b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R13),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2(%R13),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x3(%R13),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RBX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R12,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVAPD 0x100(%RSP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD -0x58752(%RIP),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x58694(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD 0xc0(%RSP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x160(%RSP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x78(%RSP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x80(%RSP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x88(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL %RBX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (,%R13,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R15,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPERMPD %ZMM6,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMPD %ZMM5,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VBROADCASTSD %XMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPERMPD $0x55,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPERMPD $-0x56,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPERMPD $-0x1,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL 0x20(%RSP),%RCX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
LEA 0x8(,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA (%R9,%RCX,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%R13,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R10,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RSI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%R15,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R10,%R15,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RSI,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x10(,%R15,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(,%R15,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RSI,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RSI,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RSI,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RCX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,0x68(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RCX,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RCX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RCX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R9,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R15,%R9,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R13,%R10,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R15,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDX,%RBX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R13,%RBX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 25caeb <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x51b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	MultiBsplineRef.hpp:41-73
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:41-49,57,63-73
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

27% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

18% of SSE/AVX loads are used in vector version.
14% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
21% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX fused multiply-add instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
KMOVD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:63
VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
VMOVAPD: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:924
VUCOMISD: 5 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:63

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:60

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 67 FP arithmetical operations:

32: addition or subtraction (10 inside FMA instructions)
35: multiply (10 inside FMA instructions)

The binary function is loading 508 bytes (63 double precision FP elements). The binary function is storing 360 bytes (45 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	274
nb uops	270
loop length	1281
used x86 registers	16
used mmx registers	0
used xmm registers	14
used ymm registers	8
used zmm registers	6
nb stack references	24
ADD-SUB / MUL ratio	0.89

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.75 cycles
front end	33.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.50	14.50	14.50	14.50	14.50	14.50	17.50	17.50	17.50	17.50	21.50	21.50	21.50	21.50	10.00	10.00
cycles	14.50	14.50	14.50	14.50	14.50	14.50	17.50	17.50	17.50	17.50	21.50	21.50	21.50	21.50	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	33.75
Dispatch	21.50
Overall L1	33.75

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	32%
load	20%
store	40%
mul	21%
add-sub	17%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	27%
load	18%
store	14%
mul	21%
add-sub	16%
fma	11%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	22%
load	21%
store	35%
mul	16%
add-sub	16%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	20%
load	20%
store	20%
mul	16%
add-sub	15%
fma	13%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 33.75 cycles. At this rate:

5% of peak load performance is reached (15.05 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 25c5d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBSD 0x28(%RDI),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD 0x50(%RDI),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMULSD 0x48(%RDI),%XMM0,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 25c6a3 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0xd3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMULSD 0x70(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD 0x78(%RDI),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 25c6e8 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VROUNDSD $0xb,%XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x60(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTTSD2SI %XMM3,%EDX	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	4	0.50	scal (12.5%)
VSUBSD %XMM0,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD -0x58507(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SETG %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %EDX,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
MOVSXD %ECX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,%XMM0,%XMM0{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD 0x98(%RDI),%XMM2,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM2,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JB 25c701 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x131>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VROUNDSD $0xb,%XMM3,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x88(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTTSD2SI %XMM3,%EDX	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	4	0.50	scal (12.5%)
VSUBSD %XMM2,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD -0x58551(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SETG %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %EDX,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
MOVSXD %ECX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JMP 25c703 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x133>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VROUNDSD $0xb,%XMM1,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTTSD2SI %XMM1,%EDX	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	4	0.50	scal (12.5%)
VSUBSD %XMM4,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD -0x58584(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SETG %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVG %EDX,%ECX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
KMOVD %EAX,%K1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	N/A
MOVSXD %ECX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM4,%XMM1,%XMM1{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD 0x70(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD 0x78(%RDI),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 25c626 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x56>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMULSD 0x98(%RDI),%XMM2,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VUCOMISD %XMM2,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JAE 25c66d <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSD -0x5847b(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x58543(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x5854b(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM1,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VBLENDPD $0x1,%XMM5,%XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (25.0%)
VMULPD %XMM5,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD -0x57efd(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VUNPCKLPD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VADDPD %XMM5,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VFMADD213PD -0x57fdf(%RIP),%XMM11,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVAPD %XMM9,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM9,%XMM3,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM3,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM7,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM9,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
TEST %R8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 25d112 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0xb42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD %XMM4,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x20(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%R8,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R8,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD -0x58629(%RIP),%XMM0,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM7,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM3,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD -0x586d8(%RIP),%XMM7,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD -0x5868d(%RIP),%XMM8,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM3,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM1,%XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VSUBSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM9,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBLENDPD $0x1,%XMM4,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (25.0%)
VMULPD %XMM4,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM4,%XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VSUBSD %XMM7,%XMM3,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD213SD %XMM3,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VADDPD %XMM5,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VUNPCKLPD %XMM0,%XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VMULPD %XMM4,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VMULSD %XMM2,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBLENDPD $0x4,%YMM2,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (50.0%)
VBROADCASTF128 -0x580fc(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	vect (25.0%)
VBLENDPD $0x8,%YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (50.0%)
VPERM2F128 $0x20,%YMM0,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x2,%YMM0,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %ZMM0,0xc0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VBLENDPD $0x8,%YMM0,%YMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	1	0.50	vect (50.0%)
VMOVAPD %ZMM2,0x100(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPD %YMM0,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2f6df0 <@plt_start@+0x1b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R13),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2(%R13),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x3(%R13),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RBX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R12,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVAPD 0x100(%RSP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBROADCASTSD -0x58752(%RIP),%ZMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x58694(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD 0xc0(%RSP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x160(%RSP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x78(%RSP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x80(%RSP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x88(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%R12	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL %RBX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (,%R13,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R15,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPERMPD %ZMM6,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMPD %ZMM5,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VBROADCASTSD %XMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPERMPD $0x55,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPERMPD $-0x56,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPERMPD $-0x1,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL 0x20(%RSP),%RCX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
LEA 0x8(,%RAX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA (%R9,%RCX,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%RCX,%R13,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R10,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RSI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R8,%R15,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R10,%R15,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RSI,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x18(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x10(,%R15,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(,%R15,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RSI,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RSI,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RSI,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RCX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,0x68(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RCX,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RCX,0x10(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RCX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R9,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R15,%R9,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R13,%R10,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R15,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RDX,%RBX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%R13,%RBX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 25caeb <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m+0x51b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼void miniqmcreference::MultiBsplineEvalRef::evaluate_v(qmcplusplus::bspline_traits::SplineType const, double, double, double, double, unsigned long)–	25.30	42.07
▼Loop 852 - MultiBsplineRef.hpp:63-71 - exec–	0.00	0.01
○Loop 851 - MultiBsplineRef.hpp:68-70 - exec	6.37	10.54
○Loop 848 - MultiBsplineRef.hpp:68-70 - exec	6.37	10.53
○Loop 850 - MultiBsplineRef.hpp:68-70 - exec	6.28	10.39
○Loop 849 - MultiBsplineRef.hpp:68-70 - exec	6.27	10.36
○Loop 856 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 854 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 859 - MultiBsplineRef.hpp:68-71 - exec	0.00	0.00
○Loop 857 - MultiBsplineRef.hpp:68-71 - exec	0.00	0.00
○Loop 858 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00
○Loop 853 - MultiBsplineRef.hpp:68-71 - exec	0.00	0.00
○Loop 855 - MultiBsplineRef.hpp:68-71 - exec	0.00	0.00
○Loop 860 - MultiBsplineRef.hpp:68-70 - exec	0.00	0.00

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